1672 Dft Jobs - Page 5

Thales people provide armed forces customers with operational advantage at every decisive moment throughout the mission. Defence and armed forces customers rely on us to deliver the full range of defence mission systems solutions at land, sea, and air. Our platforms extend across the battlespace including Above and Sonar, Electronic Combat, and Intelligence, Surveillance and Reconnaissance systems. Technical Lead - Mixed Signal Design Thales India Engineering Competency Center in Bangalore is seeking a Tech Lead Engineer role. In this role you will be responsible for generating reliable, cost effective, customized Electronics systems design, Obsolescence redesign for Defense products to meet the customer requirements as well as governing regulatory standards (DO-160, DO-254, MIL-STD, etc.). You also perform trade analysis of design approaches, engineering simulations modeling, derating analysis before finalizing the design. Qualifications: B.Tech in Electronics Communication or Electrical engineering or equivalent with 8 to 12 years of relevant experience. Higher qualifications of Post-graduation and PhD are desirable. Working experience in Avionics and Defense systems design is desirable Technical Skills and Competencies: Must have strong experience in Product design and development from requirements to Conceptual design to architectural design to detailed design and analysis Must have strong experience in designing low to high power analog electronic boards (for example, power supply, signal processing etc) for Defense / avionics Industry Must have Strong knowledge in Specification, design and verification of electronic boards (including digital functions) Must have strong knowledge of using simulation tools (SPICE, ANSYS etc) for functional simulation signal integrity and power integrity analyses Must have working experience of product performance evaluation (Hardware Verification) and product qualification to comply to DO-160 and DO-254 standards Must have excellent troubleshooting skills on Electrical / Electronic boards to find the root cause and to propose the best solution Should have experience of working with multi-disciplinary team (Mechanical team for thermal analysis enclosures design, PCB layout team and suppliers) Should have an understanding and use of DFMEA, DFT and DFM tools Definition and choice of components (including derating) Definition of electrical schematics and building blocks Boards placeroute (including signal integrity) Manufacturing failures analysis / Root cause analysis Test procedures definition and execution Component obsolescence treatment : alternative solution identification, definition/design of the solution, verification Profile/Skills Analog Electronic Engineering Skills and ability. Mastering of electronic simulation and design software (Cadence, Allegro, ANSYS, PSPICE/LTSPICE) Knowledge or Defense, aeronautics constraints (MIL-STD, DO160, DO254) Design for manufacturing Design for environmental requirements including EMC General understanding of Engineering Development lifecycles including design, development, testing, verification and validation phases

Thales people architect solutions that enable two-thirds of planes to take off and land safely. We create in-flight entertainment systems that engross 50 million fliers every year and we develop the avionics that control the world s largest commercial aircrafts. Our simulators train the next generation of pilots for fighter jets, transporters and search and rescue helicopters. And, together, each and every member of our aerospace team makes a difference.Thales India Engineering Competency Center in Bangalore is seeking a Technical Lead Engineer role to be part of Hardware engineering team. In this role you will be responsible for generating reliable, cost effective, customized Electronics systems design, Obsolescence redesign for avionics products to meet the customer requirements as well as governing regulatory standards (DO-160, DO-254, MIL-STD, etc.). You also perform trade analysis of design approaches, engineering simulations modeling, derating analysis before finalizing the design. Qualifications: B.Tech in Electronics Communication or Electrical engineering or equivalent with 8 to 14 years of relevant experience. Higher qualifications of Post-graduation and PhD are desirable. Working experience in Avionics and Defense systems design is desirable. Technical Skills and Competencies: Must have strong experience in Product design and development from requirements to Conceptual design to architectural design to detailed design and analysis. Must have strong experience in designing low to high power analog electronic boards (for example, power supply, signal processing etc) for avionics Industry. Must have Strong knowledge in Specification, design and verification of electronic boards (including digital functions) Must have strong knowledge of using simulation tools (SPICE, ANSYS etc) for functional simulation signal integrity and power integrity analyses. Must have working experience of product performance evaluation (Hardware Verification) and product qualification to comply to DO-160/MIL-STD/VITA and DO-254 standards. Must have strong knowledge in 10/100/1000 Mbps Ethernet, PCIe DDR2, DDR3, high speed NOR and NAND Flash Interface Must have strong knowledge of using UART RS-232, RS-422, RS-485, I2C, SPI. Should be familiar with Ethernet Interface/PCIe/VME 64/ MIL_STD -1553/ARINC/CAN Must have strong experience in FPGA/Microcontroller based system design. Must have excellent troubleshooting skills on Electrical / Electronic boards to find the root cause and to propose the best solution. Should have experience of working with multi-disciplinary team (Mechanical team for thermal analysis enclosures design, PCB layout team and suppliers) Should have an understanding and use of DFMEA, DFT and DFM tools and approaches. Hands on experience with Signal Integrity process using SIGRITY will be added advantage. Definition and choice of components (including derating) Definition of electrical schematics and building blocks Boards placeroute (including signal integrity) Manufacturing failures analysis / Root cause analysis Test procedures definition and execution. Component obsolescence treatment: alternative solution identification, definition/design of the solution, verification Profile/Skills Analog Electronic Engineering Skills and ability. Mastering of electronic simulation and design software (Cadence, Allegro, ANSYS, PSPICE/LTSPICE) Knowledge or aeronautics and Military/VITA constraints (DO160, MIL-STD and DO254) Design for manufacture. Design for environmental requirements including EMC and high-speed frequency. General understanding of Engineering Development lifecycles including design, development, testing, verification and validation phases

In fast changing markets, customers worldwide rely on Thales. Thales is a business where brilliant people from all over the world come together to share ideas and inspire each other. In aerospace, transportation, defence, security and space, our architects design innovative solutions that make our tomorrows possible. Technical Lead - Mixed Signal Design Thales India Engineering Competency Center in Bangalore is seeking a Senior Engineer role. In this role you will be responsible for generating reliable, cost effective, customized Electronics systems design, Obsolescence redesign for Defense products to meet the customer requirements as well as governing regulatory standards (DO-160, DO-254, MIL-STD, etc.). You also perform trade analysis of design approaches, engineering simulations modeling, derating analysis before finalizing the design. Qualifications: B.Tech in Electronics Communication or Electrical engineering or equivalent with 5 to 8 years of relevant experience. Higher qualifications of Post-graduation and PhD are desirable. Working experience in Avionics and Defense systems design is desirable Technical Skills and Competencies: Must have strong experience in Product design and development from requirements to Conceptual design to architectural design to detailed design and analysis Must have strong experience in designing low to high power analog electronic boards (for example, power supply, signal processing etc) for Defense / avionics Industry Must have Strong knowledge in Specification, design and verification of electronic boards (including digital functions) Must have strong knowledge of using simulation tools (SPICE, ANSYS etc) for functional simulation signal integrity and power integrity analyses Must have working experience of product performance evaluation (Hardware Verification) and product qualification to comply to DO-160 and DO-254 standards Must have excellent troubleshooting skills on Electrical / Electronic boards to find the root cause and to propose the best solution Should have experience of working with multi-disciplinary team (Mechanical team for thermal analysis enclosures design, PCB layout team and suppliers) Should have an understanding and use of DFMEA, DFT and DFM tools Definition and choice of components (including derating) Definition of electrical schematics and building blocks Boards placeroute (including signal integrity) Manufacturing failures analysis / Root cause analysis Test procedures definition and execution Component obsolescence treatment : alternative solution identification, definition/design of the solution, verification Profile/Skills Analog Electronic Engineering Skills and ability. Mastering of electronic simulation and design software (Cadence, Allegro, ANSYS, PSPICE/LTSPICE) Knowledge or Defense, aeronautics constraints (MIL-STD, DO160, DO254) Design for manufacturing Design for environmental requirements including EMC General understanding of Engineering Development lifecycles including design, development, testing, verification and validation phases

DFT Engineers with experience in ATPG, MBIST, post-silicon debug. Tools: TestKompress, VCS RTL Engineers with Verilog, SoC/IP design, PCIe/DDR, Spyglass. Tools: DC, Verdi, Xcelium. Physical Design Engineers with experience in Innovus, STA, 28nm Office cab/shuttle Food allowance Health insurance

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com. Senior Digital Design Engineer - PCIe We are seeking a Senior Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. Key Responsibilities Design and implement high-performance digital solutions, including RTL development and synthesis. Collaborate with cross-functional teams on IP integration for processor IPs and peripherals Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm. Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug. Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification flows Basic Qualifications / Experience Level Bachelor’s in Electronics/Electrical engineering (Master's preferred). 8+ years of digital design experience, with 4+ years focused on processor, peripherals and full chip implementation. Proven expertise in RTL development, synthesis, and timing closure. Experience with front-end design, gate-level simulations, and design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Required Expertise Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advanced nodes ( Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O cycles . Hands-on experience with processor IP (ARM/ARC) Experience of working on PCIe is a must. Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART Hands-on experience with complex DMA engines and FW interaction. Strong proficiency in System Verilog/Verilog and scripting (Python/Perl). Experience with block-level and full-chip design at advanced nodes (≤ 16nm). Silicon bring-up and post-silicon debug experience. Familiarity with industry standard simulation, debug, quality checking and synthesis tools Synopsys/Cadence tools and UVM-based design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Preferred Experience Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation is a plus. Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems Experience of working on PCIe/UAL is a big plus. Understanding of PAD design, DFT, and floor planning. Experience in synthesis, and timing closure is a big plus. Experience with NIC, switch, or storage product development. Familiarity with working in design and verification workflows in a CI/CD environment. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

GLOBAL MNC: Location: Greater Bengaluru Area Our main business focuses on automotive microcontrollers and SoCs. The solutions cover a wide range, such as Edge-ECU to ADAS applications, dedicated to creating a comprehensive solution for automotive chips. It will continue to integrate the latest electronic and electrical architecture (E/EA) designs from automakers, realize the demands of the next-generation software-defined vehicle, and apply a chip design-oriented, human-centric service-oriented architecture (SOA) to the automotive field. This approach aims to meet the diverse needs of users and provide consumers with a new user experience. JOB DESCRIPTION: We are seeking a skilled Design for Test (DFT) Architect/Lead/Manager to join our team. This role is pivotal in ensuring the testability and manufacturability of our ASIC/SoC products designed for the automotive industry. The ideal candidate will have extensive experience in DFT methodologies and will lead a team of engineers to develop robust test strategies that meet industry standards. Key Responsibilities: - DFT Strategy Development: Design and implement DFT methodologies for ASIC/SoC products, focusing on automotive applications to ensure high quality and reliability. - Architecture Design: Collaborate with hardware and software teams to integrate DFT features into the product architecture, ensuring compatibility with automotive testing standards. - Team Leadership: Lead a team of DFT engineers, providing mentorship and technical guidance to enhance their skills and capabilities. - Test Planning: Develop comprehensive test plans, including ATPG, BIST, and scan insertion strategies, to optimize fault coverage and reduce test costs. - Collaboration: Work closely with design, validation, and manufacturing teams to align DFT strategies with overall product goals and requirements. - Quality Assurance: Establish metrics and benchmarks for DFT processes, and ensure compliance with automotive industry standards (e.g., ISO 26262). - Tool Development: Evaluate and implement DFT tools and methodologies to improve test efficiency and effectiveness. - Continuous Improvement: Stay updated with industry trends and technologies in DFT and automotive testing, driving innovation within the team. Qualifications: - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. - 10+ years of experience in DFT for ASIC/SoC design, with a strong background in automotive applications. - Proven experience leading DFT teams and managing complex projects. - In-depth knowledge of DFT techniques such as scan design, boundary scan, BIST, and fault simulation. - Familiarity with automotive industry standards and regulations (e.g., ISO 26262). - Proficiency in using DFT tools and EDA software. - Strong problem-solving skills and ability to work collaboratively in a fast-paced environment. - Excellent communication skills, both verbal and written. Contact: Sumit S. B. Email: sumit@mulyatech.com Mulya Technologies www.mulyatech.com "Mining the Knowledge Community"

Large Semiconductor Service Organization with revenue over 600 Million USD Location: Bangalore Experience : 7+ Years Work location : Bangalore Well versed with the timing closure (STA), timing closure methodologies. Pre/Post-layout constraint development to timing closure. Handshake with the design team and develop functional/DFT constraints. IP level constraint integration. Multi-voltage/Switching aware corner definitions. RC/C model selection understanding. Abstraction expertise like Hyperscale/ILM/ETM. RC Balancing and scaling analysis of full chip clock. RC Balancing and scaling analysis of critical data paths. Good automation skills in PERL, TCL and EDA tool-specific scripting. DMSA @ full chip and custom scripts for timing fixes Qualification: BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design. Detailed knowledge of EDA tools and flows, Tempus/Primetime experience is must. Experience – 7+ years. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Senior Chip Lead /Chip Lead (Sr Director / Director) Hyderabad A Hyderabad based SoC Turnkey design company is looking for a talented, energetic and diligent SoC Director for leading the development of a new generation of devices. Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs in the area of HBM. Job responsibilities include: Driving the specification of the chip with architect and design leads – eventually cascading into block specifications. Make PPA decisions for the chip. Defining multiple development checkpoints – for IP/SoC Design/DV/PD Come up with overall project plan and cascaded schedule details for other teams Work with Analog/Digital IP teams to laydown integration details for the IPs. Drive the full chip floorplan / bump maps and provide area/floorplan targets to IP teams. Define the sign-off criteria for the device. Define the SoC verification plan items/scenarios to be covered. Assist/Review the micro architecture definition for digital blocks Define RTL Quality gate criteria for integration – Lint/CDC/ Drive the timing constraints/timing analysis/closure activities. Define the DFT targets for the chip and cascade that into activities needed on the DFT front. Work with PD enginers to get the physical design closure. Handle tapeout formalities Qualifications: Close to 15 years of solid experience in SoC design. A self starter. Candidate ready to define things where none exist. Ready for once in a lifetime project exposure, but ready to do heavy lifting for the effort. Proven ability to develop architecture and micro-architecture from specifications. Understanding of chip I/O design and packaging is advantageous. Experience in reviewing top-level test plans. Expertise in Synopsys Design Compiler for synthesis and formal verification. Strong working knowledge of timing closure processes. Experience with post-silicon bring-up and debugging. Familiarity with SoC integration challenges. Knowledge of design verification aspects is essential. Experience from SoC specification to GDS and commercialization is highly desired. Ability to make timely and effective decisions, even with incomplete information. Demonstrated expertise in specific technical areas, with significant experience in related fields. Provide direction, mentoring, and leadership to small to medium-sized teams. Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

Technical Director-Mixed Signal IC Design (High level Proficiency and Hand-on ) Top100 Global Semiconductor Organization HQ in California. Revenue over 200 Million USD Location: Bangalore Location: Bangalore, India Desired Education Level: Graduate / Doctorate and above Years of experience: MTech/M.S. with 16+ years of experience or Ph.D. with 13+ years We are a precision timing company. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power and better reliability. With more than 3 billion devices shipped, We are changing the timing industry. . Job Summary Responsibilities: • Lead development of analog Mixed-signal IC and owns the top level • Supervise and review block designer work and hold design review • Work with cross-functional team to architect the chip for DFT • Closely work and support cross functional team for bench validation, qualification and final test development. • Develop analog and mixed-signal architectures and circuits in CMOS or BiCMOS processes • Analyze technology, architecture, circuit design, and parametric design trade-offs to meet aggressive technical performance specifications • Perform transistor-level design and simulation using industry leading EDA tools • Lead comprehensive design reviews • Supervise Analog Circuit Physical Design Layout and edit layouts • Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test Engineering and Applications teams to ensure DFT, DFM features and achieve rapid silicon bring-up and time to production release • Work closely with the verification team to define the verification matrix. • Have the ownership of the top-level schematic and run all the top-level analog simulation. • Participate in top-level AMS verification. Qualifications & Requirements (Education must be included): • MTech/M.S. with minimum 10 years of relevant experience or Ph.D. with 6 years of Relevant experience in Electrical Engineering • Provel track record of taking at least one analog-mixed signal part to high-volume production. • Proven track record at each stage of the following: • Circuit architecture development and technical feasibility studies • Writing detailed block-level specifications and review documents • Detailed design and simulation of some of the following: Oscillators, ADCs, DACs, temperature sensors, Integer and Fractional-N PLLs, Digital PLLs, low-noise op-amps, regulators, bandgap circuits in CMOS or BiCMOS processes, subthreshold circuits and architecture • Proficiency with EDA tools including Cadence Virtuoso, Spectre, ADE, Mixed-mode AMS tools, Layout XL • Extensive knowledge of layout effects for circuit and layout design. Ability to supervise layout designers • Extensive experience with post-layout extraction and verifications • Experience with validation, characterization, qualification, and adherence to production release criteria • Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital, verifications engineers • Ability to work independently and drive solutions to challenging problems Desired Characteristics & Attributes: • An “ownership” mind set focusing on the overall success of the business. • Can do” positive, enthusiastic attitude. • Demonstrated analytical and problem-solving skills. • Strong communication skills. • Ability to work in teams and collaborate effectively with people in different functions. • Ability to efficiently context – switch between multiple concurrent tasks. We are a Equal Opportunity Employer. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Job Description Job Description Overview As a leading global aerospace company, Boeing develops, manufactures, and services commercial airplanes, defense products and space systems for customers in more than 150 countries. As a top U.S. exporter, the company leverages the talents of a global supplier base to advance economic opportunity, sustainability, and community impact. Boeing's team is committed to innovating for the future, leading with sustainability, and cultivating a culture based on the company's core values of safety, quality, and integrity. Technology for today and tomorrow The Boeing India Engineering & Technology Center (BIETC) is a 5500+ engineering workforce that contributes to global aerospace growth. Our engineers deliver cutting-edge R&D, innovation, and high-quality engineering work in global markets, and leverage new-age technologies such as AI/ML, IIoT, Cloud, Model-Based Engineering, and Additive Manufacturing, shaping the future of aerospace. People-driven culture At Boeing, we believe creativity and innovation thrives when every employee is trusted, empowered, and has the flexibility to choose, grow, learn, and explore. We offer variable arrangements depending upon business and customer needs, and professional pursuits that offer greater flexibility in the way our people work. We also believe that collaboration, frequent team engagements, and face-to-face meetings bring Inclusive perspectives and thoughts - enabling every voice to be heard and every perspective to be respected. No matter where or how our teammates work, we are committed to positively shaping people's careers and being thoughtful about employee wellbeing. At Boeing, we are inclusive and transformative. With us, you can create and contribute to what matters most in your career, community, country, and world. Join us in powering the progress of global aerospace. Boeing India Engineering has an immediate opening for an Engineering Manager - Digital Circuits who will be responsible for development and management of engineers in India to perform engineering work-statements for Boeing product life cycle management. This position will work collaboratively with teams from across the globe in an integrated design environment to help deliver an engineering statement of work. The selected individual will develop and handle Engineers, interact with the program leaders from across the globe, with a vision to grow ownership in execution with their team. This position will be in Bengaluru, India , and will be reporting directly to the Sr. Electronic Manager, India. Primary Responsibilities: Manage employees performing engineering and technical activities in the areas of ASIC/FPGA verification and design. Develops and executes integrated departmental plans, policies and procedures and provides input on departmental business and technical strategies, goals, objectives. Acquires resources for department activities, provides technical management of suppliers and leads process improvements. Develops and maintains relationships and partnerships with customers, stakeholders, peers, partners and direct reports. Provides oversight and approval of technical approaches, products and processes. Provides project/Activity planning, and key milestone tracking. Manages post silicon debug support activities for validation, SW development and Test Team. Manages directly (including people reporting) the RTL, DV and DFT primarily. Integrated PD and Emulation activities Understand complex protocols and create implementable objectives for team, Protocols would include PCIe, ARINC, MIL 1553, USB, I2C and other proprietary protocols related to space and flight systems Manages, develops and motivates employees along with functional capability planning. Build capability and capacity upon SV & UVM. Nurture directed test case scenarios using VHDL and similar platforms. Should have strong verbal and written communication skills. Basic Qualifications (Required skills/experience): Bachelor's degree or higher is required At least 12 years of experience in Digital IC design and verification, involved in at least 3 Chip Tape outs or equivalents. Proficient in tools such as Vmanager and similar tools with other EDA vendors to track and maintain verification workflow metrics for the team. Proficient in concepts such as cross domain clock sync, polymorphism. Proficient in validating the verification workflow with available limitations on tools and resources to provide maximum functional coverage on priority. Demonstrated success leading development efforts, including project management and earned value tracking. Preferred Qualifications (Desired skills/experience): Experience leading or managing in an engineering organization. Familiarity with FAA DO-254 certification. Familiar with Emulation and Safety Flow Analysis Familiar in Formal Verification techniques Familiar in Design Concepts US Person as defined by 22 C.F.R 120.15 is advantageous. Familiar with LOR verification based VCRM structure Typical Education & Experience: Education/experience typically acquired through advanced education (e.g. Bachelor) and typically 13 to 16 years related work experience or an equivalent combination of education and experience (e.g. Master+12 years of related work experience etc.) Applications for this position will be accepted until Sept. 13, 2025 Export Control Requirements: This is not an Export Control position. Education Bachelor's Degree or Equivalent Required Relocation This position offers relocation based on candidate eligibility. Visa Sponsorship Employer will not sponsor applicants for employment visa status. Shift Not a Shift Worker (India) Equal Opportunity Employer: We are an equal opportunity employer. We do not accept unlawful discrimination in our recruitment or employment practices on any grounds including but not limited to race, color, ethnicity, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military and veteran status, or other characteristics covered by applicable law. We have teams in more than 65 countries, and each person plays a role in helping us become one of the world's most innovative, diverse and inclusive companies. We are proud members of the and welcome applications from candidates with disabilities. Applicants are encouraged to share with our recruitment team any accommodations required during the recruitment process. Accommodations may include but are not limited to: conducting interviews in accessible locations that accommodate mobility needs, encouraging candidates to bring and use any existing assistive technology such as screen readers and offering flexible interview formats such as virtual or phone interviews.

Job Description At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us. Overview As a leading global aerospace company, Boeing develops, manufactures, and services commercial airplanes, defense products and space systems for customers in more than 150 countries. As a top U.S. exporter, the company leverages the talents of a global supplier base to advance economic opportunity, sustainability, and community impact. Boeing’s team is committed to innovating for the future, leading with sustainability, and cultivating a culture based on the company’s core values of safety, quality, and integrity. Technology for today and tomorrow The Boeing India Engineering & Technology Center (BIETC) is a 5500+ engineering workforce that contributes to global aerospace growth. Our engineers deliver cutting-edge R&D, innovation, and high-quality engineering work in global markets, and leverage new-age technologies such as AI/ML, IIoT, Cloud, Model-Based Engineering, and Additive Manufacturing, shaping the future of aerospace. People-driven culture At Boeing, we believe creativity and innovation thrives when every employee is trusted, empowered, and has the flexibility to choose, grow, learn, and explore. We offer variable arrangements depending upon business and customer needs, and professional pursuits that offer greater flexibility in the way our people work. We also believe that collaboration, frequent team engagements, and face-to-face meetings bring Inclusive perspectives and thoughts – enabling every voice to be heard and every perspective to be respected. No matter where or how our teammates work, we are committed to positively shaping people’s careers and being thoughtful about employee wellbeing. At Boeing, we are inclusive and transformative. With us, you can create and contribute to what matters most in your career, community, country, and world. Join us in powering the progress of global aerospace. Boeing India Engineering has an immediate opening for an Engineering Manager - Digital Circuits who will be responsible for development and management of engineers in India to perform engineering work-statements for Boeing product life cycle management. This position will work collaboratively with teams from across the globe in an integrated design environment to help deliver an engineering statement of work. The selected individual will develop and handle Engineers, interact with the program leaders from across the globe, with a vision to grow ownership in execution with their team. This position will be in Bengaluru, India , and will be reporting directly to the Sr. Electronic Manager, India. Primary Responsibilities: Manage employees performing engineering and technical activities in the areas of ASIC/FPGA verification and design. Develops and executes integrated departmental plans, policies and procedures and provides input on departmental business and technical strategies, goals, objectives. Acquires resources for department activities, provides technical management of suppliers and leads process improvements. Develops and maintains relationships and partnerships with customers, stakeholders, peers, partners and direct reports. Provides oversight and approval of technical approaches, products and processes. Provides project/Activity planning, and key milestone tracking. Manages post silicon debug support activities for validation, SW development and Test Team. Manages directly (including people reporting) the RTL, DV and DFT primarily. Integrated PD and Emulation activities Understand complex protocols and create implementable objectives for team, Protocols would include PCIe, ARINC, MIL 1553, USB, I2C and other proprietary protocols related to space and flight systems Manages, develops and motivates employees along with functional capability planning. Build capability and capacity upon SV & UVM. Nurture directed test case scenarios using VHDL and similar platforms. Should have strong verbal and written communication skills. Basic Qualifications (Required skills/experience): Bachelor’s degree or higher is required At least 12 years of experience in Digital IC design and verification, involved in at least 3 Chip Tape outs or equivalents. Proficient in tools such as Vmanager and similar tools with other EDA vendors to track and maintain verification workflow metrics for the team. Proficient in concepts such as cross domain clock sync, polymorphism. Proficient in validating the verification workflow with available limitations on tools and resources to provide maximum functional coverage on priority. Demonstrated success leading development efforts, including project management and earned value tracking. Preferred Qualifications (Desired skills/experience): Experience leading or managing in an engineering organization. Familiarity with FAA DO-254 certification. Familiar with Emulation and Safety Flow Analysis Familiar in Formal Verification techniques Familiar in Design Concepts US Person as defined by 22 C.F.R 120.15 is advantageous. Familiar with LOR verification based VCRM structure Typical Education & Experience: Education/experience typically acquired through advanced education (e.g. Bachelor) and typically 13 to 16 years' related work experience or an equivalent combination of education and experience (e.g. Master+12 years of related work experience etc.) Applications for this position will be accepted until Sept. 13, 2025 Export Control Requirements: This is not an Export Control position. Education Bachelor's Degree or Equivalent Required Relocation This position offers relocation based on candidate eligibility. Visa Sponsorship Employer will not sponsor applicants for employment visa status. Shift Not a Shift Worker (India) Equal Opportunity Employer: We are an equal opportunity employer. We do not accept unlawful discrimination in our recruitment or employment practices on any grounds including but not limited to; race, color, ethnicity, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military and veteran status, or other characteristics covered by applicable law. We have teams in more than 65 countries, and each person plays a role in helping us become one of the world’s most innovative, diverse and inclusive companies. We are proud members of the Valuable 500 and welcome applications from candidates with disabilities. Applicants are encouraged to share with our recruitment team any accommodations required during the recruitment process. Accommodations may include but are not limited to: conducting interviews in accessible locations that accommodate mobility needs, encouraging candidates to bring and use any existing assistive technology such as screen readers and offering flexible interview formats such as virtual or phone interviews.

Role: PCB Design Engineer Experience: 4-5 Years Job Location: Faridabad Job Type: Full time Position Overview: We are looking for an experienced PCB Design Engineer skilled in Allegro and Xpedition, with strong expertise in high-speed PCB layout, schematic interpretation, and manufacturing standards. This role involves designing complex layouts, ensuring signal and power integrity, and collaborating closely with manufacturing teams. Ideal candidates are detail-oriented, proactive, and committed to high-precision designs. Roles and Responsibilities: • Expertise in using ECAD tools such as Allegro/Xpedition software. • Understand and analyse technical Requirements and Customer input to execute Layout Engineering. • Experience in designing Layout for motherboards using Intel, AMD, NXP, TI processors is big plus. • Understanding the design guidelines from PDG and implementation is big plus. • Very good knowledge of relevant IPC design standards for Library creation, PCB design and Schematic Entry. • PCB layout placement with a strong background dealing with analog, digital, power, and high-speed circuitry. • Experience in high-speed net routing and usage of blind & buried vias. • Knowledge of tab routing is plus. • Experience in physical, spacing, and electrical constraint settings. • Should be able to understand and read schematics independently. • Should have awareness of Signal Integrity and Power Integrity concepts for PCB Design. • Should work with PCB manufacturers and PCB assembly houses to understand manufacturing rules. • Self-motivated, able to work independently with minimal supervision. • Experience in documentation regarding PCB Guidelines, Processes, Checklists. • Knowledge and understanding of thermal impact for the design placement. • Good expertise in DFM, DFA, DFS and DFT analysis. • Gerber, ODB++ generation and review. Requirements: • Proficient with PCB Design and schematic creation in Allegro/Expedition. • Skilled in researching and reading manufacturing datasheets, able to find and extract pertinent information for symbols and footprints. • Experienced in high pin count, fine pitch parts, QFN modules: BGAs, connectors, power modules, heatsinks/clips, SFF-TA-XXX specifications, and connectors. • Knowledgeable in PCB layout guidelines and standards, background in PCB layout design is highly desirable. • Must have timely response, take pride in high level of accuracy and precision, and great attention to details. • Self-motivated team player, flexible and ready to adapt to varying workloads and task requirements.

Role Overview We are looking for a Senior CAD Engineer to deploy and support our front end tools, to develop scripts to automate regression and debug flows, to work along with our design, implementation and verification teams. What you'll do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What you need to have B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics) 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks

The ASIC Design Senior Engineer plays a critical role in the development and implementation of advanced integrated circuit designs within the organization. You will be instrumental in driving innovation and ensuring that the products maintain a competitive edge in the rapidly evolving semiconductor industry. Your responsibilities will include contributing technical expertise and leadership in the ASIC design process, from initial concept through to production. Working collaboratively with cross-functional teams, you will solve complex design challenges, optimize performance, and ensure adherence to industry standards. In addition to deep technical knowledge, this role will require the ability to mentor junior engineers and lead project initiatives. Your strong background in digital and analog design, along with a proven track record of delivering projects on time and within budget, will be essential in shaping the future of the technology solutions and impacting the company's success. Key Responsibilities: - Design and validate complex ASICs in accordance with specifications. - Develop RTL using Verilog/System Verilog for various digital components. - Conduct simulation and verification of designs using advanced methodologies. - Execute timing analysis and optimization to meet performance requirements. - Collaborate with cross-functional teams including hardware, software, and test engineering. - Perform power estimation and drive strategies for low-power design. - Oversee the transition from design to tape-out and ensure compliance with DFT standards. - Mentorship and training of junior engineers and interns in design practices. - Participate in design reviews and provide constructive feedback. - Address and resolve design-related issues throughout the lifecycle. - Communicate effectively with project managers to ensure timelines are met. - Document design processes and maintain accurate design records. - Utilize FPGA devices for prototyping and testing of ASIC functionalities. - Research and implement new design tools and methodologies. - Keep updated with industry trends and advancements in ASIC technology. Required Qualifications: - Bachelor's or Master's degree in Electrical Engineering or related field. - Minimum of 5 years of experience in ASIC design and development. - Strong experience with digital circuit design and verification methodologies. - Proficient in Verilog and System Verilog programming. - Hands-on experience with tools such as Cadence, Synopsys, and Mentor Graphics. - Familiarity with FPGA development and prototyping techniques. - Demonstrated experience in timing closure and power optimization. - Solid understanding of DFT concepts and techniques. - Ability to mentor junior engineers and lead design projects. - Excellent problem-solving and analytical skills. - Strong communication skills, both verbal and written. - Ability to work collaboratively in a fast-paced environment. - Knowledge of industry standards and best practices in ASIC design. - Experience with scripting languages such as Perl or Python is a plus. - Strong organizational skills and attention to detail. - Demonstrated track record of successful project delivery. Skills: system verilog, problem solving, simulation and verification, power optimization, DFT, timing analysis, schematic capture, FPGA development, low-power design, DFT standards, SoC, scripting languages (Perl, Python), Verilog, digital circuit design, RTL coding, ASIC design, power estimation.,

Senior Chip Lead /Chip Lead (Sr Director / Director) Hyderabad A Hyderabad based SoC Turnkey design company is looking for a talented, energetic and diligent SoC Director for leading the development of a new generation of devices. Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs in the area of HBM. Job responsibilities include: Driving the specification of the chip with architect and design leads – eventually cascading into block specifications. Make PPA decisions for the chip. Defining multiple development checkpoints – for IP/SoC Design/DV/PD Come up with overall project plan and cascaded schedule details for other teams Work with Analog/Digital IP teams to laydown integration details for the IPs. Drive the full chip floorplan / bump maps and provide area/floorplan targets to IP teams. Define the sign-off criteria for the device. Define the SoC verification plan items/scenarios to be covered. Assist/Review the micro architecture definition for digital blocks Define RTL Quality gate criteria for integration – Lint/CDC/ Drive the timing constraints/timing analysis/closure activities. Define the DFT targets for the chip and cascade that into activities needed on the DFT front. Work with PD enginers to get the physical design closure. Handle tapeout formalities Qualifications: Close to 15 years of solid experience in SoC design. A self starter. Candidate ready to define things where none exist. Ready for once in a lifetime project exposure, but ready to do heavy lifting for the effort. Proven ability to develop architecture and micro-architecture from specifications. Understanding of chip I/O design and packaging is advantageous. Experience in reviewing top-level test plans. Expertise in Synopsys Design Compiler for synthesis and formal verification. Strong working knowledge of timing closure processes. Experience with post-silicon bring-up and debugging. Familiarity with SoC integration challenges. Knowledge of design verification aspects is essential. Experience from SoC specification to GDS and commercialization is highly desired. Ability to make timely and effective decisions, even with incomplete information. Demonstrated expertise in specific technical areas, with significant experience in related fields. Provide direction, mentoring, and leadership to small to medium-sized teams. Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

Principal / Staff IP/RTL Design Engineer (AI Accelerator) – Multiple positions - Hyderabad Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Well-funded product startup is looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. In this role you will collaborate with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures. We are seeking highly experienced individuals who have a passion for innovation and are excited about the opportunity to create world class products from India. The key responsibilities for this role include, but are not limited to: Key Responsibilities Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL. Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure. Optimize design for power, performance, and area (PPA). Interface with physical design and DFT (Design for Test) engineers for seamless integration. Drive design reviews, write design documentation, and support post silicon bring-up/debug. Minimum Qualifications B.S./M.S./Ph.D. in ECE/CS from top engineering college with 5-15 years of related experience. Previous experience in either high performance processor design or AI accelerator design is plus. Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts. Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design. Proficiency in Verilog/SystemVerilog and simulation tools. Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills. Job Qualifications: BE/BTech/ME/MTech- Computer Science or others Required Skills Develop reliable, scalable, and high-performance Modus DFT software that is easy to use. Develop software tools in C/C++ to support DFT and ATPG. Research and develop software solutions to allow greater efficiency in architecture, hardware, and software teams. Development environment is C++ on Unix in multi-threaded environment with expertise in C++, data-structure and algorithms. Strong knowledge of Tcl is preferred Experience in language compiler Prior experience with large software development projects is highly recommended.

STA and Timing closure of Infineon SoCs targeted for IoT and MCU markets. Job Description Responsible for leading STA and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets. Key contribution to timing sign-off methodology development for lower technology nodes (22nm and beyond). Ownership of constraints development for functional/test modes at pre and post layout stage. Opportunity to work on IO timing closure for critical interfaces like Serial Peripherals and External Memory Interfaces. Timing analysis and convergence of large hierarchical design across multiple modes and corners. Interact with RTL and DFT teams on timing feasibility and performance assessment. Work closely with physical design team for timing/SI closure Your Profile B.Tech or M.Tech relevant work experience and specialization in VLSI design. Strong hands-on technical experience in constraints development, timing analysis/closure of SoCs. Experience in low-power synthesis and equivalence checks will be a plus. Expert user of industry standard tools for timing signoff. Experience in scripting languages (shell, perl, tcl) and Make flow. Must be well organized, methodical and detail oriented.

Responsibilities As a creative design engineer with a knowledge of subsystems and SoCs you will be part team developing Subsystems & SoCs. You will work with Architects to capture the requirements and develop Micro-architecture specifications for one or more SOC areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc. Key responsibilities will include writing micro-architecture and work with Design team to deliver high quality RTL. Collaborate with verification and Validation team to review test plans, and help debug design issues. Closely work with the Power and Performance analysis team to evaluate and improve Subsystem/SOC PPA. Contribute to developing and improving the design methodologies. Guide and support other members of the team for overall Program success. Balance other opportunities such as working with Project Management on activities, plans, and schedules Required Skills and Experience: Bachelors or Master s degree or equivalent experience in Electronics/Electrical Engineering. Experience of 8+ years working in design of complex compute subsystems or SoCs Expertise in developing Micro-architecture and Design specifications for the SoC Infrastructure areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc. Solid understanding of digital hardware design and Verilog HDL. Experience in development and Tapeout of Complex SoC and RTL Development. Experience leading and developing RTL for Subsystems or SoCs. Conversant with Lint, CDC and RDC flows. Good communication (written, verbal, presentations) skills. Experience with Perl, Python or other scripting language Desired Skills and Experience: Experience with ARM-based designs and/or ARM System Architectures Experience developing subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet Experience with SystemVerilog and verification methodologies UVM/OVM Experience leading small teams or projects Experience or knowledge in the following areas Synthesis and timing analysis Static design checks, including CDC, RDC, X-Propagation, Linting Power management techniques DFT and physical implementation Accommodations at Arm At Arm, we want to build extraordinary teams. . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Apply Save Job View location Our Hiring Process

Responsible for SoC DFT Architecture definition / implementation / verification / silicon debug of SoC/Full Chip. Job Description In your new role you will: Responsible for SoC DFT Architecture definition / implementation / verification / silicon debug of SoC/Full Chip. Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification. Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at / TDF / Bridging / Cell-aware / iddq fault models. Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations. Hands on experience in analysis and debug of above-mentioned test domains. Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out.

Experienced in generating top-level functional vectors for IPs used in production and characterization testing. Skilled in SystemVerilog and SoC-level verification with a strong ability to debug tester failures. Possesses solid analytical and debugging skills, along with foundational knowledge in Verilog/VHDL design techniques and simulation flows. Familiar with UVM methodology and basic Perl scripting. Job Description Responsible for generating top-level functional vectors for IP s for production and Char testing. Knowledge of System Verilog. Experience with SOC level verification. Experience in Tester failure debugs. Excellent analytical and debugging skills . Basic knowledge in design techniques Verilog or VHDL. A good knowledge of simulation flow. UVM knowledge a plus. Perl basics a plus. Your Profile You are best equipped for this task if you have: ASIC flow understanding. The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the vectors, verification, and Post silicon debug . In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies . The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in?

Job Responsibilities: The role s day to day responsibilities cover: RD support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills. Job Qualifications: BE/BTech/ME/MTech- Computer Science or others Required Skills Develop reliable, scalable, and high-performance Modus DFT software that is easy to use. Develop software tools in C/C++ to support DFT and ATPG. Research and develop software solutions to allow greater efficiency in architecture, hardware, and software teams. Development environment is C++ on Unix in multi-threaded environment with expertise in C++, data-structure and algorithms. Strong knowledge of Tcl is preferred Experience in language compiler Prior experience with large software development projects is highly recommended. .

Job Responsibilities: The role s day to day responsibilities cover: RD support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills. Job Qualifications: BE/BTech/ME/MTech- Computer Science or others Required Skills Develop reliable, scalable, and high-performance Modus DFT software that is easy to use. Develop software tools in C/C++ to support DFT and ATPG. Research and develop software solutions to allow greater efficiency in architecture, hardware, and software teams. Development environment is C++ on Unix in multi-threaded environment with expertise in C++, data-structure and algorithms. Strong knowledge of Tcl is preferred Experience in language compiler Prior experience with large software development projects is highly recommended. .

Job Requirements Job Summary: We are seeking an experienced RTL Technical Lead Engineer to take ownership of RTL design and provide technical direction for complex digital blocks or SoCs. The ideal candidate will combine deep design expertise with leadership and cross-functional collaboration skills. Key Responsibilities: Lead RTL design and micro-architecture development for IP/SoC components. Translate design specifications into efficient and high-quality RTL code (Verilog/SystemVerilog).Drive technical reviews, architecture discussions, and RTL delivery schedules. Interface with verification, synthesis, DFT, and physical design teams. Ensure design quality through lint, CDC, and synthesis checks. Guide and mentor junior engineers and review their work. Debug design issues and support integration and bring-up. Preferred: Experience in low-power design, multi-clock domains, and power intent (UPF).Familiarity with industry standards like PCIe, USB, DDR, Ethernet, etc.Prior experience as a technical lead or team coordinator. Work Experience Required Skills and Experienc e: 9+ years of hands-on RTL design experience in the semiconductor/VLSI industry. Strong expertise in Verilog/System Verilog and digital design fundamentals. Good understanding of SoC integration, bus protocols (AXI, AHB), and timing constraints. Experience with tools like Synopsys/VCS, Spy Glass, Design Compiler, and Prime Time. Strong analytical and problem-solving skills.

Job Title: DFT Design Engineer Location: Bengaluru Experience Required: 12+ Years Employment Type: Full-Time Role Overview We are seeking a DFT (Design-for-Test) Lead to define, develop, and optimize DFT methodologies for our advanced LiDAR SoCs. This role will lead DFT strategy and execution, ensuring high performance and automotive-grade quality in silicon designs. Key Responsibilities Define, develop, and implement DFT methodologies for high-performance LiDAR SoCs. Lead DFT planning, insertion, verification, and validation processes. Collaborate with RTL, Physical Design teams, IP vendors, and ASIC vendors to ensure robust test implementation. Support post-silicon bring-up, debug, failure analysis, and yield improvement activities. Create and maintain DFT documentation, guidelines, and architecture specifications . Required Skills & Experience 12+ years of hands-on experience in DFT architecture and test strategies for complex ASIC/SoC designs. Strong expertise in SCAN/ATPG, MBIST, LBIST, JTAG (IEEE 1149.x/1500/1687), Boundary Scan, compression/decompression technologies for digital and mixed-signal SoCs. In-depth knowledge of EDA tools (Mentor, Synopsys) . Proficiency in scripting languages (Python, PERL, TCL). Experience with RTL coding and SDC creation for DFT modes. Recent tapeout experience in advanced technology nodes. Nice to Have Familiarity with automotive-grade silicon development (AEC-Q100, ISO26262 compliance).