1672 Dft Jobs - Page 7

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking a Senior Staff Verification Engineer to lead and contribute to the functional verification of complex SoC and IP designs for next-generation AI, HPC, and data center products. The ideal candidate has extensive experience in UVM/SystemVerilog , SoC and IP-level verification, and is passionate about ensuring first-pass silicon success . This role involves defining verification strategies, developing scalable environments, and collaborating cross-functionally with architecture, design, and software teams. Experience with Virtual Modeling, SystemC, and TLM is a plus , enabling advanced verification and early system-level validation. Qualifications Education & Experience B.S./M.S. in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience in IP/SoC verification with a proven track record of successful silicon delivery. Technical Expertise Deep knowledge of UVM/SystemVerilog for testbench development and verification IP integration. Strong understanding of SoC architecture and protocols such as DDR5, HBM3, PCIe Gen6, CXL 3.0, and other high-speed interfaces. Expertise in coverage-driven verification, constrained-random testing, and assertion-based verification. Proficient in debugging RTL, testbenches, and simulation failures using industry-standard tools. Tools & Languages Hands-on experience with simulation tools (VCS, Xcelium, Questa, etc.), waveform viewers, coverage tools, and automation scripting (Python, Perl, TCL). Preferred/Additional Skills Virtual Modeling and System-Level Verification Familiarity with SystemC and Transaction-Level Modeling (TLM) for virtual prototyping and early system validation. Experience developing or using virtual platforms for hardware/software co-verification is a strong plus. Emulation & Prototyping Exposure to emulation platforms (Palladium, ZeBu) and FPGA-based prototyping for system-level validation and performance analysis. Software Co-verification Experience working alongside firmware/software teams for pre-silicon software validation and early driver/OS bring-up. Low-Power and DFT Verification Knowledge of power-aware verification (UPF/CPF) and DFT validation methodologies is desirable. Key Responsibilities Verification Planning & Execution Lead the definition, development, and execution of comprehensive verification plans at IP and SoC levels. Develop UVM/SystemVerilog-based testbenches, including stimulus generation, checkers, and monitors for advanced SoC designs. Drive coverage-driven verification processes, ensuring functional and code coverage goals are met. Cross-Functional Collaboration Collaborate with architecture, RTL design, firmware, software, and emulation teams to define verification requirements and ensure comprehensive test coverage. Participate in design and architecture reviews, providing critical feedback on functionality, testability, and performance considerations. Debug & Issue Resolution Lead debug efforts on complex SoC and IP issues through simulation, emulation, and FPGA prototypes. Perform root-cause analysis and drive issues to closure in partnership with cross-disciplinary teams. Methodology & Infrastructure Development Enhance and maintain verification methodologies, including reusable verification IP, automation scripts, and regression infrastructure. Evaluate and adopt new tools and verification technologies to improve quality and efficiency. Leadership & Mentorship Provide technical guidance and mentorship to junior verification engineers. Lead verification reviews and strategy discussions, ensuring high technical standards and best practices. Additional Information Renesas Electronics Corporation empowers a safer, smarter and more sustainable future where technology helps make our lives easier. The leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at www.renesas.com. Renesas’ mission, To Make Our Lives Easier, is underpinned by our company culture, TAGIE. TAGIE stands for Transparent, Agile, Global, Innovative and Entrepreneurial. Our goal is to embed this unique culture in everything we do to succeed as a company and create trust with our diverse colleagues, customers and stakeholders. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas Electronics Corporation empowers a safer, smarter and more sustainable future where technology helps make our lives easier. The leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at www.renesas.com. Renesas’ mission, To Make Our Lives Easier, is underpinned by our company culture, TAGIE. TAGIE stands for Transparent, Agile, Global, Innovative and Entrepreneurial. Our goal is to embed this unique culture in everything we do to succeed as a company and create trust with our diverse colleagues, customers and stakeholders. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT . Experience: 1-3 Years .

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT . Experience: 3-5 Years .

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

Serving as the primary technical point of contact for customers, guiding them in deploying Synopsys DFT (Design for Test) technologies on their designs. Planning, directing, and executing project schedules while coordinating cross-functional activities across internal teams and customer organizations. Identifying project risks, developing contingency plans, and ensuring timely escalation and resolution of issues. Collaborating closely with Sales, Marketing, Applications Engineering, and R&D teams to deliver tailored solutions that meet customer requirements. Demonstrating, coaching, and supporting customers with the latest DFT flows, methodologies, and toolsets to enable high-quality, on-time silicon delivery. Managing multiple concurrent projects, ensuring high standards of quality and customer satisfaction throughout the engagement lifecycle. Documenting best practices, process improvements, and technical learnings to foster knowledge sharing within the team and organization. The Impact You Will Have: Empowering customers to achieve faster time-to-market and enhanced product quality through state-of-the-art DFT solutions. Strengthening Synopsys reputation as a trusted technology partner by delivering exceptional customer support and technical guidance. Driving successful adoption of Synopsys DFT tools and methodologies, contributing to the success of key internal and external programs. Facilitating seamless communication and collaboration across global, cross-functional teams, ensuring project goals are met efficiently. Identifying opportunities for process optimization, innovation, and continuous improvement within customer engagements and internal workflows. Enabling the development of high-performance, reliable silicon chips that power the next generation of intelligent devices

Define and drive netlist-level power estimation methodologies using industry-leading tools (e.g., Synopsys PrimeTime PX, Cadence Voltus). Establish and maintain correlation frameworks between RTL and gate-level power, and between estimated and silicon power. Develop automated flows for toggling activity generation, vector-based and vectorless power estimation, and regression reporting. Analyze power consumption trends and identify hotspots; provide recommendations for low-power design optimization. Collaborate with RTL design, physical design, DFT, and architecture teams to ensure early and accurate power signoff. Lead methodology development for corner analysis, dynamic/static power separation, and voltage scaling assessments. Support signoff reviews, audits, and compliance to power specifications and constraints. Provide mentorship and technical leadership within the team and across global sites

RESPONSIBILITIES:Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checksEnsuring timing correlation between PnR STA and timely feedbacks to PD teamGenerating block level HS session and using Top context from SoC for Block-SoC Interface timing closure Generating timing ECO using Tweaker/PrimeClosure

In your new role you will: Develop and implement Design for Test (DFT) methodologies for IoT products. Collaborate with design and backend teams to integrate DFT features . Create and validate test plans to ensure thorough coverage and fault detection. Support silicon bring-up and debug activities. Automate test processes such as ATPG/MBIST to enhance efficiency and accuracy. Test coverage analysis and improve test coverage to sign-off IJTAG cores, SoC. Your Profile You are best equipped for this task if you have: Bachelors in Electrical & Electronics/ECE or master s degree in VLSI. 4+ years of experience in DFT, ASIC design. Experience with DFT tools such as Tessent, Genus and Validation with Questa, Xcelium tools preferred. Solid understanding of digital design concepts and Simulations. Strong analytical and problem-solving skills. Good communication and teamwork skills

Job Title: Sr Staff DFT Engineer Job Location: Bangalore, India ( This position requires a full-time, on-site presence in our Bangalore, India office ) Job ID: AI2435 Key Responsibilities: Block-level and sub-system DFT micro-architecture including SCAN, MBIST, IP tests, JTAG Develop and execute test insertion flow for scan, MBIST, JTAG Estimate and achieve targeted test coverage. Run RTL and gate-level simulation for all DFT modes. Develop and debug timing constraints for all DFT modes. Verify test patterns pre-silicon and post-silicon Write scripts in TCL and Perl to achieve productivity enhancements through automation. Required Background: BSEE/MSEE or equivalent degree with 7+ years of experience . In-depth knowledge of VLSI design as well as hardware description languages such as Verilog . Experience with complex block-level and SOC-level DFT execution in advanced finFET technology. Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent. Good problem solving and debug capabilities is a preferred plus. Good knowledge of hardware simulation tools like VCS, Verdi, etc. Proficient in scripting languages (C/C++/TCL/Perl/Python) Should be proficient at working with cross functional and cross site teams. Must possess good communication skills, be a self-driven individual and a good team player. Personal attributes: Can-do attitude. Strong team player. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

Description Job Title: Sr Staff DFT Engineer Job Location: Bangalore, India ( This position requires a full-time, on-site presence in our Bangalore, India office ) Job ID: AI2435 Key Responsibilities: Block-level and sub-system DFT micro-architecture including SCAN, MBIST, IP tests, JTAG Develop and execute test insertion flow for scan, MBIST, JTAG Estimate and achieve targeted test coverage. Run RTL and gate-level simulation for all DFT modes. Develop and debug timing constraints for all DFT modes. Verify test patterns pre-silicon and post-silicon Write scripts in TCL and Perl to achieve productivity enhancements through automation. Required Background: BSEE/MSEE or equivalent degree with 7+ years of experience . In-depth knowledge of VLSI design as well as hardware description languages such as Verilog . Experience with complex block-level and SOC-level DFT execution in advanced finFET technology. Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent. Good problem solving and debug capabilities is a preferred plus. Good knowledge of hardware simulation tools like VCS, Verdi, etc. Proficient in scripting languages (C/C++/TCL/Perl/Python) Should be proficient at working with cross functional and cross site teams. Must possess good communication skills, be a self-driven individual and a good team player. Personal attributes: Can-do attitude. Strong team player. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

Description Job Title: Principal DFT Engineer Job Location: Bangalore, India ( This position requires a full-time, on-site presence in our Bangalore, India office ) Job ID: AI2436 Key Responsibilities: Block-level, Sub-system, and SOC DFT architecture and methodology definition including SCAN, MBIST, IP tests, JTAG. Lead DFT architecture and implementation for different sub-systems and full-chip. Develop test insertion flow for scan, MBIST, JTAG. Estimate and achieve targeted test coverage and ATE test time. Develop timing constraints for all DFT modes. Drive pre and post silicon test patterns validation and bringup. Write scripts in TCL and Perl to achieve productivity enhancements through automation. Required Background: BSEE/MSEE or equivalent degree with 16+ years of experience. 8+ years of experience leading complex DFT execution in advanced finFET technology. Must have experience in mentoring DFT engineers. In-depth knowledge of VLSI design as well as hardware description languages such as Verilog, Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent. Good problem solving and debug capabilities is a preferred plus. Good knowledge of hardware simulation tools like VCS, Verdi, etc. Proficient in scripting languages (C/C++/TCL/Perl/Python). Should be proficient at working with cross functional and cross site teams. Must possess good communication skills, be a self-driven individual and a good team player. Personal attributes: Can-do attitude. Strong team player. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

Job Title: Principal DFT Engineer Job Location: Bangalore, India ( This position requires a full-time, on-site presence in our Bangalore, India office ) Job ID: AI2436 Key Responsibilities: Block-level, Sub-system, and SOC DFT architecture and methodology definition including SCAN, MBIST, IP tests, JTAG. Lead DFT architecture and implementation for different sub-systems and full-chip. Develop test insertion flow for scan, MBIST, JTAG. Estimate and achieve targeted test coverage and ATE test time. Develop timing constraints for all DFT modes. Drive pre and post silicon test patterns validation and bringup. Write scripts in TCL and Perl to achieve productivity enhancements through automation. Required Background: BSEE/MSEE or equivalent degree with 16+ years of experience. 8+ years of experience leading complex DFT execution in advanced finFET technology. Must have experience in mentoring DFT engineers. In-depth knowledge of VLSI design as well as hardware description languages such as Verilog, Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent. Good problem solving and debug capabilities is a preferred plus. Good knowledge of hardware simulation tools like VCS, Verdi, etc. Proficient in scripting languages (C/C++/TCL/Perl/Python). Should be proficient at working with cross functional and cross site teams. Must possess good communication skills, be a self-driven individual and a good team player. Personal attributes: Can-do attitude. Strong team player. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT . Experience: 1-3 Years .

Lead a team of 5-10 resources Understand the design specification , PowerOn Specification Understand boot firmware and reset flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization. ( for SoA) Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Drive Architecture that will define the SOC/MCU architecture and detailed technical specifications from product requirements provided by business and product marketing organizations. Collaborate closely with product and software architects to define and refine SoC-level architecture Play a key role in shaping the microarchitecture of complex IP blocks and SoC subsystems Work closely with functional verification teams on test-plan development and reviews Collaborate with other functional teams including Design, Validation, DFT, physical design and emulation teams to achieve architectural goals and performance targets Provide support to functional validation teams in post silicon debug IP selection and make/buy decisions are a key factor for this role Qualifications Strong communication skills (written and verbal), problem solving, teamwork, attention to detail, commitment to task, and quality focus BTech/MTech in Electrical/Electronic/Computer/Hardware Engineering with experience of 12+ years Can – do attitude, openness to new environment, people and culture Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency Experience with benchmarking IP/SoC performance and tuning IP/SoC architecture Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Experience in using Virtual Prototype tools (ARM Fast Models, Synopsys Virtualizer, Windriver SIMICS etc..) is a plus Additional Information Renesas Electronics Corporation empowers a safer, smarter and more sustainable future where technology helps make our lives easier. The leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at www.renesas.com. Renesas’ mission, To Make Our Lives Easier, is underpinned by our company culture, TAGIE. TAGIE stands for Transparent, Agile, Global, Innovative and Entrepreneurial. Our goal is to embed this unique culture in everything we do to succeed as a company and create trust with our diverse colleagues, customers and stakeholders. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas Electronics Corporation empowers a safer, smarter and more sustainable future where technology helps make our lives easier. The leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at www.renesas.com. Renesas’ mission, To Make Our Lives Easier, is underpinned by our company culture, TAGIE. TAGIE stands for Transparent, Agile, Global, Innovative and Entrepreneurial. Our goal is to embed this unique culture in everything we do to succeed as a company and create trust with our diverse colleagues, customers and stakeholders. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT .Experience: 3-5 Years .

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: We are seeking a DFT (Design for Test) Architect & Implementation Engineer with expertise in designing and implementing DFT networks for SoC (System on Chip) devices with mixed ASIC and custom content. The ideal candidate will drive the DFT strategy, develop test methodologies, and work hands-on in integrating DFT features into the designs. This role requires deep knowledge of scan networks, scan insertion, boundary scan (JTAG), MBIST, ATPG, and fault coverage analysis. Key Responsibilities: DFT Architecture & Strategy: Define and develop DFT methodologies for ASIC designs to ensure high testability and fault coverage. Architect and implement scan, JTAG, and memory BIST (MBIST). Optimize DFT strategy to balance test coverage, performance, and area constraints. Hands-On Implementation: Develop and integrate DFT structures such as scan networks, scan chains, boundary scan, MBIST, LBIST, and built-in self-test (BIST). Generate and verify ATPG (Automatic Test Pattern Generation) patterns for fault coverage analysis. Work with RTL design engineers to ensure DFT compliance in Verilog/VHDL-based designs. Run fault simulation, stuck-at and transition fault testing, and analyze coverage reports. Collaboration & Validation: Work closely with RTL, synthesis, and physical design teams to ensure DFT design integrity. Collaborate with manufacturing and validation teams to implement test strategies for prototype bring-up. Debug and optimize DFT networks to achieve minimal test times. Work with EDA vendors to evaluate and integrate latest DFT tools and methodologies. Requirements/Qualifications: 15+ years of experience in DFT architecture and implementation. Strong expertise in FPGA-based DFT methodologies (Xilinx, Intel/Altera, Lattice, etc.). Proficiency in Verilog/VHDL for FPGA design and test logic implementation. Hands-on experience with DFT tools (Synopsys DFT Compiler, Tessent, Mentor Tessent, Cadence Modus, or similar). Strong knowledge of JTAG (IEEE 1149.1, 1149.6), scan insertion, ATPG, MBIST, LBIST, and fault modeling. Experience in timing analysis and synthesis-aware DFT implementation. Familiarity with FPGA prototyping and board bring-up. Hands-on scripting skills in Python, TCL, Perl, or Shell for DFT automation. Preferred Qualifications: Experience in AI/ML-driven DFT automation. Knowledge of high-speed interfaces and SERDES testing. Experience with post-silicon validation and ATE (Automated Test Equipment). Strong debugging skills using logic analyzers, oscilloscopes, and FPGA tools. Why Join Us? Work on cutting-edge FPGA-based designs for high-performance computing, automotive, or AI applications. Opportunity to architect and implement industry-leading DFT methodologies. Be part of a highly skilled team pushing the boundaries of FPGA design & test innovations. Travel Time: 0% - 25% To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Coordinate with painters while working on indoor and outdoor assignments. Duties are estimating Material requirements, assigning tasks, evaluating work progress, ensuring that safety guidelines are respected. Coordinating with dry abrasive blasting apparatus setup, surface preparation tools, airless spray machines, coating thickness gauge. Coordination with Third Party Inspection agency and Vendors to complete the Special Coating application. Inspection & Verification of Coating Damages & rectification Documentation Compliance & Making reports as per Regulations. Humidity control & DFT controlling for subsequent coating Proper storage of handling paint materials and abrasive materials in given specified controlled conditions. Coordinating the activities of subordinated supervisors ensuring that the production steps are respected. Calculation and estimation the amount of paint material required for specific painting job based on surface area to be painted. Follow up on Sales/Export orders and monitor their delivery. Overseeing Production / Quality Control of finished goods.

Painting Inspector ensures that all painting and coating work on a project meets quality standards and specifications. This involves inspecting surface preparation, coating application, and the final finish to ensure proper adhesion, durability, and aesthetic quality. They also verify that materials, equipment, and activities comply with safety standards and project requirements. Responsible for Quality Control activities in the areas of Incoming, Process, Third Party, Final inspection & Customer inspection activities involved with Painting and Coating. Preparation of QA Dossier, QA documentation, Verification and Handling third party inspections, Pre-dispatch inspection, Final product verification. Certified Painting Inspector with experience in industrial coating/painting inspection for valves and pressure equipment. Skilled in surface preparation, DFT measurement, paint system verification, and compliance with international standards such as NACE, and ISO. Strong background in third-party inspection coordination and quality documentation. Job Responsibilities: Follow and maintain Company standards of Quality in accordance with Company Quality System requirements. Maintain standards of safety and comply with Company s Health, Safety and Environment Management System requirements. Support Quality Supervisor for his day-to-day Quality assurance/control activities. Painting / coating inspection of Valves, actuators, and accessories Responsible for stage wise painting / coating inspection. Undertake QC painting / coating activities in the workplace for daily basis. Monitor weather condition for surface preparation and painting / coating application. Prepare inspection & test plan (ITP) for specific project / company requirements/ surface preparation and painting / coating procedure Execute Painting / coating inspection work as per company / project inspection test plan. Handle third party inspection, pre-dispatch and Final inspection Preparation of QA procedures / work instructions/ documents and records and maintain as per the retention period. Performing Internal Quality Audit / product and process audits, Supplier Evaluation and Re-evaluation audits as per the schedule. Preparation & Control of Quality Dossier, Verification of Documents Ensure product readiness prior to inspection and solve quality issues, if any Attend Inspections, Record observations and ensure compliance with specifications. To check and monitor all painting / coating related works and ensure all final products meet in accordance with company procedure, client requirement and international codes. Responsible for incoming coating / painting material inspection and has to ensure whether these materials suits to meets the requirements of project specifications. Prepare all necessary QA / QC painting / coating documents and handed over to clients review. Review of calibration status of TMME items. Co-ordinate with the paint manufacturer technical representative on daily basis. Follow-up with departments for timely closure of Customer complaints. Support NCR/CAPA process for issues arising out of inspection Provide Training and awareness. Adhering to safety rules & regulations Job Requirement : B.E or Diploma in Mechanical / Production Engineering with 5-8 years experience in Quality Control/ Painting Inspection activities NACE Level 2 Certified Coating Inspector, Certified by NACE International USA. Surface preparation inspection (Sa 2.5, SSPC-SP standards) DFT (Dry Film Thickness) & WFT checks Paint system verification (Primer, Intermediate, Topcoat) Holiday testing & adhesion testing Coordination with TPI (BV, TUV, LR) Report preparation, punch point clearance Valve industry coating specs (internal/external) Knowledge on requirements of ISO 9001, ISO 14001, OHSAS 18001, API SPEC Q1 requirements. Knowledge in Manufacturing process requirements, Customer requirements and Codes & Standards. Good communication skills NDE Level II PT, MT, UT & RT preferable Knowledge of Product and Material standards ASME, ISO, ASTM, EN etc Knowledge of Quality Management System, Product standards & approvals. Customer interaction for product approvals and Interaction with notified bodies for Certification. Knowledge on various Problem-solving techniques, Analyze problems, detect root causes and resolve issues. Knowledge on SAP, MS office, Knowledge in Chemicals, Sealants & Lubricants will be added advantage

Join SanDisk India as a Technical ASIC Project Leader and take charge of developing cutting-edge ASICs that power the next generation of SD cards for imaging, gaming, mobile, and data storage. This is a high-impact leadership role where your technical expertise and strategic vision will drive projects from concept to mass production. Key Responsibilities: Lead Full-Cycle SoC Development: Own the end-to-end development of high-performance ASIC controllers, from architecture definition to production ramp-up. Translate Product Vision into Technical Execution: Collaborate with product, firmware, and system teams to define ASIC requirements aligned with SanDisk s storage solutions. Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering teams to deliver industry-leading SoC solutions. Ensure Technical Excellence: Conduct in-depth technical reviews, identify risks early, and implement mitigation strategies to ensure project success. Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement. Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment and enthusiasm across all levels. Qualifications Master s degree in electrical engineering, Computer Engineering, or a related field. Proven experience leading complex ASIC or SoC development projects. Strong technical background in digital design, verification, and silicon validation with understanding of the SD, UHS and SD-Express standards. Excellent cross-functional leadership and communication skills. Ability to manage technical risks and drive execution in a fast-paced environment. Passion for innovation and delivering high-quality, scalable solutions. Preferred Qualifications: Proficiency with EDA tools and methodologies for ASIC development. Familiarity with industry standards and best practices in semiconductor design. Expertise in low-power design techniques and high-speed interfaces.

DFT Manager About MIPS MIPS is a leader in high-performance RISC-V CPU IP, enabling innovation across automotive, AI, data center, and embedded markets. Our engineering teams are building the next generation of compute solutions, and we are looking for passionate talent to join us in shaping the future of semiconductors. Position Overview The DFT Manager leads and develops the engineering team responsible for designing and deploying advanced Design-for-Test solutions in semiconductor chip development. This role focuses on building robust DFT architectures including ATPG, MBIST, LBIST, analog test solutions and implements repeatable methodologies and flows that ensure rapid, optimized test pattern generation and efficient project execution. Key Responsibilities Lead, mentor, and manage the DFT engineering team, overseeing daily operations and technical development. Define and deploy DFT architecture for chips with features such as Automatic Test Pattern Generation (ATPG), Memory Built-In Self-Test (MBIST), Logic Built-In Self-Test (LBIST), and analog test solutions. Develop and optimize test pattern generation methodologies, prioritizing test time reduction and manufacturing efficiency. Establish and maintain standardized, repeatable DFT methodologies and flows to consistently achieve fast turnaround and reliable results across projects. Collaborate cross-functionally to integrate DFT features and requirements throughout the silicon development lifecycle. Automate test program, script development for maximum coverage and reduced test cost. Continuously analyze test performance data and apply lessons learned for iterative improvement. Promote innovation and continuous improvement by evaluating new trends, tools, and best practices. Document DFT specifications, standards, and re-use strategies for knowledge sharing and future use. Required Qualifications Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or a related field. 8+ years of hands-on DFT experience plus proven leadership of DFT teams on SoCs. Expertise in test pattern generation, ATPG, MBIST, LBIST, analog test development, and scan insertion. Significant experience optimizing test time through efficient DFT strategies and tool use. Proven ability to design and implement repeatable DFT flows and reusable test IP. Proficiency with EDA tools (Synopsys, Cadence, Mentor Graphics), and scripting (Python, Perl, TCL). Strong analytical, organizational, leadership, and communication skills. Desired Attributes Strategic thinker who translates customer, product requirements into practical, innovative test solutions. Inspirational leader focused on team growth, technical excellence, and methodology re-use. Proactive, detail-oriented professional committed to efficiency, quality, and process improvement. Why Join MIPS Be part of a team driving innovation in RISC-V CPU IP and SoC development. Work on cutting-edge semiconductor designs with global impact. Collaborative, growth-focused environment with opportunities for innovation and leadership.

About Marvell . Your Team, Your Impact This position is with Power signoff team part of The Central Engineering PD group at Marvell, Bangalore. This team is part of global Implementation team that plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM s. We are looking for a strong technical individual contributor having experience in low power design using industry standard tools. What You Can Expect Work on digital design for ASICs, Physical Implementation, Power Supply integrity checks Low Power design & Signoff Work on complete SoC design cycle of ASICs, starting from Architecture definition, feasibility planning/benchmarking for Power/Performance/Area/Yield to end-to-end design/Implementation/Signoff Work on challenging design architecture across Networking, Processor, Computing, automotive, Connectivity and Security, in the technology nodes across 3nm/5nm/7nm and more. Collaborate with cross-functional teams including RTL design, verification, and DFT to optimize power. Perform floorplanning, placement, clock tree synthesis, routing, and physical verification. What Were Looking For Bachelor s or Masters degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. Exposure on ASIC Physical implementation, Layout and Semiconductor device/process through previous work/intern experience or course work. Experience in power analysis, estimation, and optimization flow. Understanding of Physical Design and EM/IR flow Expertise in Tcl and PERL. Experience in Physical design is preferable. Scripting/programming using Tcl/Tk/Perl/Python/Shell Detail oriented, self-motivated team worker, good verbal, and written communication skills. Strong Digital Design concepts and debugging skills. #LI-MN1 Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1

Position Overview: We are looking for a highly skilled and experienced individual for SoC PD lead position for driving SoC implementation efforts from RTL to GDSII. This role is pivotal within our talented team of engineers, ensuring that we meet our GDS release timelines, PPA requirements, and all sign-off criteria for our complex semiconductor designs. This role demands a profound technical understanding of the entire implementation cycle, from start to finish, as well as exceptional leadership skills. The successful candidate will work with various functional teams and must possess a strategic vision to drive continuous improvement in our methodologies and processes. Key Responsibilities: To be responsible for leading RTL-to-GDSII SoC implementation effort To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc. To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity. To ensure process compliance during project execution and enable / participate in technical discussions/reviews. To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations. Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team s workflow Foster a culture of innovation, collaboration, and continuous improvement - Qualifications - Bachelor s or master s degree in electrical engineering, Computer Engineering, or a related field - A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs Proven ability in technically leading a small/medium-sized team for executing projects preferred. Hands-on experience on the entire PD Flow from RTL to GDSII Should have a good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains. Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc) Exposure to static timing analysis fixes including automated ECO generation. Strong in areas on CTS, Power, Bump planning, Floorplan Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies. Library preparation in any environment (Synopsys, Cadence, etc) Working knowledge on Physical verification tasks at lower nodes (database merging / DRC / LVS / ERC / PERC / Antenna / ESD / LUP analysis/fixing) at block level/chip level The job would require complete ownership from RTL to GDS for complete SoC Exposure to IP Hardening for blocks like SERDES, USB PHY, PCIe, DDR will be an added advantage. Working knowledge of scripting languages like Perl and TCL will be considered a plus Candidate needs to be self-driven and confident in reporting the status and sharing technical results with customers. Must have the ability to present to senior management, work in a geographically dispersed team, and be aware of cross-cultural nuances. Should be able to define project milestones, identify risks, and call out mitigation plans.

Company Description VIT Bhopal University, known for its global outlook, empowers its students to achieve excellence through innovative learning methodologies. The university's comprehensive teaching methods redefine education, focusing on building knowledge-based societies. VIT Bhopal collaborates with reputed national and international organizations and has strategic partnerships with universities worldwide to prepare globally competent professionals. Role Description This is a temporary, on-site role for a Junior Research Fellow located in Bhopal. The Junior Research Fellow will be responsible for conducting research, assisting in academic projects, analyzing data, compiling research findings, and preparing reports. Daily tasks may also include collaboration with faculty members and contributing to publications and presentations. Qualifications Master's degree in a relevant field (Chemistry, biology, biochemistry) Experience with QM, DFT, Molecular Dynamics, Docking or bioinformatics tools Proficient in research methodologies and data analysis Experience in collaborating with academic professionals and contributing to publications Excellent written and verbal communication skills