1074 Dft Jobs - Page 2

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll do: EM and IR analysis for a given Power Delivery Network and Standard Cell design. Conduct detailed analysis of the PDN at Chip Top and block level to identify and mitigate potential IR (Voltage) drop issues for Static IR and Dynamic IR. Usage of industry-standard tools and methodologies to perform and analyse power and EM. Work closely with different stakeholders and make necessary convergence for design and power convergence. Provide recommendations for layout and design changes to enhance power distribution and minimize IR drop. Evaluate the risk of electromigration in the Signal & PDN (power distribution network) and provide necessary recommendations. Tool Development and Automation: Develop and implement scripts to streamline the IR drop analysis process Responsibilities include looking the IR reports and EM reports and make necessary recommendations to the PnR teams to converge and meet the goals of the design. Role will involve collaboration with Verification teams and get the right vectors for different types of analysis including functional, DFT and other scenarios for which power numbers are needed What Youll Need: 4+ years of experience with a Bachelors/ masters degree in the field of Electrical, Electronics, or computer engineering We are looking for engineer who is well-versed with power analysis (Static & Dynamic) Tools - RedhawkSC, Voltus Is must Good knowledge of PDN (power distribution networks). Good understanding of ASIC design and PnR flow is a must Good understanding of LEF and DEF based data exchanges is must Knowledge, experience in working with lower nodes of 7nm and below CPM model generation experience is a Plus We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

We are seeking a highly skilled DFT Engineer to be part of our growing VLSI/ASIC design team. Contact.-7982405927

Job Description We are seeking a Senior Staff Verification Engineer to lead and contribute to the functional verification of complex SoC and IP designs for next-generation AI, HPC, and data center products. The ideal candidate has extensive experience in UVM/SystemVerilog , SoC and IP-level verification, and is passionate about ensuring first-pass silicon success . This role involves defining verification strategies, developing scalable environments, and collaborating cross-functionally with architecture, design, and software teams. Experience with Virtual Modeling, SystemC, and TLM is a plus , enabling advanced verification and early system-level validation. Qualifications Required Qualifications Education & Experience B.S./M.S. in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience in IP/SoC verification with a proven track record of successful silicon delivery. Technical Expertise Deep knowledge of UVM/SystemVerilog for testbench development and verification IP integration. Strong understanding of SoC architecture and protocols such as DDR5, HBM3, PCIe Gen6, CXL 3.0 , and other high-speed interfaces. Expertise in coverage-driven verification , constrained-random testing, and assertion-based verification. Proficient in debugging RTL, testbenches, and simulation failures using industry-standard tools. Tools & Languages Hands-on experience with simulation tools (VCS, Xcelium, Questa, etc.), waveform viewers, coverage tools, and automation scripting (Python, Perl, TCL). Preferred/Additional Skills Virtual Modeling and System-Level Verification Familiarity with SystemC and Transaction-Level Modeling (TLM) for virtual prototyping and early system validation. Experience developing or using virtual platforms for hardware/software co-verification is a strong plus. Emulation & Prototyping Exposure to emulation platforms (Palladium, ZeBu) and FPGA-based prototyping for system-level validation and performance analysis. Software Co-verification Experience working alongside firmware/software teams for pre-silicon software validation and early driver/OS bring-up. Low-Power and DFT Verification Knowledge of power-aware verification (UPF/CPF) and DFT validation methodologies is desirable. Additional Information Key Responsibilities Verification Planning & Execution Lead the definition, development, and execution of comprehensive verification plans at IP and SoC levels. Develop UVM/SystemVerilog-based testbenches , including stimulus generation, checkers, and monitors for advanced SoC designs. Drive coverage-driven verification processes, ensuring functional and code coverage goals are met. Cross-Functional Collaboration Collaborate with architecture, RTL design, firmware, software, and emulation teams to define verification requirements and ensure comprehensive test coverage. Participate in design and architecture reviews , providing critical feedback on functionality, testability, and performance considerations. Debug & Issue Resolution Lead debug efforts on complex SoC and IP issues through simulation, emulation, and FPGA prototypes. Perform root-cause analysis and drive issues to closure in partnership with cross-disciplinary teams. Methodology & Infrastructure Development Enhance and maintain verification methodologies , including reusable verification IP, automation scripts, and regression infrastructure. Evaluate and adopt new tools and verification technologies to improve quality and efficiency. Leadership & Mentorship Provide technical guidance and mentorship to junior verification engineers. Lead verification reviews and strategy discussions , ensuring high technical standards and best practices. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Job title Sr Staff Verification Engineer – SoC/IP Design Verification Department Manufacturing Location Hyderabad Remote No Requisition ID 20020172_2025-07-03

Job Description Job Summary Drive Architecture that will define the SOC/MCU architecture and detailed technical specifications from product requirements provided by business and product marketing organizations. Collaborate closely with product and software architects to define and refine SoC-level architecture Play a key role in shaping the microarchitecture of complex IP blocks and SoC subsystems Work closely with functional verification teams on test-plan development and reviews Collaborate with other functional teams including Design, Validation, DFT, physical design and emulation teams to achieve architectural goals and performance targets Provide support to functional validation teams in post silicon debug IP selection and make/buy decisions are a key factor for this role Qualifications Qualifications Strong communication skills (written and verbal), problem solving, teamwork, attention to detail, commitment to task, and quality focus BTech/MTech in Electrical/Electronic/Computer/Hardware Engineering with experience of 12+ years Can – do attitude, openness to new environment, people and culture Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency Experience with benchmarking IP/SoC performance and tuning IP/SoC architecture Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Experience in using Virtual Prototype tools (ARM Fast Models, Synopsys Virtualizer, Windriver SIMICS etc..) is a plus Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Job title Principal SOC Architect Department Manufacturing Location Hyderabad Remote No Requisition ID 20020162_2025-07-03

Job Description Job Description: Staff Engineer We are looking for a technical leader to drive the DFT aspects of high-performance compute MCU development. The candidate must be experienced, hands-on and have robust understanding of testability features including SSN, MBIST, LBIST, Scan Insertion, ATPG, GLS and post silicon debug on automotive grade SOCs. Responsibilities Handling hierarchical scan insertion ATPG flow. Integration and Verification of MBIST at RTL level. RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST. Implementation and Verification of IEEE1149.1 JTAG, IJTAG standards. Post silicon debug activities for DFT patterns. Collaboration with RTL design, Physical design and verification teams will be a daily aspect of the role. Qualifications Degree/PG in Electrical/Electronic Engineering, Computer Engineering or Computer Science. At least 8 years of experience in related domains and have working knowledge of industry standard digital EDA toolkits. Must be conversant on EDA tools such Tessent, Genus, FC, VCS and Conformal/Formality etc. Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can–do attitude, openness to new environment, people and culture. Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus. Ability to work independently and as part of a team. Mentor and guide junior engineers in DFT. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Job title Staff Engineer- DFT Department Engineering Location Hyderabad Remote No Requisition ID 20021208_2025-06-30

Job Description Work together with system architects and micro architects to define high level specifications that are implementable. Contribute to RTL development including running tool flows like lint, CDC, Conformal low power and DFT checks Work closely with functional verification teams on test-plan development and debug. Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. UPF writing, power aware equivalence checks and low power checks. Collaborate with other functional teams including DFT, physical design and emulation teams to achieve project milestones. Provide support to functional validation teams in post silicon debug. Qualifications MTech/BTech in EE/CS with hardware engineering experience of 1 to 15 years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency. Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Job title Senior/Staff/Senior Staff/Principal - RTL Design Engineer Department Engineering Location Noida Remote No Requisition ID 20017793_2024-11-20

Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs , supporting complex architectures with multi-core, multi-power, and multi-reset domains . Demonstrate strong proficiency with front-end flows , including Lint, CDC, low-power (UPF) checks, synthesis, DFT , and Static Timing Analysis (STA) . Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI , and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 . Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation , working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Job title Principal Engineer,RTL Department Engineering Location Noida Remote No Requisition ID 20019236_2025-03-01

Arcadis is the world's leading company delivering sustainable design, engineering, and consultancy solutions for natural and built assets. We are more than 36,000 people, in over 70 countries, dedicated to improving quality of life. Everyone has an important role to play. With the power of many curious minds, together we can solve the world’s most complex challenges and deliver more impact together. Role description: We are now recruiting for an Assistant/Engineer with experience in transportation planning and modelling for our Mobility Advisory group in the GEC Bangalore office to support project delivery focusing on supporting project managers to deliver their project objectives and outcomes. Role accountabilities: Experience in transport modelling (e.g. highways, public transport, multimodal modelling, junction modelling). Knowledge and awareness in transport planning and strategy development (e.g., development planning, Transport Assessment, active travel) Experience of specification, delivery and application of strategic transport models. Proven ability to build, calibrate and validate traffic models with minimum supervision and experience in implementing demand models. Proven experience in PTV VISUM/VISSIM/CUBE/SATURN modelling suite. Experience with spreadsheet analysis and spreadsheet-based models. Knowledgeable user of data analytics and mapping tools (GIS) and able to interpret quantitative transport models. Ability to support the delivery of transport technical documents including Excel, GIS and Word skills, client letters/emails. Ability to work within a team / Working on your own initiative. Aptitude to learn and diversify skill base. Good communication skills. Good organisational skills. Mathematics and Statistic skills are all important. Strong problem solving and attention to detail. Ability to come up with practical solutions. Enthusiastic, Willing to learn, Punctual, Reliable, Committed. Qualifications & Experience: Degree qualified or equivalent essential (e.g. transport planning, civil engineering, geography, economics, mathematics or data science). Additional qualifications in a relevant discipline would be desirable. Working towards a professional qualification with a relevant professional institution (CIHT, ICE, RTPI) desirable. Nice to Have: Knowledge and understanding of Department for Transport’s Transport Appraisal Guidance (TAG). Experience of working with strategic transport clients such as National Highways, HS2, DfT, Welsh Government, Regional Transport Bodies for role 1 and for role 2 with developers, key clients such as Hs2, airports, local authorities etc. Experience in more than one Strategic modelling platform i.e, SATURN, EMME, CUBE, VISUM. Experience in Operational Modelling Platform i.e., VISSIM/SYNCHRO/LINSIG/AIMSUN Have an interest in developing digital skills such as data analysis or Python coding. Why Arcadis? We can only achieve our goals when everyone is empowered to be their best. We believe everyone's contribution matters. It’s why we are pioneering a skills-based approach, where you can harness your unique experience and expertise to carve your career path and maximize the impact we can make together. You’ll do meaningful work, and no matter what role, you’ll be helping to deliver sustainable solutions for a more prosperous planet. Make your mark, on your career, your colleagues, your clients, your life and the world around you. Together, we can create a lasting legacy. Join Arcadis. Create a Legacy. Our Commitment to Equality, Diversity, Inclusion & Belonging We want you to be able to bring your best self to work every day which is why equality and inclusion is at the forefront of all our activities. Our ambition is to be an employer of choice and provide a great place to work for all our people. We are an equal opportunity employer; women, minorities, and people with disabilities are strongly encouraged to apply. We are dedicated to a policy of non-discrimination in employment on any basis including race, caste, creed, colour, religion, sex, age, disability, marital status, sexual orientation, and gender identity. #JoinArcadis #CreateALegacy #Hybrid

As a Qualcomm Hardware Engineer, you will play a crucial role in the planning, design, optimization, verification, and testing of electronic systems. Your responsibilities will include working on various types of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to help in the development of cutting-edge products. You will be involved in the front-end implementation of MSIP designs, RTL development, validation for linting, clock-domain crossing, low power and DFT rules, and collaborating with the functional verification team on test-plan development and debug. Your role will also entail developing timing constraints, providing support for physical design team, UPF writing, power-aware equivalence checks, low power checks, DFT insertion, ATPG analysis, SoC integration support, and chip level pre/post-silicon debug. To be successful in this role, you should hold an MTech/BTech in EE/CS with at least 5 years of hardware engineering experience. You should have expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks), synthesis, DFT, functional verification, and static timing analysis. Experience with post-silicon bring-up and debug will be an added advantage. Additionally, the ability to collaborate effectively with global teams and strong communication skills are essential for this role.,

TechiesDesigns is seeking enthusiastic and motivated fresh graduates to join our team as Trainee PCB Design Engineers . This is an exciting opportunity for candidates looking to build a strong foundation in the field of PCB design and electronics hardware development. Key Responsibilities: Assist in the design and development of PCB layouts using industry-standard design tools (such as Altium, Eagle, KiCAD, etc.). Work closely with senior engineers to understand schematic design, layout guidelines, and DFM/DFT principles. Support in creating documentation, Gerber files, and BOM generation. Participate in prototype testing, troubleshooting, and validation. Learn and adhere to industry best practices and company design standards. Continuously upgrade knowledge and skills related to electronics and PCB design. Requirements: Fresh graduates with B.E / Diploma in ECE, EEE, or related streams. Basic understanding of electronics components, schematics, and circuit design. Familiarity with any PCB design tool is a plus. Strong analytical and problem-solving skills. Eagerness to learn and work in a collaborative environment. Good communication and documentation skills. What We Offer: Hands-on training and mentorship from experienced engineers. Exposure to real-world design projects. Opportunity to grow into a full-time PCB Design Engineer role. Supportive and innovative work culture. How to Apply: Interested candidates can send their updated resume to [Insert Email] with the subject line Application for Trainee PCB Design Engineer . Apply for this position Allowed Type(s): .pdf, .doc, .docx By using this form you agree with the storage and handling of your data by this website. *

Job Overview: Experience: 3-15 years Responsibilities: Verification engineer with a knowledge of IP verification or SoC integration verification Experience in SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx integration verification in SoC RTL. Experience in architecting and implementing SV/UVM testbenches, create and maintain reusable verification components Experience in formal verification strategy for complex IP blocks defining properties, driving proofs and coverage closure Your key responsibilities will include writing test plans, defining test methodologies, SystemVerilog/Verilog testbench development, developing UVM or C based software tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills and Experience : Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies UVM/OVM, Formal(jasper), power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of IP or SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures. Porting peripheral driver software Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Experience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures. Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.) Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm

SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

SILICON DESIGN ENGINEER 2 THE ROLE: The focus of this role is to execute the front end implementation of sub-blocks or IP. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. KEY RESPONSIBILITIES: Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure Collaborate with designer and PNR teams to achieve closure. Execute as per schedule. Complete quality delivery for synthesis and timing closure. Debug and resolve technical issues PREFERRED EXPERIENCE: Experienced in synthesis and timing closure Good to have experience in LEC, CLP Have handled blocks with complex designs, high frequency clocks and complex clocking complete understanding of timing constraints, low power aspects and concepts of DFT Have debug experience to solve issues. scripting and automation ACADEMIC CREDENTIALS: Bachelors with 2 years of experience or Masters degree with 1 years of experience in Electrical Engineering #LI-RP1

Where ASIC Physical Design, Sr Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12343 Remote Eligible No Date Posted 23/07/2025 Alternate Job Titles: ASIC Physical Design Engineer Place & Route Engineer Sr. Physical Design Specialist We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented engineer with a strong background in ASIC physical design and a keen interest in advancing semiconductor technology. You thrive in collaborative, fast-paced environments and are motivated by technical challenges that push the boundaries of what s possible in chip design. With your foundational education in electronics or electrical engineering, you have honed a solid understanding of CMOS and submicron ASIC flows, working on advanced technology nodes such as 28nm, 16nm, 14nm, 10nm, and 7nm. You possess hands-on experience with industry-leading EDA tools, including Synopsys ICC-II/FC, Design Compiler, PrimeTime, and Cadence Innovus, and are adept at developing, optimizing, and verifying robust ASIC design flows. Your curiosity drives you to stay on top of the latest methodologies, and your analytical mindset ensures you can solve complex problems with innovative solutions. You are comfortable taking ownership of tasks, whether it s developing flows, performing timing analysis, or releasing production views for IP. You communicate clearly, collaborate effectively, and are committed to delivering high-quality results with attention to every detail. You believe in continuous improvement, proactively seeking ways to optimize power, performance, and area (PPA) while maintaining the highest standards of quality. Most importantly, you are excited about making an impact in a global team that values diversity, learning, and technological excellence. What You ll Be Doing: Developing and optimizing ASIC design flows to build and verify standard cell libraries, ensuring the best possible Power, Performance, and Area (PPA) with uncompromised quality. Creating and maintaining Place & Route (P&R) methodologies using industry-standard tools such as Synopsys ICC-II/FC and Cadence Innovus. Releasing P&R production views for IP, ensuring readiness for downstream design and integration teams Conducting thorough physical verification (DRC/LVS), timing analysis (STA), and addressing design closure challenges across advanced technology nodes. Collaborating with cross-functional teams to integrate design flows, improve automation, and resolve technical issues throughout the ASIC lifecycle. Implementing and validating low-power design concepts using UPF/CPF formats, and ensuring robust power analysis and planning. Generating and managing technology files, library views (Milkyway, NDM), and deliverables such as LEF, DEF, GDS for standard cell libraries. The Impact You Will Have: Enable the creation of high-performance, energy-efficient silicon chips that power next-generation applications and devices. Drive improvements in PPA and overall design quality, directly influencing customer satisfaction and product competitiveness. Ensure timely and robust release of IP production views, accelerating time-to-market for Synopsys customers. Advance the state-of-the-art in physical design methodologies, contributing to Synopsys leadership in the semiconductor industry. Collaborate cross-functionally to share best practices and foster a culture of continuous improvement and innovation. Support the successful deployment of Synopsys tools and flows in real-world customer projects, reinforcing our reputation for technical excellence. What You ll Need: Bachelor s or Master s degree in Electronics or Electrical Engineering (or equivalent) from a reputed university. 1-2 years experience in ASIC design, with hands-on exposure to advanced process nodes (28nm, 16nm, 14nm, 10nm, 7nm) and multiple foundries. Strong understanding of CMOS, ASIC flow in submicron nodes, and expertise in Place & Route, physical verification (DRC/LVS), and timing analysis (STA). Proficiency with Synopsys (ICC-II/FC, Design Compiler, PrimeTime) and Cadence (Innovus, RC/Genus) EDA tools. Experience with all stages of the ASIC design flow, including Synthesis, DFT, timing analysis, floor planning, power planning, CTS, ECO flow, STA, and power analysis. Good grasp of low power design concepts, UPF/CPF formats, and standard cell library view generation processes (Milkyway, NDM). Who You Are: Analytical thinker with strong problem-solving skills and meticulous attention to detail. Effective communicator, able to articulate complex technical concepts to diverse audiences. Collaborative team player who thrives in a multicultural and multidisciplinary environment. Self-motivated, adaptable, and eager to learn new technologies and methodologies. Proactive in identifying areas for improvement and driving innovative solutions. The Team You ll Be A Part Of: You ll join a dynamic, inclusive team of physical design and ASIC implementation experts dedicated to developing world-class design flows and methodologies. Our team collaborates closely with IP development, CAD, and validation groups, sharing knowledge and driving best practices across the organization. We value open communication, continuous learning, and a passion for technical excellence, and we are committed to supporting each other s growth and success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Candidate must have completed 03-06 months of training in VLSI. Candidate must have knowledge about: VLSI - Design Verification VLSI - Physical Design VLSI - Hardware VLSI - Analog Circuit Analog (Memory Design/Layout) VLSI - DFT RTL

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

Talent Acquisition Specialist – Semiconductor Hiring | Hyderabad | 0 – 6 Months Experience Education: MBA (HR or related) with Bachelor's in Electronics or related field About the Role: We are seeking a smart, energetic, and highly motivated Talent Acquisition Specialist to join our Semiconductor hiring team. This is an exciting opportunity for fresh graduates or early-career professionals who are passionate about recruitment and want to be part of building the next generation of semiconductor talent. The ideal candidate should have a strong interest in technology hiring, excellent communication skills, and a willingness to learn and grow in a fast-paced environment. Key Responsibilities: Support end-to-end recruitment for niche semiconductor roles (ASIC, SoC, RTL, DFT, AMS, etc.) Screen resumes and evaluate candidates based on job requirements and technical fit Conduct initial HR discussions and schedule interviews with technical panels Work closely with internal stakeholders to understand job descriptions and role expectations Build candidate pipelines through sourcing tools (LinkedIn, Naukri, etc.) Maintain and update applicant tracking systems and recruitment dashboards Assist in campus engagement and outreach programs where required Coordinate with onboarding and documentation teams for smooth candidate joining Requirements: MBA in Human Resources (preferred) with a Bachelor's degree in Electronics, ECE, or a related stream 0 to 6 months of experience in recruitment or internship experience in TA (preferred but not mandatory) Strong communication and interpersonal skills Interest or basic understanding of semiconductor industry roles is a plus Self-driven, organized, and eager to learn Proficiency in MS Office tools (Excel, Word, PPT) Why Join Us? Opportunity to work in a growing Semiconductor talent team Exposure to niche technical hiring Learn from experienced mentors and stakeholders Fast-track career development and learning programs If you're passionate about people and technology, and ready to kick-start your career in Talent Acquisition, we’d love to hear from you!

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Work with the team on Verilog RTL and scripted flow implementation of the specified Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design. Work with the team on Verilog testbench implementation of the specified verification tests for DFT features and use case. Work with the team on automation scripts intended for robustness of implementation quality and improvement of efficiency. Minimum Qualifications: Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 2 to 4 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Preferred Qualifications: VLSI circuit physical behaviors in silicon (electrical migration, temperature/voltage variation effects). Basic timing concepts, including setup and hold, metastability. Some EDA tools usage experience Strong verbal communication skills and ability to thrive in a dynamic environment Scripting/coding language: Tcl, Python, Perl, or c/c++. Why Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re "old" (36 years strong) and only about hardware, but we’re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can’t put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it). Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us!

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products. As a part of this team, you will contribute to designing networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations globally. Cisco Silicon One is a groundbreaking silicon architecture that allows customers to utilize top-of-the-line silicon in various network environments. Join us in shaping innovative solutions by working on the design, development, and testing of complex ASICs. In this role, you will collaborate with the team on Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics requirements. You will also be involved in Verilog testbench implementation for verification tests and automation scripts to enhance implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience. - Proficiency in DFT, test, and silicon engineering trends. - Familiarity with JTAG protocols, Scan and BIST architectures, ATPG, and EDA tools. - Verification skills in System Verilog Logic Equivalency checking and Test-timing validation. **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon. - Knowledge of timing concepts and EDA tools usage. - Strong verbal communication skills and adaptability in a dynamic environment. - Proficiency in scripting/coding languages such as Tcl, Python, Perl, or C/C++. Cisco is committed to embracing diversity, fostering innovation, and driving digital transformation. With a focus on inclusive teamwork and a culture of creativity, we encourage individuality and support continuous learning and growth. At Cisco, we value accountability, boldness, and diversity of thought. Join us in our journey to create a future where technology drives positive change and equality for all.,

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for the core Switching, Routing, and Wireless products. We design networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations worldwide. Cisco Silicon One is a unique silicon architecture that allows customers to utilize top-of-the-line silicon in TOR switches, web-scale data centers, and across various networks with a unified routing and switching portfolio. Join our team and contribute to shaping Cisco's innovative solutions by participating in the design, development, and testing of cutting-edge ASICs. As a member of our team, you will be involved in the Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug, and diagnostics requirements. Additionally, you will collaborate on Verilog testbench implementation for verification tests related to DFT features and use cases. Your role will also include contributing to automation scripts aimed at enhancing implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience - Knowledge of the latest trends in DFT, test, and silicon engineering - Proficiency in JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan - Familiarity with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime - Verification skills encompass System Verilog Logic Equivalency checking and validating the Test-timing of designs **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon, including electrical migration and temperature/voltage effects - Knowledge of basic timing concepts like setup and hold, metastability - Experience with EDA tools - Strong verbal communication skills and ability to excel in a dynamic environment - Proficiency in scripting/coding languages like Tcl, Python, Perl, or C/C++ Cisco is a diverse and inclusive environment where individuality is celebrated, and collaborative teamwork drives meaningful change for an inclusive future. Embracing digital transformation, we assist our customers in implementing digital changes in their businesses, showcasing our expertise as both a hardware and software company. Our innovative network solutions adapt, predict, learn, and protect, setting us apart as a company that defies traditional categorization. At Cisco, we value accountability, boldness, and diversity of thought. We foster a culture of innovation, creativity, and learning from failures, all while promoting equality for all individuals. Our inclusive environment encourages employees to be themselves, whether it's through unique personal styles or a passion for technology and positive change. Join us at Cisco, where your individuality and dedication to excellence are celebrated.,

Skills: Strong technical foundation and proven hands-on experience in PCB design using industry-standard software. Deep understanding of various sensor technologies, Sensor building , signal conditioning, and their practical application in embedded systems or IoT devices. Proficiency in circuit simulation tools. Ability to guide students in conceptualizing, designing, fabricating (conceptually), and testing complete electronic hardware projects incorporating sensors and custom PCBs. Must be able to confidently explain and simplify complex electronics and hardware concepts for diverse age groups and academic levels. Excellent communication skills in English and Hindi (both verbal and written). Strong planning and time management abilities. Strong public speaking and presentation skills. Comfortable handling large groups and tailoring delivery methods to suit different institutions. Excellent stakeholder management handling clients, academic institutions, and internal teams Willingness to take up training responsibilities as required. Role & responsibilities Lead Training Sessions: Deliver engaging and practical trainings covering PCB Design, Sensor Designing & Integration , Hardware Prototyping & Testing across colleges, schools, and premier institutions . Mentorship & Team Training: Train, guide, and mentor junior trainers from PHN Technology, ensuring content and delivery consistency in PCB design and sensor systems. Content Development: Develop and continuously update training materials, live projects, case studies, and hands-on labs that demonstrate practical applications of PCB design and sensor technologies. Travel Readiness: Willingness and ability to travel extensively across India for conducting workshops and sessions as per schedule. Preferred candidate profile We are looking for a highly skilled professional with deep expertise in PCB design, diverse sensor technologies and sensor designing . The ideal candidate should have a minimum of 5+ years of relevant experience in teaching, corporate training, or industry roles. A strong command over communication (both verbal and written) in English and Hindi is essential, along with the ability to clearly explain and simplify complex concepts to learners across diverse age groups and academic levels. Candidates should possess excellent public speaking and presentation skills , and be comfortable delivering sessions to large groups while tailoring the content as per institutional needs.

Candidate will be responsible for building/maintaining highlyconfigurable and reusable IO Subsystems (Note: An IO Subsystem is alogic IP that processes the IO Pads/IO Ring information and requiredlogic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner) Job Description In your new role you will: Candidate will be responsible for building/maintaining highly configurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes the IO Pads/IO Ring information and required logic to allow multiple on-chip peripherals to share the same IOs in a configurable manner) Candidate will be responsible for RTL design for integration of IO pads into SoC, building the required multiplexing logic and necessary power control signals integration. Strong fundamentals in DFT/Fault-grading and/or hands on experience. Sound & Practical Written and Verbal Communication Skills. Your Profile You are best equipped for this task if you have: Must have worked in ASIC Design flow, with ASIC experience of upto 5years. Must be strong in scripting using Perl/Python Must be familiar with RTL design for for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Experience: 3 6 Years Location: Pune Joining: Immediate Work Location / Mode of Work Hinjewadi / Work from office Key Responsibilities: Design and layout of multi layer PCBs for EV powertrain modules (inverters, BMS, DC DC converters, OBC, motor controllers) Collaborate with hardware/thermal engineers and cross-functional teams to optimize layout Create schematics, footprints, BOMs; ensure DFM/DFT and high-speed design compatibility Coordinate with PCB manufacturers for prototyping and compliance Ensure designs follow IPC standards and EMI/EMC considerations Required Skills: Proficiency in PCB design tools (Altium, OrCAD, Allegro, etc.) Experience in power electronics, signal integrity, thermal constraints Familiarity with EMI/EMC compliance and automotive design practices Xpetize is a technology solutions company, supporting customers in IoT, application and engineering services, data services, cybersecurity, cloud and social services. We are headquartered in Trivandrum with offices in Bengaluru, Pune, USA and Japan. We work tirelessly to help our customers across the globe since 2011 and relentlessly trying to grow our expertise across geographies. Our flagship Industry 4.0 product XPETICS, is a fully managed IIoT platform that lets customers securely connect and process IoT data at scale. We have a flexible and open work culture, lots of fun, flexi work hours, up skilling programs, medical insurance for family and parents and ensuring work life balance.e

BE/B.Tech in Electronics, Electrical, Telecommunication, or Instrumentation Key Competencies Required: Electronics control module and electrification product design Analog and sensor interface circuits Microcontroller / microprocessor-based designs Switch-mode and linear power supply design (Buck, Boost converters) EMI/EMC compliance and multilayer PCB design Familiarity with UART, I2C, SPI, RS485, CAN, Ethernet Simulation tools: Pspice, LTSPICE Design tools: Capture, Altium Board debugging tools: Logic analyzers, DSO Signal integrity tools: Hyperlynx, Cadence SI Role Expectations: Requirement analysis Schematic design & development Prototyping & testing Design documentation Lifecycle understanding (DFM/DFT, certifications)