1672 Dft Jobs - Page 2

Position: Hardware Design Manager Years of Experience: 15 Years to 18 Years Education: B.E/B.Tech Electronics/ Electrical/Instrumentation PURPOSE OF THE ROLE This position will lead the overall hardware design function, ensuring the successful development of high-quality, reliable, and cost-effective hardware solutions for Air conditioning products VRF, Residential, Chiller, Heat pump solution. This role requires strong leadership, deep technical expertise in electronic hardware design, and proven experience in managing multi-disciplinary engineering teams. The candidate will be responsible for strategic planning, execution, and delivery of hardware projects in alignment with business goals. Technical Expertise Strong knowledge of power electronics, schematic capture, PCB design tools, and hardware simulation. Understanding of manufacturing processes, DFM/DFT principles. Familiarity with EMI/EMC compliance, thermal management, and reliability Testing. Define the long-term vision, strategy, and roadmap for hardware design. Align hardware design goals with business objectives and market requirements. Drive innovation in design processes, tools, and methodologies. Design and review PCBs, and BOMs for air conditioning control systems. Ensure EMI/EMC compliance, protection circuitry, and thermal management in hardware design. Lead design optimization for cost, manufacturability, and performance. Work closely with firmware teams to define hardware-software interfaces, including ADC/DAC ranges, digital IO behavior, and communication protocols (RS485, CAN, Wi-Fi, BLE, etc.). Perform system-level debugging during development and field issues. Ensure robust design verification and validation processes are followed. Mitigate design risks through FMEA, simulations and rigorous testing. Oversee resolution of field failures and continuous product improvement. Main Responsibilities: Product Hardware Architecture & Specification’s Finalized hardware architecture - Inverter Drive and logic controllers, communication modules, and power boards – for VRF/Residential AC’s/Chiller/Commercial Refrigeration products. Complete hardware design specifications, including control logic, sensing, communication, and safety circuits. Clear interface definitions with firmware/software and mechanical systems. Hardware Design Document’s Approved schematic designs and Bill of Materials (BOM) for each model/variant. Close coordination with PCB layout and part development team, Design calculation sheets for power electronics, control circuits, and protection systems. Updated design standards library (component database, reference designs, PCB stack-up guidelines). Design Verification & Validation Report’s Functional test reports for control boards, inverter boards, and sensor interfaces. EMI/EMC compliance test reports in accordance with HVAC and regional standards. Thermal performance and reliability test documentation. Cost Optimization & Component Strategy / Manufacturing & Quality Readiness Component cost-reduction proposals without compromising performance or reliability. Approved list of alternate components for high-risk/long lead-time parts. Standardization plan for components across product families to reduce procurement complexity. DFM (Design for Manufacturing) and DFT (Design for Test) guidelines incorporated into all hardware. Manufacturing test jig designs and test procedure documentation. Supplier qualification reports for PCB fabricators, component vendors, and assembly houses. Regulatory & Safety Compliance Compliance with HVAC safety standards (e.g., IEC 60335, UL 60335, IS standards for India). Documentation and approvals for electrical safety, energy efficiency, and environmental requirements (RoHS/REACH). Grounding, insulation, and surge protection strategies validated and documented. Cross-Functional & Customer Deliverables / Team Development & Process Improvements Regular hardware progress updates to program management and product teams. Hardware support for field trials and customer evaluations. Root cause analysis and corrective actions for field issues related to hardware. Training plan for hardware design team on new technologies (e.g., high-efficiency inverters, IoT modules). Implementation of design review and approval processes. Continuous improvement of hardware development workflows and tools.

About Us Incygys Group is a fast-growing technology conglomerate with strong footprints in advanced automation, clean air technologies, and smart home/industrial solutions . Under our flagship brands: Invac – Pioneers in wet & dry self-flushing central vacuum systems Inair – Innovators in ventilation equipment including ERVs, inline fans, AHUs, and demand-controlled IAQ systems Incygys Automation – Leading ELV networking and MEP integration services With operations expanding across India, APAC, Middle East, and Europe, we are committed to engineering excellence, sustainability, and cutting-edge product design. Role Overview We are looking for a PCB Design Engineer with 5–6 years of relevant experience who can design, develop, and optimize PCB layouts for our next-generation products across ventilation, automation, and central vacuum technologies. The candidate should have hands-on experience in schematic capture, multilayer board design, EMI/EMC compliance, and manufacturing support , and be able to collaborate with cross-functional teams including R&D, mechanical design, and product engineering. Key Responsibilities (KRAs) PCB Design & Development Design and develop schematics and PCB layouts for power electronics, IoT modules, and control systems. Create multi-layer PCBs ensuring compliance with signal integrity, EMI/EMC standards , and manufacturability. Product Integration Collaborate with firmware and mechanical engineers to ensure smooth integration. Validate designs with hardware testing and debugging. Documentation & Process Generate Gerber files, BoM, fabrication drawings , and design documentation. Support DFM/DFT activities and coordinate with manufacturing vendors. Innovation & R&D Support Contribute to new product development including IoT-enabled control boards for ERV, AHU, and vacuum systems. Explore and implement cost-effective PCB design strategies . Key Performance Indicators (KPIs) On-time delivery of PCB designs and prototypes as per project schedules. First-time-right design success rate (minimal iterations). Compliance with industry standards (IPC, EMI/EMC). Cost optimization in PCB development and vendor coordination. Documentation accuracy and completeness. Required Skills & Qualifications B.E/B.Tech in Electronics/Electrical/Instrumentation Engineering. 5–6 years of hands-on PCB design experience. Proficiency in tools such as Altium Designer, OrCAD, Eagle, KiCad, or similar . Strong understanding of analog/digital circuits, power supply design, microcontrollers, and IoT communication protocols . Knowledge of DFM, DFT, IPC standards, thermal management, and high-speed design . Excellent problem-solving skills and ability to lead junior engineers or external design partners. Why Join Us? At Incygys, you will be part of a multi-brand, innovation-driven ecosystem working on cutting-edge technologies in clean air systems, automation, and IoT. We foster a culture of collaboration, ownership, and continuous growth , giving you the opportunity to contribute to products that impact homes, industries, and communities worldwide.

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

We aspire to be world-leader in innovative telecom and security solutions by offering cutting-edge, high-performance telecom and security solutions to business customers. Our Mission is simple. To prove that Indian engineers can design, develop, and manufacture world-class technology products for customers across the world, right from India. Join our team of like-minded engineers, applied researchers, and technocrats with the will, courage, and madness to achieve this mission! Why work at Matrix Matrix fully integrates software and hardware across its products. Engineers here collaborate more effectively to create solutions that solve real problems and make an impact. We are responsible for every nut, bolt, and line of code in our products! As an engineer, your involvement will be critical in the entire lifecycle of a product - right from ideation-development-production-deployment. Get to feel the sense of accomplishment that comes with creating something that solves a real and pressing problem and is used by scores of customers. Job Description Role : Hardware Design Engineer/ Sr. Engineer - (PCB/ CAD) Function : Hardware Design - (PCB/ CAD) Work Location : Vadodara, Gujarat Who are you You are an energetic and passionate PCB/CAD Design Engineer with a strong background in PCB layout design. You have experience working on high-speed and complex boards, and you excel at using CAD tools to create precise and efficient designs. Your expertise and enthusiasm drive you to tackle challenging projects and deliver high-quality results. Experience : 2+ Years (Freshers can also apply with relevant Internship) Qualification : B.E/ B.tech/ M.E/ M.tech (EC, Electronics & Communication) OR MSc (EC/Electronics) Technical Skills Required : Good understanding of Datasheets, Library creation for Complex Logical and Footprints. IPC Standards for Footprint Creation and Layout process Exposure to all relevant IPC standards & MIL Standard design practices PCB Designing flow from Library creation to Gerber release to FAB. High speed Constraints setting and routing. Should have worked on High Speed signal routing . Hands-on experience in Designing High-speed, Multilayer PCB designs DFM checks, DFx (DFA, DFM & DFT) checks Should have hands-on expertise on standard High Speed Digital, Analog & Mixed signal Design ,I2C,SPI, USB2.0/3.0, Ethernet, PoE, BLE, Wi-fi, GSM, TFT LCD, DDR2/DDR3/DDR4, SD Card, NAND, MIPI , Optical interface etc. DRC and Post-processing (Gerber Settings, FAB & Assembly files generation) Quality checks for Footprints, PCB Layout file, FAB & Assembly files Interaction with Design, Mechanical, SI, PI, Thermal, FAB, Assembly house for Clarification and Reviews Good communication skills and should be able to handle projects independently EDA Tools: Mentor Expedition. Valor Gerber tools for reviews How Your Day Might Look Like Check datasheets to update and create accurate PCB component libraries. Design and adjust PCB layouts following industry standards. Handle the entire PCB design process, from creating libraries to preparing files for manufacturing. Set up and test high-speed signals to ensure everything works properly. Work on complex, multilayer PCB designs, focusing on signal integrity and layout. Perform Design for Manufacturing (DFM) checks to make sure designs are ready for production. Check design rules and finalize files for fabrication and assembly. Review and verify designs with design, mechanical, signal integrity, power integrity, thermal, and assembly teams. Manage your projects, making sure everything stays on track from start to finish. What we offer Opportunity to work for an Indian Tech Company creating incredible products for the world, right from India Be part of a challenging, encouraging, and rewarding environment to do the best work of your life Competitive salary and other benefits Generous leave schedule of 21 days in addition to 9 public holidays, including holiday adjustments to convert weekends into long weekends 5-day workweek with 8 flexi-days months, allowing you to take care of responsibilities at home and work Company-paid Medical Insurance for the whole family (Employee+Spouse+Kids+Parents). Company paid Accident Insurance for the Employee On-premise meals, subsidized by the company

As a PCB Layout Engineer, your role involves interpreting schematics, layouts, BOMs, and datasheets to understand components, their packaging, and PCB requirements. You will be responsible for creating and maintaining schematic symbols and footprints according to ANSI Y32.2 / IEEE 315 (US schematic symbols), IEC 60617 (European standards), and IPC-7351 (land pattern and footprint creation). Utilizing tools like Altium Designer, PADS, and Cadence Allegro, you will design high-quality multi-layer PCBs, optimizing them for DFM, DFT, and DFA with a focus on cost, reliability, and layer reduction. Understanding PCB materials, fabrication processes, soldering standards, and assembly techniques is crucial for this role. Additionally, you will be expected to generate fabrication outputs such as Gerbers, ODB++, drill files, BOMs, Pick & Place, and mechanical drawings, and conduct thorough reviews for design quality, manufacturability, and compliance to standards. Key Responsibilities: - Interpret schematics, layouts, BOMs, and datasheets to understand components and PCB requirements. - Create and maintain schematic symbols and footprints per industry standards. - Design high-quality multi-layer PCBs using Altium Designer, PADS, and Cadence Allegro. - Optimize designs for DFM, DFT, DFA, with a focus on cost, reliability, and layer reduction. - Generate fabrication outputs including Gerbers, drill files, BOMs, Pick & Place, and mechanical drawings. - Conduct thorough reviews for design quality, manufacturability, and compliance to standards. Qualifications Required: - 7+ years of hands-on PCB library management experience including symbol/footprint creation. - Strong understanding of DFM, DFT, DFA. - Proficiency with EDA tools such as Altium Designer, PADS, and Cadence Allegro. - Familiarity with component manufacturers, packages, specifications, and selection criteria. - Ability to interpret datasheets, component specs, and assess mounting/thermal requirements. - Knowledge of IPC standards such as IPC-2221, IPC-7351, IPC-610. - Familiarity with assembly guidelines, soldering standards, PCB materials, and manufacturing processes. Please note that the educational requirement for this position is a B Tech degree in ECE or EEE.,

As a Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. **Key Responsibilities:** - Front-End implementation of MSIP (Temp/Voltage/Security Sensors, Controllers) designs - RTL development and its validation for linting, clock-domain crossing, conformal low power, and DFT rules - Work with functional verification team on test-plan development and debug - Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA - UPF writing, power-aware equivalence checks, and low-power checks - DFT insertion and ATPG analysis for optimal SAF, TDF coverage - Provide support to SoC integration and chip-level pre/post-silicon debug **Qualifications Required:** - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field The company Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to security and confidentiality of company information. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through Qualcomm's Careers Site.,

We aspire to be world-leader in innovative telecom and security solutions by offering cutting-edge, high-performance telecom and security solutions to business customers. Why work at Matrix Matrix fully integrates software and hardware across its products. Engineers here collaborate more effectively to create solutions that solve real problems and make an impact. We are responsible for every nut, bolt, and line of code in our products! As an engineer, your involvement will be critical in the entire lifecycle of a product - right from ideation-development-production-deployment. Get to feel the sense of accomplishment that comes with creating something that solves a real and pressing problem and is used by scores of customers. About The Role Role Hardware Design Engineer/ Sr. Engineer - (PCB/ CAD) Function Hardware Design - (PCB/ CAD) Work Location Vadodara, Gujarat Who are you You are an energetic and passionate PCB/CAD Design Engineer with a strong background in PCB layout design. You have experience working on high-speed and complex boards, and you excel at using CAD tools to create precise and efficient designs. Your expertise and enthusiasm drive you to tackle challenging projects and deliver high-quality results. Experience 2+ Years Qualification B.E/ B.tech/ M.E/ M.tech (EC, Electronics & Communication) OR MSc (EC/Electronics) Technical Skills Required : Good understanding of Datasheets, Library creation for Complex Logical and Footprints. IPC Standards for Footprint Creation and Layout process Exposure to all relevant IPC standards & MIL Standard design practices PCB Designing flow from Library creation to Gerber release to FAB. High speed Constraints setting and routing. Should have worked on High Speed signal routing . Hands-on experience in Designing High-speed, Multilayer PCB designs DFM checks,DFx (DFA, DFM & DFT) checks Should have hands-on expertise on standard High Speed Digital, Analog & Mixed signal Design ,I2C,SPI, USB2.0/3.0, Ethernet, PoE, BLE, Wi-fi, GSM, TFT LCD, DDR2/DDR3/DDR4, SD Card, NAND, MIPI ,Optical interface etc. DRC and Post-processing (Gerber Settings, FAB & Assembly files generation) Quality checks for Footprints, PCB Layout file,FAB & Assembly files Interaction with Design, Mechanical, SI, PI, Thermal, FAB, Assembly house for Clarification and Reviews Good communication skills and should be able to handle projects independently EDA Tools: Mentor Expedition. Valor Gerber tools for reviews How Your Day Might Look Like Check datasheets to update and create accurate PCB component libraries. Design and adjust PCB layouts following industry standards. Handle the entire PCB design process, from creating libraries to preparing files for manufacturing. Set up and test high-speed signals to ensure everything works properly. Work on complex, multilayer PCB designs, focusing on signal integrity and layout. Perform Design for Manufacturing (DFM) checks to make sure designs are ready for production. Check design rules and finalize files for fabrication and assembly. Review and verify designs with design, mechanical, signal integrity, power integrity, thermal, and assembly teams. Manage your projects, making sure everything stays on track from start to finish. What we offer Opportunity to work for an Indian Tech Company creating incredible products for the world, right from India Be part of a challenging, encouraging, and rewarding environment to do the best work of your life Competitive salary and other benefits Generous leave schedule of 21 days in addition to 9 public holidays, including holiday adjustments to convert weekends into long weekends 5-day workweek with 8 flexi-days months, allowing you to take care of responsibilities at home and work Company-paid Medical Insurance for the whole family (Employee+Spouse+Kids+Parents). Company paid Accident Insurance for the Employee On-premise meals, subsidized by the company If you are an Innovative Tech-savvy individual, Look no further. Click on Apply and we will reach out to you soon!

About The Role About The Role Will be responsible for Designing and Implementing DFT techniques. Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression. Implementing, integrating and verifying memory BIST and boundary scan. ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test Coverage and simulations at gate level with timing (SDF). Basic understanding of complete SOC design and flow. Cross functional teams interaction for issue resolution. Participate in driving new DFT methodology and solutions to improve quality, reliability and insystem test and debug capability. Hiring candidate with these specific personal characteristic and qualifications. Mentoring junior engineers and drive innovation/automation. Excellent in problem solving and analytical skills. Excellent communication, team work and networking skills. Primary Skills Should Have Good understanding of Design and DFT Architecture. Should have been part of atlest 3 Tapeout SoC. Well Versed with ATPG Tools & MBIST Tools. Secondary Skills Team Player, Strong Business Acumen with understanding of organizational issues (conflict resolution between stakeholders). Familiarity with Desired Flexibility and adaptability with respect to project management.

Job Title: Computational Chemist Function: Science & Technology Reports to: Research Scientist Scope: PC Location: Unilever R&D Bangalore About Unilever Established over 100 years ago, we are one of the world’s largest consumer goods companies. We are known for our great brands and our belief that doing business the right way drives superior performance. We believe that the winning businesses of tomorrow will be those which anticipate and respond to the huge changes shaping people’s lives across the world. We are more certain than ever that it is the right time to focus our sustainability efforts on the four key priorities where we are best placed to drive impact: climate , nature , plastics and livelihoods . Business Context And Main Purpose Of The Job Personal Care (PC) business is focused on being the best in class company for Personal care products with personalised desirable experiences and beauty solutions for whole-body wellness. The business is committed to address (a) Big Unmet consumer need/insight/idea (b) Right to WIN with superior proposition with product love & noticeable superiority (c). clean beauty product with reduce environmental footprint. The role of the Science and Technology (S&T-PC-Physical science) pillar within R&D is to deliver breakthrough “Differentiated Technologies, with capabilities” to meet PC goals around the world. S&T-PC-Physical science team is focused on building future fit skills team and talent in “Advanced Materials, Measurements delivering long lasting freshness for whole body & personalisation Integrated with Digital”. S&T-PC-Physical science team is employing advanced materials & measurements science for superior multi targeted consumer needs with perceivable efficacy and care across deodorant and skin cleansing category. The teams focus is to deliver faster and cost-effective Innovations through Advanced Material Pillar leveraging “Computational chemistry”. The purpose is to build differentiated innovation roadmap & impactful claims by (a) Developing and applying QSAR models to predict properties like ADMET, binding affinity, or material properties based on molecular descriptors. (b). Performing Density Functional Theory (DFT) and other QM methods to investigate molecular structure. To meet our purpose, we need candidate with expertise in materials design, development, and analytics using digital approach. Main Accountabilities Collaborate with scientists to conduct modelling and simulation projects, presenting results and insights to stakeholders. Adopt AI/ML and deep learning algorithms to develop and test hypotheses relevant to material science. Perform laboratory experiments to validate hypotheses and support simulation results. Streamline modelling workflows to facilitate the adoption of digital tools, enabling quicker insight generation and decision-making. Maintain and expand expertise in materials modelling and simulation by staying updated with the latest research and technological advancements. Enhance team's capabilities in materials design, development, and analytics using digital approach. Support in managing external research programs and data-driven initiatives to advance material science research. Key Interfaces Senior Line manager S&T Programme team S&T Category Discover Leaders Patent attorney Key Skills B.Tech/M.Tech in Chemical Engineering or master’s degree in chemistry / physics / Material Science Specialization in modelling, simulation and ML or minimum 3 years’ experience in modelling and simulation. Strong background in quantum mechanics, molecular modeling, and statistical analysis. Relevant Experience Experience in QSAR modeling, quantum mechanics & DFT. Ability to work multi-functional teams. Experience in experimental research preferably in materials science or a related field. Standard Of Leadership Purpose & Service Personal Mastery Agility Our commitment to Equality, Diversity & Inclusion Unilever embraces diversity and encourages applicants from all walks of life! This means giving full and fair consideration to all applicants and continuing development of all employees regardless of age, disability, gender reassignment, race, religion or belief, sex, sexual orientation, marriage and civil partnership, and pregnancy and maternity. "All official offers from Unilever are issued only via our Applicant Tracking System (ATS). Offers from individuals or unofficial sources may be fraudulent—please verify before proceeding."

Basic qualifications: Strong academic and technical background in electrical engineering. A Bachelor s degree in EE / Computer is required, and a Master s degree is preferred. 8 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Required experience : Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less. Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level. Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production. Experience with Cadence and/or Synopsys physical design tools/flows. Familiarity and working knowledge of System Verilog/Verilog. Experience with DFT tools and techniques. Experience in working with IP vendors for both RTL and hard-mac blocks. Good scripting skills in python or Perl Preferred : Good knowledge of design for test (DFT), stuck-at and transition scan test insertion. Familiarity with DFT test coverage and debug. Familiarity with ECO methodologies and tools. Your base salary will be determined based on your experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the DFT spec, implementation, verification, and Post silicon debug. Job Description In your new role you will: The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the vectors, verification, and Post silicon debug. In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Scripting skills such as PERL/TCL/Python are preferred Your Profile You are best equipped for this task if you have: ASIC flow understanding. Experienced in LEC, CLP, power analysis flow is preferred The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the DFT spec, implementation, verification, and Post silicon debug. In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Scripting skills such as PERL/TCL/Python are preferred Degree & Discipline: BE/B.Tech Electrical/Electronic or ME/M Tech in VLSI design. Experience in Industry: 8+ years of in DFT implementation, verification and post silicon debug areas

Basic qualifications: Strong academic and technical background in electrical engineering. A Bachelor s degree in EE / Computer is required, and a Master s degree is preferred. 10 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Required experience : Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less. Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level. Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production. Experience with Cadence and/or Synopsys physical design tools/flows. Familiarity and working knowledge of System Verilog/Verilog. Experience with DFT tools and techniques. Experience in working with IP vendors for both RTL and hard-mac blocks. Good scripting skills in python or Perl Preferred : Good knowledge of design for test (DFT), stuck-at and transition scan test insertion. Familiarity with DFT test coverage and debug. Familiarity with ECO methodologies and tools. Your base salary will be determined based on your experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

A Day in Your Life at MKS: As a Sr. Electrical Engineer (PCB Designer) at MKS Global Capability Center Bangalore, you will partner with R&D teams across MKS PSD Business Units to deliver high-quality PCB layouts for complex hardware. You Will Make an Impact By: PCB layout of new designs and update of existing designs of complex hardware platforms Complete documentation of designs conforming to MKS documentation standards including Altium database, assembly prints, fabrication prints, Gerber package, ICT testpoint files, etc Cable harness design. Select components based upon availability, cost & technical requirements, and work with drafters to create high quality cable drawings & BOM's. Closely coordinate with US & Europe-based design engineers. Skills You Bring: Experience required: 5+years post educational degree Extensive Altium PCB layout experience with existing portfolio of designs, Altium library management experience preferred Excellent verbal and written communications skills. Knowledge of PCB assembly processes and proven track record of DFM (design for manufacture), DFT (design for test), and DFC (design for cost). Experience with AutoCAD or Draftsight

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER - STA Synthesis THE ROLE: The focus of this role is to plan and execute the front end implementation of IPs and its closure. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on tenchical issues. KEY RESPONSIBILITIES: Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure Collaborate with designer and PNR teams to achieve closure. Understand duration required, plan and execute as per schedule. Complete quality delivery for synthesis and timing closure. Debug and resolve technical issues PREFERRED EXPERIENCE: Highly experienced in synthesis, LEC, CLP and timing closure Prefered top level or SOC level experience Have handled blocks with complex designs, high frequency clocks and complex clocking complete understanding of timing constraints, low power aspects and concepts of DFT Have debug experience to solve issues. scripting and automation ACADEMIC CREDENTIALS: Bachelors with 8 years of experience or Masters degree with 6 years of experience in Electrical Engineering #LI-AB1 Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER - DFT VERIFICATION T HE ROLE : The focus of this role is to strategize, plan, build, and execute DFT verification for AMD s next generation Server SoCs, resulting in no bugs in the final design. Drive post silicon bring up and test program for ATE. THE PERSON: Person is this role should have solid prior DFT verification experience. Expected to be good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. Should process strong analytical and problem-solving skills and willing to learn and ready to take on problems. K EY RESPONSIBLITIES : Develop and execute pre-silicon verification test plans for DFT features of the next gen Zen architecture-based Server SoC. Develop directed and random verification tests to fully validate DFT functionality. Verify DFT design blocks and subsystems (such as JTAG, MBIST, High speed IO PHY, Scan, Security, Fuse, Clocks, Resets, etc.) using complex SV or C++ verification environments. Construct System Verilog and/or C/C++ models and test sequence libraries for simulation. Build test bench components including Agents, Monitors and Scoreboards for DUT. Compose tests, assertions, checkers, validation vectors and coverage bins to ensure verification completeness. Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives. Develop high coverage and cost-effective test patterns, and take part in ATE bring-up. Post silicon ATE and System level debug support of the test patterns delivered. Optimize the test patterns to improve the test quality and reduce test costs. P REFERRED EXPERIENCE : Minimum 10 years of experience in DFT feature verification (such as JTAG, MBIST, SCAN, fuse, IO-PHY loopback testing) Strong background in Verilog, System Verilog (SV), SVA, UVM verification methodologies and C++ Strong debug skills and experience with debug tools such as Verdi Experience with EDA simulation tools like Synopsys VCS, Cadence NCSIM, Verdi Experience with scripting languages like Tcl/Perl/Ruby/Python Working knowledge of Unix/Linux OS, file version control systems ADDITIONAL SKILLS: Experience working on DFT verification for complex SOCs Experience working on multiple SoCs from pre-silicon to post-silicon phase is a great plus Strong analytical/problem solving skills and pronounced attention to details required Excellent written and verbal communication is a must ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electronics engineering/Electrical Engineering #LI-PK2 Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

Job Requirements Job Title: Senior Engineer - Physical Design (PD) Job Type: Full-Time We are seeking a highly skilled and experienced Physical Design Lead in VLSI with a minimum of 3-7 years of experience to join our team. As the Lead Engineer in Physical Design, you will be responsible for overseeing the physical design process, ensuring the successful implementation of complex VLSI designs. esponsibilities: Lead the physical design (PD) team through complete ASIC/SoC implementation flow. Handle floorplanning, partitioning, placement, CTS (Clock Tree Synthesis), routing, and sign-off activities. Drive timing closure, power optimization, area optimization, and DRC/LVS clean designs. Collaborate with RTL, DFT, verification, and package teams to achieve project goals. Manage block-level and chip-level physical design, including hierarchical and flat methodologies. Perform static timing analysis (STA), power analysis, and signal integrity checks. Ensure physical verification, IR drop, and EM analysis closure. Guide junior engineers, review their work, and provide technical mentorship. Drive tool flow automation and efficiency improvements in PD. Interface with customers/stakeholders for updates, reviews, and sign-off. Required Skills: Strong hands-on expertise in physical design tools (Cadence Innovus / Synopsys ICC2 / Mentor). Solid understanding of ASIC design flow and foundry process nodes (7nm/5nm/14nm or relevant). Deep knowledge of STA, power analysis, IR/EM, and physical verification methodologies. Good experience in ECO (Engineering Change Order) flows. Familiarity with scripting languages (TCL, Perl, Python) for automation. Proven experience handling full chip/block-level PD independently. Strong problem-solving and debugging skills. Good communication and leadership abilities to lead a PD team. Education: B. E. /B. Tech or M. E. /M. Tech in Electronics, Electrical, or VLSI Design. Work Experience Required Skills: Strong hands-on expertise in physical design tools (Cadence Innovus / Synopsys ICC2 / Mentor). Solid understanding of ASIC design flow and foundry process nodes (7nm/5nm/14nm or relevant). Deep knowledge of STA, power analysis, IR/EM, and physical verification methodologies. Good experience in ECO (Engineering Change Order) flows. Familiarity with scripting languages (TCL, Perl, Python) for automation. Proven experience handling full chip/block-level PD independently. Strong problem-solving and debugging skills. Good communication and leadership abilities to lead a PD team.

Job Requirements Job Title: Senior Engineer - DFT Job Type: Full-Time We are seeking a Senior Engineer with 2-4 years of experience in MBIST and SCAN, scripting for DFT in the VLSI industry. The ideal candidate will have a strong background in designing and implementing Design for Testability (DFT) solutions, including Memory Built-In Self-Test (MBIST) and Scan Insertion. Key Responsibilities: - Develop and implement DFT methodologies for VLSI designs - Create and execute scripts for DFT tasks - Collaborate with cross-functional teams to ensure successful DFT implementation - Analyze and debug DFT issues to ensure high-quality test coverage - Stay current on industry trends and advancements in DFT technologies Qualifications: - B. E/B. Tech or M. E/M. Tech in Electronics, or related fields. - 2-4 years of experience in MBIST and SCAN, scripting for DFT in the VLSI industry - Proficiency in scripting languages such as TCL, Perl, or Python - Strong understanding of DFT concepts and methodologies - Excellent problem-solving and communication skills If you are a motivated and experienced Engineer with a passion for DFT in the VLSI industry, we encourage you to apply for this exciting opportunity. Work Experience - Develop and implement DFT methodologies for VLSI designs - Create and execute scripts for DFT tasks - Collaborate with cross-functional teams to ensure successful DFT implementation - Analyze and debug DFT issues to ensure high-quality test coverage - Stay current on industry trends and advancements in DFT technologies

Who You'll Work With You will be in the Silicon One development organization as an ASIC DFT Engineer in Bangalore India with a primary focus on Design-for-Test. You will work with DFT Lead, Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Who You Are You are an ASIC Design for Test Hardware Engineer with 4-8 years of related work experience with a broad mix of technologies. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 4 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan insertion and ATPG. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience working with Gate level simulation, debugging with VCS and other simulators. Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Strong verbal skills and ability to thrive in a multifaceted environment Scripting skills: Tcl, Python/Perl. Preferred Skills: Test Static Timing Analysis Post silicon validation using DFT patterns.

Job Requirements Job Title: Lead Engineer - Physical Design (PD) Job Type: Full-Time We are seeking a highly skilled and experienced Physical Design Lead in VLSI with a minimum of 9 years of experience to join our team. As the Lead Engineer in Physical Design, you will be responsible for overseeing the physical design process, ensuring the successful implementation of complex VLSI designs. esponsibilities: Lead the physical design (PD) team through complete ASIC/SoC implementation flow. Handle floorplanning, partitioning, placement, CTS (Clock Tree Synthesis), routing, and sign-off activities.Drive timing closure, power optimization, area optimization, and DRC/LVS clean designs.Collaborate with RTL, DFT, verification, and package teams to achieve project goals. Manage block-level and chip-level physical design, including hierarchical and flat methodologies. Perform static timing analysis (STA), power analysis, and signal integrity checks.Ensure physical verification, IR drop, and EM analysis closure. Guide junior engineers, review their work, and provide technical mentorship.Drive tool flow automation and efficiency improvements in PD. Interface with customers/stakeholders for updates, reviews, and sign-off. Required Skills: Strong hands-on expertise in physical design tools (Cadence Innovus / Synopsys ICC2 / Mentor). Solid understanding of ASIC design flow and foundry process nodes (7nm/5nm/14nm or relevant). Deep knowledge of STA, power analysis, IR/EM, and physical verification methodologies.Good experience in ECO (Engineering Change Order) flows. Familiarity with scripting languages (TCL, Perl, Python) for automation. Proven experience handling full chip/block-level PD independently.Strong problem-solving and debugging skills. Good communication and leadership abilities to lead a PD team. Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design. Work Experience Required Skills: Strong hands-on expertise in physical design tools (Cadence Innovus / Synopsys ICC2 / Mentor). Solid understanding of ASIC design flow and foundry process nodes (7nm/5nm/14nm or relevant). Deep knowledge of STA, power analysis, IR/EM, and physical verification methodologies.Good experience in ECO (Engineering Change Order) flows. Familiarity with scripting languages (TCL, Perl, Python) for automation. Proven experience handling full chip/block-level PD independently.Strong problem-solving and debugging skills. Good communication and leadership abilities to lead a PD team.

Job Requirements We are seeking a highly motivated Trainee Engineer to join our esteemed VLSI Design for Test (DFT) team. The selected candidate will actively participate in design-for-test methodology, with a specific focus on MBIST and scripting for automation. Key Responsibilities: Provide support to the DFT team in the implementation and verification of test structures. Engage in MBIST (Memory Built-In Self Test) design, integration, and validation. Create and maintain automation scripts (TCL/Perl/Python) for design and test flows. Assist in the identification and resolution of DFT-related issues. Collaborate closely with design and verification teams to ensure the delivery of high-quality results. Required Skills: Foundational understanding of DFT concepts (Scan, MBIST). Hands-on experience in MBIST implementation. Proficiency in scripting languages such as TCL, Perl, Python, and Shell. Demonstrated problem-solving and debugging abilities. A strong desire to learn and contribute within a team-oriented environment. Qualification: B.E/B.Tech or M.E/M.Tech in Electronics Work Experience Required Skills: Basic understanding of DFT concepts (Scan, MBIST). Hands-on experience in MBIST implementation. Scripting skills in TCL/Perl/Python/Shell. Good problem-solving and debugging skills. Strong willingness to learn and work in a team environment.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1 Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

Job Requirements Job Title: Senior Engineer - DFT Job Type: Full-Time We are seeking a Senior Engineer with 2-4 years of experience in MBIST and SCAN, scripting for DFT in the VLSI industry. The ideal candidate will have a strong background in designing and implementing Design for Testability (DFT) solutions, including Memory Built-In Self-Test (MBIST) and Scan Insertion. Key Responsibilities: Develop and implement DFT methodologies for VLSI designs Create and execute scripts for DFT tasks Collaborate with cross-functional teams to ensure successful DFT implementation Analyze and debug DFT issues to ensure high-quality test coverage Stay current on industry trends and advancements in DFT technologies Qualifications: B.E/B.Tech or M.E/M.Tech in Electronics, or related fields. 2-4 years of experience in MBIST and SCAN, scripting for DFT in the VLSI industry Proficiency in scripting languages such as TCL, Perl, or Python Strong understanding of DFT concepts and methodologies Excellent problem-solving and communication skills If you are a motivated and experienced Engineer with a passion for DFT in the VLSI industry, we encourage you to apply for this exciting opportunity. Work Experience Develop and implement DFT methodologies for VLSI designs Create and execute scripts for DFT tasks Collaborate with cross-functional teams to ensure successful DFT implementation Analyze and debug DFT issues to ensure high-quality test coverage Stay current on industry trends and advancements in DFT technologies

Job Requirements Job Title: Lead Engineer - DFT We are seeking a highly skilled Lead Engineer with expertise in Design for Test (DFT) to join our team. The ideal candidate will have a strong background in MBIST, SCAN ATPG, and Boundary scan, with hands-on experience in insertion and verification. Proficiency in scripting languages such as Perl and TCL is essential for this role. Key Responsibilities: Develop and implement DFT strategies for complex integrated circuits Collaborate with design and verification teams to ensure DFT requirements are met Conduct MBIST, SCAN ATPG, and Boundary scan testing to ensure high-quality designs Utilize scripting skills to automate testing processes and improve efficiency Qualifications: B.E/B.Tech or M.E/M.Tech in Electronics, or related fields. Good Experience in DFT, with a focus on MBIST, SCAN ATPG, and Boundary scan Proficiency in scripting languages such as Perl and TCL Strong problem-solving skills and attention to detail If you are a motivated engineer with a passion for DFT and a strong background in scripting, we encourage you to apply for this exciting opportunity. Join our team and contribute to the development of cutting-edge technology. Work Experience Develop and implement DFT strategies for complex integrated circuits Collaborate with design and verification teams to ensure DFT requirements are met Conduct MBIST, SCAN ATPG, and Boundary scan testing to ensure high-quality designs Utilize scripting skills to automate testing processes and improve efficiency

Job Requirements We are seeking a highly motivated Trainee Engineer to join our esteemed VLSI Design for Test (DFT) team. The selected candidate will actively participate in design-for-test methodology, with a specific focus on MBIST and scripting for automation. Key Responsibilities: Provide support to the DFT team in the implementation and verification of test structures. Engage in MBIST (Memory Built-In Self Test) design, integration, and validation. Create and maintain automation scripts (TCL/Perl/Python) for design and test flows. Assist in the identification and resolution of DFT-related issues. Collaborate closely with design and verification teams to ensure the delivery of high-quality results. Required Skills: Foundational understanding of DFT concepts (Scan, MBIST). Hands-on experience in MBIST implementation. Proficiency in scripting languages such as TCL, Perl, Python, and Shell. Demonstrated problem-solving and debugging abilities. A strong desire to learn and contribute within a team-oriented environment. Qualification: B.E/B.Tech or M.E/M.Tech in Electronics Work Experience Required Skills: Basic understanding of DFT concepts (Scan, MBIST). Hands-on experience in MBIST implementation. Scripting skills in TCL/Perl/Python/Shell. Good problem-solving and debugging skills. Strong willingness to learn and work in a team environment.

Job Requirements Job Title: Lead Engineer - Physical Design (PD) Job Type: Full-Time We are seeking a highly skilled and experienced Physical Design Lead in VLSI with a minimum of 9 years of experience to join our team. As the Lead Engineer in Physical Design, you will be responsible for overseeing the physical design process, ensuring the successful implementation of complex VLSI designs. esponsibilities: Lead the physical design (PD) team through complete ASIC/SoC implementation flow. Handle floorplanning, partitioning, placement, CTS (Clock Tree Synthesis), routing, and sign-off activities.Drive timing closure, power optimization, area optimization, and DRC/LVS clean designs.Collaborate with RTL, DFT, verification, and package teams to achieve project goals. Manage block-level and chip-level physical design, including hierarchical and flat methodologies. Perform static timing analysis (STA), power analysis, and signal integrity checks.Ensure physical verification, IR drop, and EM analysis closure. Guide junior engineers, review their work, and provide technical mentorship.Drive tool flow automation and efficiency improvements in PD. Interface with customers/stakeholders for updates, reviews, and sign-off. Required Skills: Strong hands-on expertise in physical design tools (Cadence Innovus / Synopsys ICC2 / Mentor). Solid understanding of ASIC design flow and foundry process nodes (7nm/5nm/14nm or relevant). Deep knowledge of STA, power analysis, IR/EM, and physical verification methodologies.Good experience in ECO (Engineering Change Order) flows. Familiarity with scripting languages (TCL, Perl, Python) for automation. Proven experience handling full chip/block-level PD independently.Strong problem-solving and debugging skills. Good communication and leadership abilities to lead a PD team. Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design. Work Experience Required Skills: Strong hands-on expertise in physical design tools (Cadence Innovus / Synopsys ICC2 / Mentor). Solid understanding of ASIC design flow and foundry process nodes (7nm/5nm/14nm or relevant). Deep knowledge of STA, power analysis, IR/EM, and physical verification methodologies.Good experience in ECO (Engineering Change Order) flows. Familiarity with scripting languages (TCL, Perl, Python) for automation. Proven experience handling full chip/block-level PD independently.Strong problem-solving and debugging skills. Good communication and leadership abilities to lead a PD team.