ASIC Verification Engineer

Atos

3 - 5 years

5 - 9 Lacs

bengaluru

Posted:3 days ago| Platform:

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Skills Required

object oriented programming system verilog asic verification systemc uvm soc verification design verification digital design vhdl verilog hdl rtl design axi rtl coding ahb perl i2c asic sta vlsi design ovm rtl spi verilog asic design pcie vlsi

Work Mode

Work from Office

Job Type

Full Time

Job Description

Education:Bachelors degree (BE/B.Tech)orMasters degree (ME/M.Tech)

Roles & Responsibilities:

Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team.
Write and perform the test plan in close cooperation with the logical design team.
Develop coverage models and verification environments using UVM-SystemVerilog C++. Write, maintain and publish the verification specification.
Monitor, analyze and debug simulation errors.
Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time.
Produce a maintainable and reusable code across projects

Required Skills and Experience

Curious, demanding and rigorous.
Mastering object oriented programming.
Knowledge of UVM verification methodology (or equivalent) and SystemVerilog SystemC hardware verification languages
Knowledge of Constraint-Random Coverage-Driven verification environments development in SystemVerilog C ++ (drivers monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp SVA)
Knowledge of simulation tools and coverage database visualization tools
Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints.

Our Offering:

Competitive salary package
Leave Policies: 10 Days of Public Holiday (Includes 2 days optional) & 22 days of Earned Leave (EL) & 11 days for sick or caregiving leave.
Benefit Plans (Insurance) Medical & Life & Accidental & EDLI

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