ASIC Verification Engineer

As an ASIC Verification Engineer, you will collaborate with design and verification engineers to develop and execute robust verification strategies. You will be responsible for creating and maintaining testbenches and test cases aligned with test plans and design specifications. Additionally, you will develop, enhance, and maintain UVM-based verification frameworks to ensure the reliability of ASIC design. Your role will involve delivering automated regression suites to reduce risk and contribute to unit-level and system-level verification deliverables for complete test coverage. Furthermore, you will design and maintain a verification environment for testing RTL implementations against reference models developed in MATLAB and Python. You will also execute and automate regression test runs across design iterations and analyze code and functional coverage to provide detailed feedback and recommendations to the design and verification teams. Your responsibilities will include generating and presenting verification reports, highlighting test results, coverage metrics, and improvement areas. Qualifications: - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. - 5+ years of experience in ASIC verification or digital design verification. - Strong proficiency in SystemVerilog for functional verification. - Hands-on experience with UVM (Universal Verification Methodology). - Familiarity with Cadence Xcelium or similar industry-standard simulators. - Excellent analytical and problem-solving skills with a strong attention to detail. Preferred Skills: - Experience working in Linux-based environments. - Proficiency in scripting languages such as Python or TCL for test automation. - Understanding of DSP algorithms and mixed-signal verification concepts. The company provides dental insurance, health insurance, and vision insurance as part of the benefits package. This is a full-time, contract position with an in-person work location.,