110 Systemc Jobs

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Required education Bachelor's Degree Required technical and professional expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails

As an experienced Functional Formal Verification Engineer, you will be leading the formal verification efforts for complex digital designs. You will play a critical role in ensuring the quality and reliability of our digital designs. **Key Responsibilities:** - Lead complete formal verification for single or multiple design blocks and IPs, including developing and implementing formal verification strategies and test plans. - Create comprehensive formal verification test plans and specifications to ensure thorough coverage of design functionality. - Prove design properties, identify bugs, and collaborate with design teams to improve micro-architectures and ensure design correctness. - Craft innovative solutions for verifying complex design architectures, including developing re-usable and optimized formal models and verification code bases. - Mentor junior team members and provide technical leadership in formal verification methodologies, including training and guidance on industry-standard tools and techniques. - Collaborate with cross-functional teams, including design and verification, to ensure seamless integration of formal verification into the overall verification flow. **Qualifications:** - Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field. - 10+ years of experience in formal verification of complex IP/SubSystem/SoCs, with a strong understanding of digital logic design and verification techniques. - Expertise in formal verification tools and property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog, or VHDL. - Experience with industry-standard EDA formal tools. - Experience with scripting languages (e.g., Python, Tcl, Perl) and programming languages such as C/C++/SystemC. - Excellent problem-solving and analytical skills, with the ability to debug complex issues and optimize verification performance. - Strong communication and interpersonal abilities, with experience working in a team environment and collaborating with cross-functional teams. - Proven track record in technical leadership and mentoring, with experience guiding junior engineers and contributing to the development of formal verification methodologies. The company is looking for someone with experience in CPU, GPU, or other complex digital architectures, including knowledge of industry-standard protocols (e.g., AXI, CHI, PCIe). Familiarity with UVM methodology and/or other simulation-based verification methodologies is preferred. Additionally, expertise in Jasper or VC Formal products is highly desirable.,

We are seeking an experienced System on Chip (SoC) Architect to join our development team. The ideal candidate will be involved in designing, integrating, and optimizing SoC hardware architectures and ensuring seamless software-hardware co-development. You have: Bachelors Degree in Electrical Engineering, Computer Engineering, or a related field (Masters or Ph.D. preferred). Overall,15+ years of experience as a Chip design expert. 8+ years of proven experience in IC design, SoC architecture, or a similar role. Proficiency in hardware description languages: Verilog, VHDL, and System Verilog Expertise in EDA tools for IC design and verification: Mentor Graphics, Cadence, or Synopsys Strong understanding of SoC architecture, including processor, memory subsystem, and interconnects (e.g., AXI, AMBA). Experience with hardware-software co-design and debugging tools. Knowledge of low-power design techniques and methodologies. Strong scripting skills in Python, Tcl, or Perl for automation. Tools : MATLAB/Simulink, Microsoft Visio, Mentor Graphics QuestaSim It would be nice if you also had: Familiarity with high-level modeling tools like SystemC. Knowledge of advanced packaging technologies (e.g., Chiplets, 3D ICs). Exposure to machine learning or AI accelerators in SoC design. Develop SoC architectures for advanced applications, ensuring scalability, performance, and power efficiency Lead hardware design and integration processes, including RTL coding, synthesis, and verification Collaborate with software teams to ensure efficient software-hardware co-design and integration Perform system-level modeling and simulations to validate architectural choices Guide SoC implementation, including floor planning, physical design, and timing closure Follow best practices for IC design and manufacturing Analyze system requirements, identify bottlenecks, and propose innovative solutions

Experience : 3 to 10 Years Qualification : Bachelors or Masters (Electronics and Communication Engineering or equivalent) Job Description: As an Emulation Engineer, youll be an integral part of a dynamic team dedicated to creating cutting-edge ASIC solutions for High-Performance Computing (HPC) systems. Your role will involve defining the validation strategy leading to functional sign-off for these high-performance computing designs. Key functions and responsibilities: Proficient in various emulation technologies, including simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods. Familiarity with tools such as Palladium, Protium, Veloce, or Zebu. Good Knowledge of SystemC/C/C++ and UVM/SV verification languages Experience with SystemVerilog and C++ for modelling RTL components and transactors. Ability to develop C/C++/SystemC/SV tests in HDL-HVL (Hardware Description Language-Hardware Verification Language) Co-emulation platforms. Understanding of compilation and build flow. Skilled at building images from scratch, making necessary design modifications to adapt to emulation. Work closely with verification teams to define and implement comprehensive pre and post silicon test plans. Interface effectively with design, verification, validation, and software development teams to understand their needs from an emulation perspective. Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip systems). Balancing performance and ease of debug. Proficient in post-silicon bring-up, debugging, and issue reproduction on emulators. Familiarity with Python and TCL scripting languages. Exposure to domains such as PCIe, CXL, DDR, Flash, Memory, USB, and CPU. Strong communication and collaboration skills to work effectively with cross-functional teams and domain experts. Successfully manage multiple design releases and provide support for debugging customer issues.

You will be part of the HDD modelling team at Western Digital, where you will be responsible for developing, maintaining, and testing the SoC models using C#. These models capture the register accurate functionality of the controller chip managing the HDD/NAND storage, helping in shortening clients" SDLC and facilitating the shift left paradigm. Your key responsibilities will include: - Understanding SoC and Memory Architecture and developing C# based models - Implementing new HW IPs/features in the model - Debugging and fixing issues in Co-Simulation Environment - Interacting with other teams/groups to debug failures and root-cause issues - Continuous interaction with Design/Verification teams - Partnering with firmware development in embedded C++ using latest standards - Participating in SCRUM/Agile processes following SAFe - Delivering cutting-edge storage products with interfaces like SAS, SATA, PCIe - Collaborating with cross-functional teams to develop HDD products - Understanding the end-to-end product lifecycle Qualifications required for this role: - 4-7 years experience with Bachelors or 2-5 years with Masters in CS, CE, EE, EC or equivalent - Good knowledge and hands-on experience of C#/C++/SystemC - Understanding of C#/C/C++, Object-oriented programming, Data Structure, Algorithms, Multi-threaded programming - Prior experience in low-level firmware development - Excellent grasp of Digital Logic Fundamentals - Understanding of micro-controller architecture, embedded systems - Ability to rapidly learn new technologies, complex code, and develop system architecture view - Strong problem-solving, algorithm design, system design, and complexity analysis skills - Technical mindset with attention to detail and a positive attitude - Use of out-of-box thinking for creative solutions - Excellent interpersonal skills, including written and verbal communication Preferred qualifications include previous RTOS experience, working experience with scripting languages, and knowledge of Memory (SRAM/DRAM/ROM/Flash). Western Digital thrives on diversity and believes in creating an inclusive environment where every individual can thrive. If you require any accommodation during the hiring process, please contact staffingsupport@wdc.com with your specific request.,

About The Role Project Role : Business Process Architect Project Role Description : Analyze and design new business processes to create the documentation that guides the implementation of new processes and technologies. Partner with the business to define product requirements and use cases to meet process and functional requirements. Participate in user and task analysis to represent business needs. Must have skills : Vmware Virtualization Administration Good to have skills : NA Minimum 12 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Business Process Architect, you will analyze and design new business processes, creating documentation that guides the implementation of innovative processes and technologies. Your typical day will involve collaborating with various stakeholders to define product requirements and use cases, ensuring that business needs are accurately represented through user and task analysis. You will engage in discussions that shape the future of business operations, working diligently to align technology solutions with organizational goals and objectives. Roles & Responsibilities:- Expected to be an SME.- Collaborate and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Conduct performance assessments and recommend improvements based on findings.- Facilitate knowledge sharing sessions to enhance team capabilities.- Deploy, maintain, and operate the virtualization infrastructure in strict adherence with the defined procedures with the aim of highest operational stability.- Execute, maintain and improve the operational processes and activities, deliver according to the highest quality and standards, ensuring high service delivery levels, compliance and customer satisfaction.- Conduct incident investigation, communication and resolution.- Perform out of business hours support activities and participate to on-call rotation.- Create, maintain and report KPIs.- Support internal and external audits activities, as well as resolution of findings.- Strictly adhere to corporate processes, standards, policies and operational procedures.- Investigate and implement operations automation where relevant. Professional & Technical Skills: - Must To Have Skills: Proficiency in VMware Virtualization Administration.- Good To Have Skills: Experience with Nutanix Administration.- Strong understanding of performance testing methodologies and tools.- Experience in capacity planning and application performance management.- Proficient in problem detection and resolution techniques.- Excellent knowledge of the following solutions and technologies:RHEL, VMware ESX in a stretched cluster deployment, VMware VCF, disk storage replication, Python, Ansible, Terraform, Jira. Knowledge of alternative hypervisor solutions such as Nutanix or Huawei DCS is a plus.- Very strong customer-oriented mindset and attitude, experience in interacting with both internal and external customers.- Previous experience (5 years) in a similar role operating a highly critical virtualization infrastructure within a financial environment. Additional Information:- The candidate should have minimum 7-10 years of experience in VMware Virtualization Administration.- This position is based at our Hyderabad office.- A 15 years full time education is required. Qualification 15 years full time education

We are looking for highly skilled and motivated System-on-Chip & FPGA Performance Modeling architects who will be responsible for developing and simulating models of performance critical hardware components. As a member of the Architecture team, you will collaborate closely with fellow architects and designers to explore early design space across potential architectures at FPGA level, interconnect level, and within subsystems. Your primary goal will be to achieve best-in-class Power, Performance and Cost as a function of features. You will take ownership of performance throughout the development lifecycle, starting from concept development, design, all the way to silicon validation. This role requires cross-team collaboration involving architecture exploration, TLM model development, workload analysis, performance evaluation, correlation to cycle-accurate RTL and Silicon, and enabling customers to evaluate the performance of their FPGA systems. The ideal candidate should possess strong C++ and SystemC coding skills for developing TLM2.0 performance models, testbenches, and workloads. Additionally, knowledge of data movement within modern SoC architectures such as interconnect, DDR, PCIe, Ethernet, and embedded processors is required. Familiarity with state-of-the-art Performance modeling methods with a focus on realizable performance in the final product is crucial. While FPGA knowledge is a plus, it is not essential. Candidates with a Bachelors, Masters, or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field are encouraged to apply for this position.,

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: Minimum Qualifications Previous experience working on complex high-performance RTL design, preferably on DSP or processor based sub-system. Expert in hardware (RTL) design in Verilog, System Verilog or VHDL. Knowledge of standard on chip bus interface protocols (AXI, APB, AHB) Experience with some of below. Model development (SystemC, or C++) RTL to gates synthesis (Synopsys DCG or Cadence Genus) Design rule and CDC checking (SVA assertions, Spyglass, 0-in) Work on high performance low power RTL design. Scripting languages (PERL, Python, TCL, C, etc.) PRINCIPAL DUTIES AND RESPONSIBILITIES: Develop micro-architecture, design and program specific documentation Design and modelling of compute ASIC modules and sub-systems. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Resolves architecture, design, or verification problems by applying sound ASIC engineering practices Use of various design tools (Synopsys, Compiler Linting, CDC, LEC, CLP etc.) to check and improve design quality Help the design verification team execute on the functional verification strategy. Generates innovative ideas for IP core and process flow improvements Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: QCT's Bangalore Wireless R&D HW team is looking out for experienced Wireless Modem HW model developers to work on Qualcomms best in class chipsets in modem WWAN IPs Roles and Responsibilities You will be contributing to flagship modem core IP development covering 5G(NR) & 4G (LTE) technologies. You will be part of team defining and developing next generation multi-mode 5G modems. You will be working on development and verification of HW models of modem core IP. The models are developed on C++/SystemC platform and used as golden reference for RTL verification and pre Silicon FW development ( virtual prototyping). The candidate must be well versed with C++ and should have good exposure to SystemC and/or System Verilog and/or Matlab. The candidate must have ability to understand HW micro-architecture & its modeling abstraction. Working knowledge of physical layer of wireless technologies like NR,LTE , WLAN, Bluetooth is highly desired. Expertise on digital signal processing and working experience on HW modeling and/or RTL design/ verification of IP are preferred. Candidates with SW/FW background on wireless IP can also apply. Candidates with strong technical knowhow on non-wireless DSP based HW IPs ( with Design / Verification/ Modeling skills) will also be considered. Minimum qualification : Bachelors or Masters in Electrical/Electronics/Computers Science from reputed college/university. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area :Engineering Group, Engineering Group > Systems Engineering General Summary: We are seeking a highly experienced Network-on-Chip (NoC) Architecture and Systems Engineerto join our innovative and dynamic NoC systems team. The ideal candidate will have a deep understanding of NoC architectures, system design, and various communication protocols such as PCIe, CXL, and AMBA CHI. This role involves designing, implementing, and optimizing NoC solutions for complex SoC (System on Chip) designs, collaborating with cross-functional teams, and driving research and development initiatives to stay at the forefront of technology. Key Responsibilities: Architecture Design: Develop and optimize NoC architectures for high-performance SoC designs, including routers, interconnects, and communication protocols. Protocol Expertise: Design and implement NoC solutions that support various communication protocols such as PCIe, CXL, and AMBA CHI. System understanding: Understanding of NoC solutions for overall SoC design, ensuring seamless communication between various IP blocks and subsystems. Performance Analysis: Conduct detailed performance analysis and benchmarking of NoC designs to identify bottlenecks and areas for improvement. Collaboration: Work closely with hardware, software, and verification engineers to ensure that NoC designs meet system requirements and performance goals. Troubleshooting: Identify and resolve complex issues in NoC design and simulation. Research and Development: Stay updated with the latest advancements in NoC technology and contribute to the development of new methodologies and tools. Actively participate in research projects to explore new NoC architectures and protocols. Primary Skills Proficient in NoC design and optimization techniques. Strong understanding of digital design principles and SoC architecture. Experience with hardware description languages (HDLs) such as Verilog. Familiarity with SystemC and C++ for modeling and simulation is a plus. Knowledge of NoC simulation tools and environments is a plus (e.g., Gem5, Noxim). Experience with performance analysis and benchmarking tools. Expertise in various communication protocols such as PCIe, CXL, and AMBA CHI is a plus. Soft Skills Excellent problem-solving and analytical skills. Strong communication and collaboration abilities. Ability to work independently and in a team environment. Attention to detail and a commitment to quality. Enthusiasm for research and innovation. Preferred Skills: Experience with Network-on-Chip, high-performance computing and parallel processing. Knowledge of ASIC design flows. Familiarity with scripting languages (e.g., Python, Perl). Experience with version control systems (e.g., Git). Background in NoC design, NoC Architecture, low-power design and optimization. Publication history in relevant technical journals or conferences. Qualifications: Education: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 6 to 11 years of experience in NoC architecture and systems design. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. ORPhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field.

General Summary: Adreno GPU has been the industry leading mobile graphics solution and has been the dominating GPU in todays smart phone market. Our power efficient GPU solution is fundamental to enable the exciting new markets like VR, IoT, AI, drone, autonomous driving etc. We are looking for talented Graphics System engineers to create world class GPU products to enable high performance graphics and compute with low power consumption. As a member of our Graphics System team, you will help create the simulator of our next generation graphics core for mobile devices. In this position, you will be responsible for development of the GPU architecture design using advanced modeling methodologies. You are expected to understand the design and implementation, define the development scope, develop the algorithm for some functional blocks, and verify the correctness of the design. You will be working with architects, designers, driver, and compiler teams to accomplish your tasks. Develop bitwise accurate functional models (C-model) (by using C/C++ etc.) to simulate our new architectures and solutions Develop solid test suites and perform functional verification & validation with the C-Model and RTL simulation Perform conformance tests, stress & random tests and stabilize GPUs & Compute systems Additional Job DescriptionAdditional Job Description Critical Must Have skills/experience for role Good understanding of modern 3D graphics pipeline. Programming experience in graphics or compute using API like DirectX, OpenGL OpenCL, Vulkan. Programming experience in modeling using C++ and good understanding of computer/GPU architecture and pipeline. Debugging and problem-solving skills. Ability to write clean, professional & maintainable code in C++. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. ORPhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. Preferred skills/experience for role: Knowledge ongraphics/ray-tracing/computearchitecture & pipeline (e.g., DirectX, OpenGL, OpenCL, Vulkan, etc.)C/C++/Perl/Pythonprogramming language Good communication skills and ability & desire to work as a team player. SystemC and TLM experience are desirable Agile development methodology experience is preferable Graphics & compute driver or compiler experience is a plusVerilog/Vera/SystemVerilogexperience is a plus Required :Minimum Qualifications- Bachelor's or higher degree in Computer Engineering, Computer Science, Electrical Engineering, or related field.- 8+ years Systems Engineering or related work experiencePreferred Qualifications:- Master's or higher degree in Computer Engineering or Computer Science.- 7+ years Systems Engineering or related work experience

General Summary: Job Summary: We are seeking a highly motivated and skilled Performance and Power Analysis Engineer to join our Display Systems team in Bengaluru. In this critical role, you will be responsible for the analysis, modeling, and optimization of performance and power consumption across various stages of our cutting-edge chip development process. You will take the lead and collaborate closely with architecture, design, Software and verification teams to ensure our products meet stringent performance targets and power efficiency requirements. As an independent collaborator, contribute with cross functional teams, SoC performance and SW/HW teams to enhance or optimize the process. This is an exciting opportunity to contribute to the development of next-generation semiconductor technology. Responsibilities: Develop and maintain architectural-level and/or cycle-accurate models for performance and power estimation. Analyze trade-offs between performance, power, and area (PPA) at the architecture and microarchitecture levels. Drive performance and power analysis early in the design cycle to influence architecture and design decisions. Collaborate with architecture and design teams to explore and evaluate different design options and trade-offs to optimize performance and power. Conduct detailed analysis to identify performance bottlenecks and power inefficiencies in chip architectures and microarchitectures. Perform power profiling and characterization of designs under various operating conditions and workloads. Develop and implement power reduction techniques at different design stages (e.g., clock gating, power gating, voltage scaling). Analyze and debug performance and power-related issues during simulation, emulation, and silicon bring-up. Generate comprehensive reports and presentations summarizing analysis results and providing actionable recommendations to the design teams, cross-functional teams and senior leadership. Stay abreast of the latest industry trends, tools, and methodologies in performance and power analysis. Contribute to the development and improvement of internal tools and flows for performance and power analysis. Collaborate with verification teams to define and execute performance and power validation plans. Validate model accuracy through correlation with RTL simulations, emulation, and silicon measurements. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. ORPhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 8+ years of experience in performance and power analysis for ASIC or SoC designs. Strong understanding of computer architecture, microarchitecture, and digital design principles. Strong experience in developing and utilizing performance and power models using languages such as SystemC, Python, C++, or custom in-house frameworks. Proficiency in using industry-standard performance and power analysis tools (e.g., Synopsys PrimeTime PX) Solid understanding of power management techniques and low-power design methodologies. Experience with simulation and emulation environments. Strong analytical and problem-solving skills with the ability to interpret complex data and draw meaningful conclusions. Excellent communication and interpersonal skills with the ability to collaborate effectively with cross-functional teams. Familiarity with silicon bring-up and post-silicon power/performance characterization is a plus. Experience with machine learning techniques for power/performance prediction is a plus. Experience with IOS and Xcode profiling/development is a plus

General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field.

General Summary: Highly skilled SystemC Modeling Engineer is required to join dynamic and innovative NoC Systems team in Qualcomm Bangalore Design Center. The ideal candidate will have a strong background in digital design and a deep understanding of SystemC for hardware modeling and simulation. This role involves developing and maintaining high-quality SystemC models for complex digital systems, collaborating with cross-functional teams, and ensuring that Qualcomm products meet the highest standards of performance and reliability. Key Responsibilities: Model Development: Design and implementation of SystemC models for digital systems, including processors, memory controllers, and peripheral interfaces. Methodology: Awareness of Virtual prototypes and Performance modeling using C++/SystemC/TLM 2.0. Approximately timed and Loosely Timed(LT) style of coding for software development when using Virtual Prototype Verification: Development and executution of testbenches to verify the correctness and performance of SystemC models. Optimization: Optimization of models for simulation speed and resource efficiency. Documentation: Creation and maintenance of detailed documentation for models, testbenches, and verification plans. Collaboration: Work closely with hardware and software engineers to ensure seamless integration of SystemC models into the overall system design. Troubleshooting: Identify and resolve issues in the modeling and simulation process. Research: Stay updated with the latest advancements in SystemC and digital design techniques. Technical Skills Proficient in SystemC and C++. Strong understanding of digital design principles and techniques. Experience with hardware description languages (HDLs) such as Verilog is a plus. Familiarity with simulation tools and environments is a plus. Soft Skills Excellent problem-solving and analytical skills. Strong communication and collaboration abilities. Ability to work independently and in a team environment. Attention to detail and a commitment to quality. Preferred Skills Experience with Network-on-chip, high-performance computing and parallel processing. Knowledge of ASIC design. Familiarity with scripting languages (e.g., Python, Perl). Experience with version control systems (e.g., Git). Qualifications: Education: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 5 to 10 yearsof experience in digital design and SystemC modeling. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. ORPhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

You will be responsible for developing Simulation models of IBM Enterprise Power Systems and Processors. You will work on design, development, test and support of the Simulation models for IBM Power Servers. You will be involved in defining and implementing high performance software by demonstrating a strong understanding of Embedded Hardware Design. You will contribute in developing an environment of continuous improvement across product lines and development groups. Define, design, implement and test software applications using a variety of technologies, including, but not limited toC/C++, Linux, Python, GIT and scripting languages. Interact with the test team to define test plans and test data; identify reproduce and defects; fix and verify defects. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 6+ years of Firmware / Simulation design and development experience. Strong understanding of the CPU Architecture Experience to the Processor or other Hardware Simulation Should be able to understand the Processor Instruction Set Proven Programming skills in C Programming and Python scripting Good knowledge of low level software stacks , operating systems and device drivers. Experience with Git, Gerrit , Jenkins , Perl / Python. Knowledge to enterprise server domain and its firmware development. Experience with simulation tools and languages like Simics, QEMU, SystemC or Virtualizer on Linux is required Experience with virtual platform development and bringup of firmware is required. Exposure to Agile methodology with project management and defect tracking with Jira, Github, Bugzilla or similar. Understanding of code versioning and test CI tools like Git Hub Enterprise, Gerrit and Jenkins or Travis. Preferred technical and professional experience QEMU model development experience C proficiency.

General Summary: Today, more intelligence is moving to edge devices, and mobile is becoming the pervasive AI platform. Building on the smartphone foundation, Qualcomm envisions making AI ubiquitous - expanding beyond mobile and powering machines, vehicles, and Internet of things. Be part of the group that is working on technology which will bring cognition to all connected devices. Join the machine learning team responsible for ASIC IP design and integration of leading-edge technologies in the area of image post processing, machine learning, and IoT. We are searching for a lead ASIC Design Engineer to be part of the AI Processor Design Team responsible for developing hardware to support AI/ML and video processing systems. Preferred Qualifications Masters- Electrical Engineering , Computer Engineering, Exposure to functional safety, Automotive(ASIL) ASIC design. Experience with cache control and/or video processing function design/verification Detail oriented with strong analytical and debugging skills Strong communication (written and verbal), collaboration, and specification skills Ability to work well in a team and collaborate with your colleagues worldwide Minimum Qualifications Previous experience working on complex high-performance RTL design, preferably on DSP or processor based sub-system. Expert in hardware (RTL) design in Verilog, System Verilog or VHDL. Knowledge of standard on chip bus interface protocols (AXI, APB, AHB) Experience with some of below. Model development (SystemC, or C++) RTL to gates synthesis (Synopsys DCG or Cadence Genus) Design rule and CDC checking (SVA assertions, Spyglass, 0-in) Work on high performance low power RTL design. Scripting languages (PERL, Python, TCL, C, etc.) PRINCIPAL DUTIES AND RESPONSIBILITIES: Develop micro-architecture, design and program specific documentation Design and modelling of compute ASIC modules and sub-systems. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Resolves architecture, design, or verification problems by applying sound ASIC engineering practices Use of various design tools (Synopsys, Compiler Linting, CDC, LEC, CLP etc.) to check and improve design quality Help the design verification team execute on the functional verification strategy. Generates innovative ideas for IP core and process flow improvements Level of Responsibility: Working independently with little supervision. Making decisions that are moderate in impact; Using deductive and inductive problem solving; multiple approaches may be taken/necessary to solve the problem; often information is missing or incomplete; intermediate data analysis/interpretation skills may be required. May be solicited during strategic planning period. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

General Summary: As a Qualcomm Systems Engineer, you will research, design, develop, simulate, and/or validate systems-level software, hardware, architecture, algorithms, and solutions that enables the development of cutting-edge technology. Qualcomm Systems Engineers collaborate across functional teams to meet and exceed system-level requirements and standards. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. ORPhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. Job Overview Work with Qualcomm's security architecture / IP and access control team on next generation SOC for smartphone, tablet, automotive and IOT product categories. is responsible for assisting product development teams throughout the company to apply secure HW design principles to individual blocks, computing cores, and at the SoC level. SW/HW co-design, HW development experience. Familiarity with debug architectures such as JTAG and ARM coresight are a plus Successful candidates will be able to engage with product teams independently with minimal supervision to detect and mitigate security vulnerabilities in hardware architecture and implementations, involve in access control issues at both SW and HW. Minimum Qualifications 6 to 12 years of industry or academic experience in Security are required. Additionally, applicants must have expertise in two or more of the following areas: Computer architecture and hardware based or assisted access control and security Mobile platform security, Secure Boot, Secure Storage, Access Control, Secure Debug, DDR protection ARM TrustZone, Virtualization Operating system security and hypervisor security languages: C/C++, Python, RTL Teamwork across various teams and geolocations. Able to communicate in English, both verbal and written. Preferred Qualifications The following skills/experience will be considered a plus: ARM architecture SoC security design Applied Cryptography Trusted Computing Working Knowledge on hardware firewalls for access control Knowledge on AI/ML is added advantage SystemVerilog, VHDL, Verilog, SystemC - FPGA/ASIC design is a plus Side channel attacks, power analysis and timing attacks on crypto elements is a plus Memory technology (DDR4, DDR5), storage technologies is (eMMC, UFS) is a plus Educational Requirements: Required: Bachelor degree and above, Computer Engineering and/or Electrical Engineering Experience Requirements: Bachelors/ Masters with 5-7+ years Systems Engineering or related work experience

We are seeking a skilled Embedded SystemC Architect with over 10 years of experience to take charge of designing and developing high-performance virtual platforms and system-level models in Bangalore. As an Embedded SystemC Architect, you will play a crucial role in creating SystemC/TLM 2.0 models for various SoC components and virtual platforms, along with developing and enhancing embedded software and firmware elements in C/C++. Your expertise in SystemC modeling, SoC architecture, and solving intricate hardware-software interaction issues will be pivotal in this position. Your responsibilities will include designing and implementing SystemC/TLM 2.0 models for SoC components and virtual platforms, creating and managing embedded software and firmware components in C/C++, optimizing models for CPU, memory subsystems, hardware accelerators, and bus protocols, modeling peripherals such as Timers, DMA Controllers, and I/O devices, collaborating with hardware and software teams for co-simulation and integration, as well as mentoring junior engineers and leading technical discussions related to modeling and simulation. Key Requirements: - Proficiency in SystemC and TLM 2.0. - Strong command over C/C++ programming with a profound knowledge of Object-Oriented Programming (OOPS). - Hands-on experience in embedded software/firmware development. - Extensive understanding of SoC architecture, including CPU pipelines, GPUs, memory controllers and subsystems, hardware accelerators, and bus protocols (AXI, PCIe, USB). - Experience in modeling embedded peripherals. - Exposure to PSoc programming. Desired Skills: - Previous experience in developing Virtual Platforms (VPs) for semiconductor or embedded products. - Familiarity with simulators like QEMU, Synopsys Virtualizer, or equivalents. - Knowledge of hardware/software co-simulation methods. - Understanding of Verilog/SystemVerilog for hardware design analysis. If you are passionate about embedded systems, SystemC modeling, and SoC architecture, and possess a strong technical background in the mentioned areas, we encourage you to apply for this challenging and rewarding role as an Embedded SystemC Architect.,

Qualcomm India Private Limited is the innovation leader in the area of integrated chipsets that power advanced mobile devices, multimedia platforms, and varied Automotive solutions. By enabling advanced ADAS and IVI capabilities in automotives, Qualcomm is expanding its reputation as the industry powerhouse for innovation. Join Qualcomm and become part of the growing Automotive systems team that innovates to bring higher performance at low power consumption and device cost, while providing the strongest feature differentiation. We are seeking system engineers with 5-10 years of experience for our efforts in the performance modeling/evaluation and architecture of our automotive hardware. Successful candidates will get an opportunity to work in a fast-paced environment on cutting-edge technologies that span multimedia, Compute, and Machine learning technologies. The responsibilities of this role may include designing and maintaining transaction accurate static models for compute IPs, performance validation, debugging performance issues in pre/post silicon platforms, architecture analysis for performance optimization, defining use-case flows for automotive use cases, understanding product features, evaluating their impact on system performance, and collaborating with product marketing and customers to provide the best possible feature support at given system configurations. Qualifications: - 5-10 years of Systems Engineering or related work experience - Strong analytic and problem-solving skills - Proficiency in C/C++, SystemC, python - Good understanding of computer architecture and SoC infrastructure - Strong systems mindset for analyzing power, performance, area, and architecture - Knowledge of typical multimedia flows is a plus - Experience in debugging system performance issues and performance modeling/verification is a plus - IP HW architecture experience and automotive experience are advantageous Educational Requirements: - Bachelor's degree in Computer Engineering, Computer Science, or Electrical Engineering - Master's degree in Computer Engineering, Computer Science, or Electrical Engineering is preferred Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities during the application/hiring process. For more information about this role, please contact Qualcomm Careers.,

You will be responsible for developing a deeper understanding of standard bus protocols like AHB, AHB5, AXI4, ACE, CHI-B, C, D, E, etc. and develop SW Softmodel / RTL IPs / accelerated VIPs using C/C++/SystemVerilog/SystemC/UVM. You will make them perfect for Simulation (Questa) and Emulation (Platform), helping customers to deploy and use them in their Verification Environment. Job Requirements: BE/ME/BTech/MTech in Electronics/Electrical Engineering/Computer Engineering or related stream with 2+ years of relevant experience. Skills: - Strong knowledge of Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env. - Understanding of verification tools like Simulator, Synthesis, etc. - Hands-on experience on C/C++, System Verilog, UVM, SystemC, RTL. - Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB, etc. - Excellent written and verbal interpersonal skills. - Self-motivated and a great teammate.,

At Cadence, we are seeking individuals who are passionate about technology and aspire to make a difference in the industry. Join our esteemed North America hardware application engineering team and collaborate with top AEs, PEs, and R&D professionals in the EDA field. Cadence has been recognized as one of the World's Best Workplaces by Fortune magazine and Great Place to Work for eleven consecutive years, providing you with an opportunity to be part of a leading organization. As a member of the North America Verification Field Applications Engineering (FAE) Team, you will work closely with our R&D teams in India. Your primary responsibility will be to specialize in advanced virtual interface solutions including Accelerated Verification IPs and Virtual Bridges solutions for Cadence's hardware emulation and prototyping platforms. By engaging in key campaigns in North America, you will drive innovative HW emulation solutions for prominent semiconductor and system companies, serving as a crucial liaison between customers, North America AEs, and R&D teams. Key Responsibilities: - Take on a technical leadership role in virtual interface solutions for Palladium and Protium, becoming the expert resource for the North America field AE team. - Offer comprehensive technical support in collaboration with R&D to facilitate advanced emulation flows and secure design wins. - Advocate for customer requirements and collaborate closely with R&D in India to develop competitive technical solutions. Requirements: - Proficiency in hardware emulation with expertise in interface protocols such as PCIe, AMBA, and Ethernet. - Familiarity with synthesizable coding style and fundamental SoC architectures. - Knowledge of SystemVerilog, VHDL, Verilog, C/C++, and SystemC. - Ability to quickly assess emulation environments and design complexities. - Excellent verbal and written communication skills to effectively facilitate communication between external customers, NA FAE team, and internal R&D teams. - Strong teamwork capabilities. - Minimum 8 years of industry experience. Join us at Cadence and contribute to meaningful work that challenges the boundaries of technology. Be a part of our team to solve problems that others cannot.,

Qualcomm India Private Limited is seeking a Systems Engineer to be part of the Engineering Group, specifically in the Systems Engineering department. As a Systems Engineer at Qualcomm, you will engage in researching, designing, developing, simulating, and validating systems-level software, hardware, architecture, algorithms, and solutions. Your work will contribute towards the development of cutting-edge technology, enabling next-generation experiences and driving digital transformation. Collaboration across functional teams is essential to meet and exceed system-level requirements and standards. The ideal candidate should possess a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field with a minimum of 3 years of Systems Engineering experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with at least 1 year of experience in the same field would also be considered. The job overview includes working with Qualcomm's security architecture/IP and access control team on developing next-generation SOCs for various product categories such as smartphones, tablets, automotive, and IoT. Responsibilities involve assisting product development teams in applying secure hardware design principles at different levels, including individual blocks, computing cores, and SoCs. Experience in software/hardware co-design and familiarity with debug architectures like JTAG and ARM coresight are advantageous. Candidates should have 5 to 7+ years of industry or academic experience in Security, along with expertise in areas such as computer architecture, mobile platform security, ARM TrustZone, operating system security, programming languages like C/C++, Python, RTL, and teamwork across different teams and locations. Strong communication skills in English, both verbal and written, are essential. Preferred qualifications include skills/experience in ARM architecture SoC security design, applied cryptography, trusted computing, hardware firewalls for access control, knowledge in AI/ML, FPGA/ASIC design using SystemVerilog, VHDL, Verilog, SystemC, and familiarity with memory and storage technologies. Educational requirements include a Bachelor's degree or above in Computer Engineering and/or Electrical Engineering. Experience-wise, a Bachelor's or Master's degree with 5-7+ years of Systems Engineering experience is preferred. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities during the application/hiring process. They expect employees to adhere to all policies and procedures, including security measures for protecting confidential information. Staffing and recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes. For more information about this role, please contact Qualcomm Careers.,

Are you ready to take the next step in your career and contribute to cutting-edge ASIC and IP/SoC development We are looking for an experienced Design Engineer to join our team in Hyderabad. This is an exciting opportunity to work with a talented team on high-impact projects, pushing the boundaries of digital design in a collaborative and fast-paced environment. As a key technical contributor, you will work closely with ASIC engineering management to define and implement digital IP/SoC designs, and integrate these with third-party designs into customer ASICs and SoCs. You'll be part of a multi-site development team, ensuring the delivery of high-quality designs that meet customer requirements and solving complex technical challenges. Key Responsibilities: - Design & Implementation: Specify, micro-architect, implement, and perform design verification for complex RTL IP blocks, from basic SoC building blocks to advanced video processing and encoding/decoding logic. - IP Development Cycle: Take part in the full lifecycle of IP developmentfrom customer concept to backend layout and silicon validation. - Collaboration: Work closely with SoC architects to ensure designs align with project requirements and integrate seamlessly with the rest of the SoC. - Technical Guidance: Provide technical advice and solutions to design, verification, physical design, silicon validation, and production test teams. - Customer & Team Engagement: Analyse customer requirements and implement functional digital designs and integration flows for complex SoCs. Provide support for customer-facing technical discussions. - Tool & Script Development: Develop, maintain, and deploy proprietary scripts and tools for ASIC/SoC design and database management. Leverage industry-leading EDA tools for design quality assurance, power optimisation, and synthesis/timing analysis. - Continuous Learning: Stay up-to-date with the latest advances in engineering technologies and methodologies to maintain our competitive edge. - Mentorship: Coach junior engineers and support them in all aspects of design activities, including coding, synthesis, debug, DFT, and backend integration. - Technical Publications: Contribute to technical white papers, and provide sales support as part of a collaborative team. Key Relationships: Internal: Collaborate with Engineers, Senior Engineers, Principal Engineers, Project Managers, Sales, Finance, and HR teams. External: Technical communication with customers (minimal), and liaising with EDA Tool Vendors, Foundries, and Assembly Houses. What We're Looking For: Qualifications: Essential: - Degree/Masters or PhD in Electrical Engineering, Computer Science, or a related field. - Typically, 5+ years of relevant experience in digital design and IP/SoC development. Desirable: - A Masters or PhD in a related subject with practical experience of 5+ years. Skills & Experience: Essential: - Expertise in IP design, implementation, and verification. - Strong knowledge of RTL synthesis, performance, and power analysis. - In-depth understanding of digital design concepts and problem-solving capabilities. - Proficient in HDL coding (VHDL, Verilog, SystemVerilog). - System design knowledge, including clock domain management, reset schemes, and power management. - Experience with SoC level verification (HW/SW co-verification, multi-mode simulation, gate-level simulation). - Experience with design checking tools (Lint, CDC, LEC). - Strong communication skills and ability to provide technical guidance to junior engineers. Desirable: - Familiarity with ARM processor subsystems, video processing, bus protocols (AXI/AHB/ACE). - Experience with low power design methodology (UPF/CPF) and synthesis/timing analysis. - Experience with Tcl, Perl, Python, SystemC, IPXACT, and database management. - Familiarity with Linux software frameworks. Attributes: - Self-motivated with the ability to work independently and as part of a team. - Strong problem-solving skills and ability to adapt quickly to changing priorities. - Excellent attention to detail and time management skills. - A fast learner who thrives in a dynamic, collaborative environment.,

As a SystemC Architect, you will be responsible for architecting and developing high-performance SystemC/TLM 2.0 models for complex SoC systems. Your role will involve designing and implementing simulation models for embedded systems and hardware components, including CPUs, GPUs, accelerators, and memory subsystems. You will collaborate closely with cross-functional teams to define system architecture and interface requirements and lead performance optimization and validation efforts for virtual platforms. Additionally, you will mentor junior engineers and drive technical excellence within the team. To excel in this role, you must have expertise in SystemC and Transaction-Level Modeling (TLM 2.0) along with strong proficiency in C/C++ programming and a deep understanding of Object-Oriented Programming (OOP). Your hands-on experience in embedded software/firmware development and solid knowledge of SoC architecture, including CPU pipelines, GPUs, hardware accelerators, memory hierarchies, and bus protocols (AXI, PCIe, USB, etc.) will be crucial for success. Experience in peripheral modeling such as timers, DMA controllers, and I/O devices is also required. Good-to-have skills for this position include experience in developing Virtual Platforms (VPs) for semiconductor applications, familiarity with simulators like QEMU, Synopsys Virtualizer, or similar tools, exposure to hardware/software co-simulation environments, and an understanding of Verilog/SystemVerilog for analyzing and correlating with hardware designs. If you have 10+ years of experience, a strong foundation in embedded systems, and the required skill set, we encourage you to apply for this challenging and rewarding SystemC Architect role based in Bangalore.,