62 Systemc Jobs - Page 3

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of Processors or ASICs. Minimum 3+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug Formal verification experience

Description: We are looking for a highly skilled and motivated engineers to join the team that is modelling ARMs v9 architecture and the latest RISC-V cores from our customers in the RISC-V ecosystem You will create C software models of leading-edge CPU technologies that will power future systems in markets such as data centers, mobile communications, and Internet of Things (IoT), You will be joining an experienced multinational development team located in UK, Europe, or USA The team is responsible for building and supporting high speed simulation models of Arm and RISC-V processors and embedded systems These models are for use in IP design, verification, and software development, and are also delivered to our OEM and Silicon Partners The models are distributed with configuration and analysis tools, and can be integrated into standard SystemVerilog, C, C++, and SystemC environments, Job Purpose: As part of the modelling team, you will build highly efficient C models and platforms using the industry open standard OVP APIs, as well as working with other teams to design systems to allow our Imperas Fast Processor Models to be used within their workflows and platforms, Key objectives of this role include: To develop, test, and maintain high speed software models (ImperasFPMs) of advanced CPU and system level IP, To technically support other engineers, To be responsible for producing and executing model development plans for your area of responsibility, in conjunction with project management and engineering peers, To build Virtual Platforms that can be used for early software development, To support internal and external users of these CPU models, We offer an international work environment that is characterized by flexibility, an informal atmosphere, a fast pace and an opportunity to impact the way the industry develops new systems and embedded software You will work with highly professional and motivated colleagues who value and support your contribution Synopsys is a dynamic international workplace with opportunities for personal and professional growth The position carries an attractive compensation and benefits package commensurate with a competitive global company, Technical attributes: Mandatory: Bachelors/Masters in ECE/CS with 5+ years of experience Excellent in C/C++ Knowledge of Processor architectures Arm, RISC-V etc Knowledge of Hardware and Software Interfacing Excellent in problem solving and analytical skills, Excellent communication, team work and networking skills Preferred: Knowledge of SystemC, TLM and experience creating system level models Knowledge of Embedded Software Understanding of Peripheral model internals or Interconnects like AXI / AHB Experience with EDA Tools

Looking for Siemens EDA ambassadors: Lead Member Technical Staff The electronics industry is evolving at an ever-accelerating pace. At Siemens EDA, we are dedicated to empowering customers to bring life-changing innovations to market faster and achieve leadership in their industries. We achieve this by providing the most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services worldwide . Key Responsibilities: In this role, you will be at the forefront of designing, developing, and implementing software solutions for both internal and external products, ensuring that we consistently exceed customer expectations and uphold the highest quality standards. You will be pivotal in ensuring the functional excellence of released products across multiple platforms, tackling complex challenges head-on. Moreover, youll be responsible for creating and implementing software designs that often span multiple product areas, collaborating seamlessly with multi-functional teams to drive efficiency, optimize performance, and elevate our solutions! Job Qualifications: We bring together a dynamic team of individuals with a B.E./B.Tech./M.Tech. in Computer Science, Electrical Engineering, Electronics & Communication, Instrumentation & Control, or related fields. Do you have 3-5 years of experience in software development, specifically specializing in FPGA synthesis solutions?W We possess a strong understanding of digital design fundamentals and are proficient in C/C++ and Object-Oriented Programming (OOP). Our team excels in algorithm analysis, development, and optimization of data structures, and we continuously strive for excellence through open and constructive feedback! Good to Have: Familiarity with synthesis, simulation, and verification methodologies is a definite plus. A basic understanding of at least one Hardware Description Language (HDL) such as Verilog, SystemVerilog, VHDL, or SystemC is highly advantageous.

Responsibilities for this role include: Develop functionally accurate SystemC/TLM software models for CPUs (ARM and RISC-V architectures) and other Hardware devices that can be used to compose Virtual Platforms. Verify the models functionality versus behavior model and/or RTL using SystemC and/or UVM/SystemVerilog and apply unit testing/debug and implement the test plan. Build Virtual Platform for Hardware designs on the System Level. Load/Boot Linux/Mentor Embedded Linux (MEL)/ Android on the Virtual Platform. Simulate and Debug Customers Software on the Virtual Platform Write professional Functional Specs and Design Documents. We dont need hard workers, just super minds! Bachelor, Master, or Ph.D. degree or equivalent experience in Computer or Electrical Engineering with minimum 2-8 years of experience and Very Good with honors degree. Strong experience in C/C++ Programming and in Embedded Linux Development. We need someone with the basic knowledge of digital circuits and digital design/systems and having good background in programming using SystemC is a plus. We are looking for someone who has good experience in using Linux/Unix OS and experience in scripting/scripting languages such as Make/Tcl/Perl. Position requires well developed written and oral communication skills. Also, being able to work with tight deadlines and meet schedules.

Looking for Siemens EDA ambassadorsLead Member Technical Staff The electronics industry is evolving at an ever-accelerating pace. At Siemens EDA, we are dedicated to empowering customers to bring life-changing innovations to market faster and achieve leadership in their industries. We achieve this by providing the most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services worldwide. Key Responsibilities In this role, you will be at the forefront of designing, developing, and implementing software solutions for both internal and external products, ensuring that we consistently exceed customer expectations and uphold the highest quality standards. You will be pivotal in ensuring the functional excellence of released products across multiple platforms, tackling complex challenges head-on. Moreover, you"™ll be responsible for creating and implementing software designs that often span multiple product areas, collaborating seamlessly with multi-functional teams to drive efficiency, optimize performance, and elevate our solutions! Job Qualifications We bring together a dynamic team of individuals with a B.E./B.Tech./M.Tech. in Computer Science, Electrical Engineering, Electronics & Communication, Instrumentation & Control, or related fields. Do you have 2-5 years of experience in software development, specifically specializing in FPGA synthesis solutions?W We possess a strong understanding of digital design fundamentals and are proficient in C/C++ and Object-Oriented Programming (OOP). Our team excels in algorithm analysis, development, and optimization of data structures, and we continuously strive for excellence through open and constructive feedback! Good to Have Familiarity with synthesis, simulation, and verification methodologies is a definite plus. A basic understanding of at least one Hardware Description Language (HDL) such as Verilog, SystemVerilog, VHDL, or SystemC is highly advantageous. We"™ve got quite a lot to offer. How about you? This role is based in Noida, where you"™ll have the opportunity to work with diverse teams shaping the future, driving innovation, and providing state-of-the-art solutions. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare. Transform everyday

Project Role : Performance Engineer Project Role Description : Diagnose issues that an in-house performance testing team has been unable to. There are five aspects to Performance Engineering:software development lifecycle and architecture, performance testing and validation, capacity planning, application performance management and problem detection and resolution. Must have skills : Vmware Virtualization Administration Good to have skills : Nutanix Administration Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Performance Engineer, you will engage in diagnosing complex issues that the in-house performance testing team has been unable to resolve. Your typical day will involve collaborating with various teams to analyze performance metrics, conducting thorough assessments of application performance, and implementing strategies to enhance system efficiency. You will also be responsible for validating performance testing results and ensuring that applications meet the required performance standards, contributing to the overall success of the software development lifecycle and architecture. Roles & Responsibilities: Expected to be an SME. Collaborate and manage the team to perform. Responsible for team decisions. Engage with multiple teams and contribute on key decisions. Provide solutions to problems for their immediate team and across multiple teams. Conduct performance assessments and recommend improvements based on findings. Facilitate knowledge sharing sessions to enhance team capabilities. Deploy, maintain, and operate the virtualization infrastructure in strict adherence with the defined procedures with the aim of highest operational stability. Execute, maintain and improve the operational processes and activities, deliver according to the highest quality and standards, ensuring high service delivery levels, compliance and customer satisfaction. Conduct incident investigation, communication and resolution. Perform out of business hours support activities and participate to on-call rotation. Create, maintain and report KPIs. Support internal and external audits activities, as well as resolution of findings. Strictly adhere to corporate processes, standards, policies and operational procedures. Investigate and implement operations automation where relevant. Professional & Technical Skills: Must To Have Skills: Proficiency in VMware Virtualization Administration. Good To Have Skills: Experience with Nutanix Administration. Strong understanding of performance testing methodologies and tools. Experience in capacity planning and application performance management. Proficient in problem detection and resolution techniques. Excellent knowledge of the following solutions and technologies:RHEL, VMware ESX in a stretched cluster deployment, VMware VCF, disk storage replication, Python, Ansible, Terraform, Jira. Knowledge of alternative hypervisor solutions such as Nutanix or Huawei DCS is a plus. Very strong customer-oriented mindset and attitude, experience in interacting with both internal and external customers. Previous experience (5 years) in a similar role operating a highly critical virtualization infrastructure within a financial environment. Additional Information: The candidate should have minimum 7-10 years of experience in VMware Virtualization Administration. This position is based at our Hyderabad office. A 15 years full time education is required. Qualification 15 years full time education

Project Role : Performance Engineer Project Role Description : Diagnose issues that an in-house performance testing team has been unable to. There are five aspects to Performance Engineering:software development lifecycle and architecture, performance testing and validation, capacity planning, application performance management and problem detection and resolution. Must have skills : Vmware Virtualization Administration Good to have skills : NA Minimum 12 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Performance Engineer, you will engage in diagnosing complex issues that the in-house performance testing team has been unable to resolve. Your typical day will involve collaborating with various teams to analyze performance metrics, conducting thorough assessments of application performance, and implementing strategies to enhance system efficiency. You will also be responsible for validating performance testing results and ensuring that applications meet the required performance standards, contributing to the overall success of the software development lifecycle and architecture. Roles & Responsibilities: Expected to be an SME. Collaborate and manage the team to perform. Responsible for team decisions. Engage with multiple teams and contribute on key decisions. Provide solutions to problems for their immediate team and across multiple teams. Conduct performance assessments and recommend improvements based on findings. Facilitate knowledge sharing sessions to enhance team capabilities. Deploy, maintain, and operate the virtualization infrastructure in strict adherence with the defined procedures with the aim of highest operational stability. Execute, maintain and improve the operational processes and activities, deliver according to the highest quality and standards, ensuring high service delivery levels, compliance and customer satisfaction. Conduct incident investigation, communication and resolution. Perform out of business hours support activities and participate to on-call rotation. Create, maintain and report KPIs. Support internal and external audits activities, as well as resolution of findings. Strictly adhere to corporate processes, standards, policies and operational procedures. Investigate and implement operations automation where relevant. Professional & Technical Skills: Must To Have Skills: Proficiency in VMware Virtualization Administration. Good To Have Skills: Experience with Nutanix Administration. Strong understanding of performance testing methodologies and tools. Experience in capacity planning and application performance management. Proficient in problem detection and resolution techniques. Excellent knowledge of the following solutions and technologies:RHEL, VMware ESX in a stretched cluster deployment, VMware VCF, disk storage replication, Python, Ansible, Terraform, Jira. Knowledge of alternative hypervisor solutions such as Nutanix or Huawei DCS is a plus. Very strong customer-oriented mindset and attitude, experience in interacting with both internal and external customers. Previous experience (5 years) in a similar role operating a highly critical virtualization infrastructure within a financial environment. Additional Information: The candidate should have minimum 7-10 years of experience in VMware Virtualization Administration. This position is based at our Hyderabad office. A 15 years full time education is required. Qualification 15 years full time education

AMD is looking for a talented, self-driven and motivated engineer to technically lead AIG s Simulation Modeling projects working on AMD s XDNA (AI Engine) architecture and the Vitis AI family of software tools. The XDNA is an industry leading architecture in terms of performance per watt and is used in AMD s client and embedded devices as the primary engine for Machine Learning workloads. It is the hardware engine behind Windows Co-pilot on AMD devices. The team provides a fast-paced environment offering each of its members immense opportunity to interact with a wide variety of people including from other organizations like hardware designers, marketing, support, and even direct customer interaction, and truly learn and grow their skills and capabilities. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated technical issues to resolution. They should have demonstrated ability to identify technical problems, explore and propose viable options, and apply technical solutions. They should be able to excel in a global team environment with strong verbal and written communication skills. . KEY RESPONSIBILITIES: Vitis AI is AMD s primary SDK that enables users to compile and run their ML models on the XDNA architecture. As a senior member of this high-performance team, the selected candidate will have responsibility to model the XDNA architecture in terms of functionality, accuracy and simulation speed. Candidate will work with compiler, runtime/driver teams to bring up latest AI models like CNNs, Transformers, StableDiffiusion, NLPs etc. on the XDNA simulator. This is a crucial part of AMD s shift-left strategy for the successful bring up of new devices and day 0 enablement of models. Candidates would develop a deeper understanding of the various ML models, and how they are executed, identify performance bottlenecks and enable faster development. PREFERRED EXPERIENCE: Minimum 10 years of relevant work experience. Strong background in C++ based development and debug, dealing with multi-threaded infrastructure and performance optimization Experience in creating cycle accurate modeling of IPs in C++ or SystemC / TLM. Understanding of SoCs, and bringing up of software stack from driver to application on simulation model. Understanding hardware metrics like latency/throughput on any sub-system, and what changes impact those metrics. Experience in software development environment on both Linux and Windows is required. Experience in technologies like Virtual Platforms, SystemC/QEMU models, Emulation platforms, Hw/Sw co-design, and Performance analysis is desired. Familiarity with hardware languages like VHDL, Verilog and System Verilog for simulation using tools like Modelsim, VCS, Questa Sim is highly desired. ACADEMIC CREDENTIALS: Bachelor s or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: QCT's Bangalore Wireless R&D HW team is looking out for experienced Wireless Modem HW model developers to work on Qualcomm"™s best in class chipsets in modem WWAN IPs Roles and Responsibilities You will be contributing to flagship modem core IP development covering 5G(NR) & 4G (LTE) technologies. You will be part of team defining and developing next generation multi-mode 5G modems. You will be working on development and verification of HW models of modem core IP. The models are developed on C++/SystemC platform and used as golden reference for RTL verification and pre Silicon FW development ( virtual prototyping). The candidate must be well versed with C++ and should have good exposure to SystemC and/or System Verilog and/or Matlab. The candidate must have ability to understand HW micro-architecture & its modeling abstraction. Working knowledge of physical layer of wireless technologies like NR,LTE , WLAN, Bluetooth is highly desired. Expertise on digital signal processing and working experience on HW modeling and/or RTL design/ verification of IP are preferred. Candidates with SW/FW background on wireless IP can also apply. Candidates with strong technical knowhow on non-wireless DSP based HW IPs ( with Design / Verification/ Modeling skills) will also be considered. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Skillset/Experience: 5-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug "” 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.