Meta is hiring talented individuals to join our Infrastructure organization as ASIC Frontend Implementation Engineers (RDC/CDC). In this role, you will play a critical part in designing and developing efficient System on Chip (SoC) and IP for data center applications. As an ASIC Frontend Implementation Engineer, your primary focus will be on the front-end implementation process and static verification tools, transforming RTL designs into optimized netlists. You will utilize your expertise in RTL Lint, CDC analysis, timing constraints, and synthesis to ensure seamless integration of various components to build efficient System on Chip (SoC) and IP for data center applications.By joining our team, you'll have the opportunity to contribute to the development of cutting-edge technology that powers Meta's infrastructure.
- Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC
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Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC
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Perform RTL Lint and work with the Designers to create waivers
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Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults
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Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power
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Developing Automation scripts and Methodology for all Front End (FE)-tools including (Lint, CDC, RDC,)
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Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback
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Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
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2+ years of experience in static verification tools
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Experience with Lint, Clock Domain & Reset Domain crossing
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Knowledge of SOC Integration (Clocking, Reset, PLL, etc)
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Knowledge of front-end ASIC flows
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Experience with RTL design using SystemVerilog or other HDL
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Successful candidates must remain in role in the same team in India for a minimum period of 24 months before being eligible for transfer to another role, team or location
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Scripting and programming experience using Perl/Python, TCL, and Make
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Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools
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Experience with SOC Design Integration and Front-End Implementation
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Experience with developing structural rule based checks for RTL & Netlist
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Experience with Netlist-CDC Analysis and improving MTBF
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Knowledge of Timing/physical libraries, SRAM Memories
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
