2300 Verilog Jobs - Page 13

We are looking for experienced FPGA Verification Engineer. As a FPGA Verification Engineer, you will work for a high complexity DWDM equipment for LH/ULH applications. You will work in close collaboration with multi location cross-functional R & D teams. Our work includes everything from product concept to finished product - a process that spans over the entire development cycle. The team takes full responsibility for delivery on time with the right quality. As an FPGA Verification engineer, you will be responsible for designing verification plan, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and strong will to drive for solutions. Education Necessary: Candidates must have a bachelors degree or higher in EE with very good academics. Roles & Responsibilities: Must have 10 years of experience in developing System Verilog UVM based test environments, developing and implementing test plans at block, sub-chip and chip levels. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools. Exposure to UVM (or similar) verification methodologies is required. Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred. Should be conversant with technologies like, Ethernet, PCIe etc. Knowledge of telecom protocol is preferred. Structured and thorough with analytical and troubleshooting skills. Good written and oral communication skills are required. Flexible, innovative, self-driven and willing to take own initiatives. Highly motivated team player. We offer: A high pace in development of new products. Tight cooperation with other disciplines. Short product development cycles, Real results of your work, you will see how it affects our products and sales. International possibilities of development and internal advancement. Social and wellness activities and clubs. A friendly and helpful atmosphere. Highly competent and motivated colleagues.

About The Role JD Must have skills. Payment Domain Expertise, MUST - Knowledge on MT and MX Message, Basics of SQL, and Java Specific skillset on MTS and UPF knowledge. Payment domain expertise, knowledge on MT and MX messages Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. - Grade Specific JD Must have skills. Payment Domain Expertise, MUST - Knowledge on MT and MX Message, Basics of SQL, and Java Specific skillset on MTS and UPF knowledge. Payment domain expertise, knowledge on MT and MX messages Skills (competencies) Verbal Communication

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications. What You Can Expect In this role based in Hyderabad - India, you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. You will be responsible for maintaining, enhancing, and supporting Marvell's Place and Route Flow, leveraging industry-standard EDA tools. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What We're Looking For Completed a Bachelor’s Degree in Electronics/Electrical Engineering or related fields and have 4-8 years of related professional experience OR a Master’s degree and/or PhD in Electronics/Electrical Engineering or related fields. In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis. Good understanding of standard Synthesis to GDS flows and methodology. Good scripting skills in languages such as Perl, tcl, and Python. Good understanding of digital logic and computer architecture. Hands-on experience in advanced technology nodes upto 2nm. Strong hands-on experience in blocks/subsystem P&R implementation using Cadence Innovus and Synopsys FC. Strong experience in block level signoff power, timing, PV closure & debugging skills. Good top level and full-chip experience is an added advantage Knowledge of Verilog/VHDL. Good communication skills and self-discipline contributing in a team environment. Ability to independently drive subsystems/IPs P&R and signoff closure working with global teams. Ability to mentor juniors and be involved in team development activities. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills Do you have a passion for invention and self-challenge? This position gives you an opportunity to learn and participate in one of the most cutting-edge projects that Lattice’s Silicon Engineering team has embarked upon to date. We are validating building blocks in FPGA on board level to ensure functionality and performance aspect of Design intent. FPGA consists of various IPs as a building block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc. As a Silicon Design Validation engineer, you will have an opportunity to learn and train yourself on how to validate one/or many of the building blocks within the FPGA. And also, you will be able to acquire knowledge on process/methodology required for validating certain IPs from planning to completion. While you are working on those, you will be exposed to cutting edge equipment and advanced boards as well as Various SW/tools/scripts. What you’re going to be exposed to and learn: The Ideal Candidate Is Highly Motivated In Developing a Career In Silicon Design Validation Engineering. You Will Get Significant Exposure And Training In The Following Areas Chance to learn FPGA and it’s build block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, MIPI, Fabric, I/O etc but not limited. Validate and characterize various IPs from silicon arrival to release to production. Develop validation and characterization plans for certain IP, bench hardware and software. Develop test logic RTL to achieve intended validation/characterization test. Drive new silicon product bring-up, validation, debug to asses IP functionality/performance. Characterizing data sheet parameters. Analyzing the measured data with statistical view. Data sheet preparation etc. Serve as the central resource with design, verification, manufacturing, test, quality and marketing/apps as the product(s) move Silicon arrival to product release. Supporting customer issues as required to resolve issues found after product release You Have… 5+ years of experience Electrical Engineering degree with a strong desire to pursue an engineering career in Silicon Design Validation Expertise in High Speed Serdes Interface characterization and protocol compliance testing such as PCIe/Ethernet/SDI/CoaXpress/JESD204, MIPI D-PHY, MIPI CSI/DSI-2, USB and DisplayPort/HDMI etc. Expertise in high speed board design and signal integrity evaluation/debug. Expertise in Verilog/VHDL and design implementation using FPGA development tools. Expertise in test automation development using programming languages such as Python, Perl. Knowledge of statistical analysis concepts and use of analysis tools such as JMP, R. Proficiency with bench equipment for device characterization such as BERT, VNA, Oscilloscopes, Protocol Exerciser/Analyzers. Exposure on FPGA(emulation/prototyping etc) Strong written and verbal communication skills to work with cross-functional team Self-motivated and proactive with critical thinking. Good problem solving and debugging skills.

Category Engineering Hire Type Employee Job ID 12162 Remote Eligible No Date Posted 20/07/2025 Alternate Job Titles: ASIC Verification, Sr. Engineer Sr. Engineer, Digital Verification We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and innovative engineer with a strong background in high-speed protocols and a keen interest in growing your expertise through verification-related work. You thrive in a collaborative environment, working alongside experienced digital design and verification professionals. With a solid foundation in Verilog, VHDL, and/or SystemVerilog, you are eager to expand your knowledge and your skills to state-of-the-art products. Your excellent problem-solving abilities and strong communication skills enable you to identify and address design issues effectively. You are organized, detail-oriented, and capable of managing multiple tasks efficiently. With your passion for learning and exploring new technologies, you are committed to contributing to the success of our projects and the broader goals of Synopsys. What You’ll Be Doing: Identify verification environment requirements from various sources, including specifications, design functionality, and interfaces. Generate verification test plans, environment documentation, and usage documentation. Define, develop, and verify complex UVM verification environments. Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics. Identify design problems, propose corrective actions, and address inconsistencies in documented functionality. Collaborate with cross-functional teams to ensure the successful integration and verification of projects. The Impact You Will Have: Ensure the robustness and reliability of our digital designs through meticulous verification processes. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enhance the overall quality and performance of our silicon IP products. Help our customers bring differentiated products to market quickly and with reduced risk. Drive continuous improvements in our verification methodologies and practices. Support the growth and success of Synopsys by contributing to our reputation for innovation and excellence. What You’ll Need: Proven desire to learn and explore new state-of-the-art technologies. Demonstrated proficiency in Verilog, VHDL, and/or SystemVerilog. Experience with scripting languages such as BASH, TCSH, PERL, PYTHON, or TCL is a plus. Understanding of verification methodologies such as UVM is a plus. Strong organizational and communication skills. 3+ years of relevant experience in ASIC digital verification. Who You Are: A passionate and innovative engineer with a strong technical background. Detail-oriented and capable of managing multiple tasks efficiently. Excellent problem-solving abilities and a proactive approach to addressing challenges. Strong communication skills, both written and spoken. A collaborative team player who thrives in a dynamic and fast-paced environment. The Team You’ll Be A Part Of: You will join an experienced and dedicated digital design and verification team focused on developing state-of-the-art products. Our team is committed to excellence and continuous improvement, working collaboratively to achieve our goals. You will have the opportunity to learn from experts in various fields and contribute to the success of our projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Introduction IBM Infrastructure division builds Servers, Storage, Systems and Cloud Software which are the building blocks for next-generation IT infrastructure of enterprise customers and data centers. IBM Servers provide best-in-class reliability, scalability, performance, and end-to-end security to handle mission-critical workloads and provide seamless extension to hybrid multicloud environments. India Systems Development Lab (ISDL) is part of word-wide IBM Infrastructure division. Established in 1996, the ISDL Lab is headquartered in Bengaluru, with presence in Pune and Hyderabad as well. ISDL teams work across the IBM Systems stack including Processor development (Power and IBM Z), ASCIs, Firmware, Operating Systems, Systems Software, Storage Software, Cloud Software, Performance & Security Engineering, System Test etc. The lab also focuses on innovations, thanks to the creative energies of the teams. The lab has contributed over 400+ patents in cutting edge technologies and inventions so far. ISDL teams also ushered in new development models such as Agile, Design Thinking and DevOps. Your Role And Responsibilities As a Software Engineer at IBM India Systems Development Lab (IBM ISDL), you will get an opportunity to work on all the phases of product development (Design/Development, Test and Support) across core Systems technologies including Operating Systems, Firmware, Systems Software, Storage Software & Cloud Software. As a Software Developer At ISDL: You will be focused on development of IBM Systems products interfacing with development & product management teams and end users, cutting across geos. You would analyze product requirements, determine the best course of design, implement/code the solution and test across the entire product development life cycle. One could also work on Validation and Support of IBM Systems products. You get to work with a vibrant, culture driven and technically accomplished teams working to create world-class products and deployment environments, delivering an industry leading user experience for our customers. You will be valued for your contributions in a growing organization with broader opportunities. At ISDL, work is more than a job - it's a calling: To build. To design. To code. To invent. To collaborate. To think along with clients. To make new products/markets. Not just to do something better, but to attempt things you've never thought was possible. Are you ready to lead in this new era of technology and solve some of the most challenging problems in Systems Software technologies? If so, let’s talk. Required Technical And Professional Expertise Required Technical Expertise: Knowledge of Operating Systems, OpenStack, Kubernetes, Container technologies, Cloud concepts, Security, Virtualization Management, REST API, DevOps (Continuous Integration) and Microservice Architecture. Strong programming skills in C, C++, Go Lang, Python, Ansible, Shell Scripting. Comfortable in working with Github and leveraging Open source tools. AI Software Engineer: As a Software Engineer with IBM AI on Z Solutions teams, you will get the opportunity to get involved in delivering best-in class Enterprise AI Solutions on IBM Z and support IBM Customers while adopting AI technologies / Solutions into their businesses by building ethical, secure, trustworthy and sustainable AI solutions on IBM Z. You will be part of end to end solutions working along with technically accomplished teams. You will be working as a Full stack developer starting from understanding client challenges to providing solutions using AI. Required Technical Expertise: Knowledge of AI/ML/DL, Jupyter Notebooks, Linux Systems, Kubernetes, Container technologies, REST API, UI skills, Strong programming skills like – C, C++, R, Python, Go Lang and well versed with Linux platform. Strong understanding of Data Science, modern tools and techniques to derive meaningful insights Understanding of Machine learning (ML) frameworks like scikit- learn, XGBoost etc. Understanding of Deep Learning (DL) Frameworks like Tensorflow, PyTorch Understanding of Deep Learning Compilers (DLC) Natural Language Processing (NLP) skills Understanding of different CPU architectures (little endian, big endian). Familiar with open source databases PostGreSQL, MongoDB, CouchDB, CockroachDB, Redis, data sources, connectors, data preparations, data flows, Integrate, cleanse and shape data. IBM Storage Engineer: As a Storage Engineer Intern in a Storage Development Lab you would support the design, testing, and validation of storage solutions used in enterprise or consumer products. This role involves working closely with hardware and software development teams to evaluate storage performance, ensure data integrity, and assist in building prototypes and test environments. The engineer contributes to the development lifecycle by configuring storage systems, automating test setups, and analyzing system behavior under various workloads. This position is ideal for individuals with a foundational understanding of storage technologies and a passion for hands-on experimentation and product innovation. Preferred Technical Expertise: Practical working experience with Java, Python, GoLang, ReactJS, Knowledge of AI/ML/DL, Jupyter Notebooks, Storage Systems, Kubernetes, Container technologies, REST API, UI skills, Exposure to cloud computing technologies such as Red Hat OpenShift, Microservices Architecture, Kubernetes/Docker Deployment. Basic understanding of storage technologies: SAN, NAS, DAS Familiarity with RAID levels and disk configurations Knowledge of file systems (e.g., NTFS, ext4, ZFS) Experience with operating systems: Windows Server, Linux/Unix Basic networking concepts: TCP/IP, DNS, DHCP Scripting skills: Bash, PowerShell, or Python (for automation) Understanding of backup and recovery tools (e.g., Veeam, Commvault) Exposure to cloud storage: AWS S3, Azure Blob, or Google Cloud Storage Linux Developer: As a Linux developer, you would be involved in design and development of advanced features in the Linux OS for the next generation server platforms from IBM by collaboration with the Linux community. You collaborate with teams across the hardware, firmware, and upstream Linux kernel community to deliver these capabilities. Preferred Technical Expertise Excellent knowledge of the C programming language Knowledge of Linux Kernel internals and implementation principles. In-depth understanding of operating systems concepts, data structures, processor architecture, and virtualization Experience with working on open-source software using tools such git and associated community participation processes. Hardware Management Console (HMC) / Novalink Software Developer: As a Software Developer in HMC / Novalink team, you will work on design, development, and test of the Management Console for IBM Power Servers. You will be involved in user centric Graphical User Interface development and Backend for server and virtualization management solution development in Agile environment. Preferred Technical Expertise Strong Programming skills in in Core Java 8, C/C++ Web development skills in JavaScript (Frameworks such as Angular.js, React.js etc),, HTML, CSS and related technologies Experience in developing rich HTML applications Web UI Frameworks: Vaadin, React JS and UI styling libraries like Bootstrap/Material Knowledge of J2EE, JSP, RESTful web services and GraphQL API AIX Developer: AIX is a proprietary Unix operating system which runs on IBM Power Servers. It’s a secure, scalable, and robust open standards-based UNIX operating system which is designed to meet the needs of Enterprises class infrastructure. As an AIX developer, you would be involved in development, test or support of AIX OS features development or open source software porting/development for AIX OS Preferred Technical Expertise Strong Expertise in Systems Programming Skills (C, C++) Strong knowledge of operating systems concepts, data structures, algorithms Strong knowledge of Unix/Linux internals (Signals, IPC, Shared Memory,..etc) Expertise in developing/handling multi-threaded Applications. Good knowledge in any of the following areas User Space Applications File Systems, Volume Management Device Drivers Unix Networking, Security Container Technologies Linkers/Loaders Virtualization High Availability & clustering products Strong debugging and Problem-Solving skills Performance Engineer: As a performance Engineer , you will get an opportunity to conduct experiments and analysis to identify performance aspects for operating systems and Enterprise Servers. where you will be responsible for advancing the product roadmap by using your expertise in Linux operating system, building kernel , applying patches, performance characterization, optimization and hardware architecture to analyse performance of software/hardware combinations. You will be involved in conducting experiments and analysis to identify performance challenges and uncover optimization opportunities for IBM Power virtualization and cloud management software built on Open stack. The areas of work will be on characterization, analysis and fine-tune application software to help deliver optimal performance on IBM Power. Preferred Technical Expertise Experience in C/C++ programming Knowledge of Hypervisor, Virtualization concepts Good understanding of system HW , Operating System , Systems Architecture Strong skills in scripting Good problem solving, strong analytical and logical reasoning skills Familiar with server performance management and capacity planning Familiar with performance diagnostic methods and techniques Firmware Engineer: As a Firmware developer you will be responsible for designing and developing components and features independently in IBM India Systems Development Lab. ISDL works on end-to-end design, development across Power, Z and Storage portfolio. You would be a part of WW Firmware development organization and would be involved in designing & developing cutting edge features on the open source OpenBMC stack (https://github.com/openbmc/) and developing the open source embedded firmware code for bringing up the next generation enterprise Power, Z and LinuxONE Servers. You will get an opportunity work alongside with some of the best minds in the industry, forum and communities in the process of contributing to the portfolio. Preferred Technical Expertise Strong System Architecture knowledge Hands on programming skills with C, C++ , C on Linux Distros. Experience/exposure in Firmware/Embedded software design & development, Strong knowledge of Linux OS and Open Source development Experience with Open Source tools & scripting languages: Git, Gerrit, Jenkins, perl/python Other Skills (Common For All The Positions): Strong Communication, analytical, interpersonal & problem solving skills Ability to deliver on agreed goals and the ability to coordinate activities in the team/collaborate with others to deliver on the team vision. Ability to work effectively in a global team environment Enterprise System Design Software Engineer: The Enterprise Systems Design team is keen on hiring passionate Computer science and engineering graduates / Masters students, who can blend their architectural knowledge and programming skills to build the complex infrastructure geared to work for the Hybrid cloud and AI workloads. We have several opportunities in following areas of System & chip development team : Processor verification engineer Needs to develop the test infrastructure to verify the architecture and functionality of the IBM server processors/SOC or ASICs. Will be responsible to creatively think of all the scenarios to test and report the coverage. Work with design as well as other key stakeholders in identifying /debugging & Resolving logic design issues and deliver a quality design Processor Pre / Post silicon validation engineer As a validation engineer you would design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. Electronic design automation – Front & BE tool development. EDA tools development team is responsible for developing state of the art Front End verification , simulation , Formal verification tools , Place & Route, synthesis tools and Flows critical for designing & verifying high performance hardware design for IBM's next generation Systems (IBM P and Z Systems) which is used in Cognitive, ML, DL, and Data Center applications. Required Professional And Technical Skills: Functional Verification / Validation of Processors or ASICs. Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Strong C/C++programming skills in a Unix/Linux environment required Great scripting skills – Perl / Python/Shell Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow. Understand Verilog / VHDL , verification coverage closure Proven problem-solving skills and the ability to work in a team environment are a must

Lead Verification Engineer Experience: 7+ years Location: Hyderabad Job Description: Work as a member of a geographically distributed verification team to verify next-generation ASIC and FPGAs Develop testplans, implement testbenches, create testcases, and ensure functional coverage closure Handle regression testing and contribute to verification infrastructure development Develop both directed and random verification tests Debug test failures, identify root causes, and work with RTL and firmware engineers to resolve design defects and test issues Review functional and code coverage metrics, modify or add tests or constrain random tests to meet coverage requirement Collaborate with design, software and architecture teams to verify design under test Preferred Experience: Proficient in IP-level FPGA and ASIC verification Knowledge of PCIe, CXL or other IO protocol is preferred Proficient in Verilog/SystemVerilog, and scripting languages such as Perl or Python Hands-on experience with SystemVerilog and UVM is mandatory Experience in developing UVM-based verification testbenches, processes, and flows Solid understanding of design flow, verification methodology, and general computational logic design and verification About Company ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.

Introduction IBM Infrastructure division builds Servers, Storage, Systems and Cloud Software which are the building blocks for next-generation IT infrastructure of enterprise customers and data centers. IBM Servers provide best-in-class reliability, scalability, performance, and end-to-end security to handle mission-critical workloads and provide seamless extension to hybrid multicloud environments. India Systems Development Lab (ISDL) is part of word-wide IBM Infrastructure division. Established in 1996, the ISDL Lab is headquartered in Bengaluru, with presence in Pune and Hyderabad as well. ISDL teams work across the IBM Systems stack including Processor development (Power and IBM Z), ASCIs, Firmware, Operating Systems, Systems Software, Storage Software, Cloud Software, Performance & Security Engineering, System Test etc. The lab also focuses on innovations, thanks to the creative energies of the teams. The lab has contributed over 400+ patents in cutting edge technologies and inventions so far. ISDL teams also ushered in new development models such as Agile, Design Thinking and DevOps. Your Role And Responsibilities As a Software Engineer at IBM India Systems Development Lab (IBM ISDL), you will get an opportunity to work on all the phases of product development (Design/Development, Test and Support) across core Systems technologies including Operating Systems, Firmware, Systems Software, Storage Software & Cloud Software. As a Software Developer At ISDL: You will be focused on development of IBM Systems products interfacing with development & product management teams and end users, cutting across geos. You would analyze product requirements, determine the best course of design, implement/code the solution and test across the entire product development life cycle. One could also work on Validation and Support of IBM Systems products. You get to work with a vibrant, culture driven and technically accomplished teams working to create world-class products and deployment environments, delivering an industry leading user experience for our customers. You will be valued for your contributions in a growing organization with broader opportunities. At ISDL, work is more than a job - it's a calling: To build. To design. To code. To invent. To collaborate. To think along with clients. To make new products/markets. Not just to do something better, but to attempt things you've never thought was possible. Are you ready to lead in this new era of technology and solve some of the most challenging problems in Systems Software technologies? If so, let’s talk. Required Technical And Professional Expertise Required Technical Expertise: Knowledge of Operating Systems, OpenStack, Kubernetes, Container technologies, Cloud concepts, Security, Virtualization Management, REST API, DevOps (Continuous Integration) and Microservice Architecture. Strong programming skills in C, C++, Go Lang, Python, Ansible, Shell Scripting. Comfortable in working with Github and leveraging Open source tools. AI Software Engineer: As a Software Engineer with IBM AI on Z Solutions teams, you will get the opportunity to get involved in delivering best-in class Enterprise AI Solutions on IBM Z and support IBM Customers while adopting AI technologies / Solutions into their businesses by building ethical, secure, trustworthy and sustainable AI solutions on IBM Z. You will be part of end to end solutions working along with technically accomplished teams. You will be working as a Full stack developer starting from understanding client challenges to providing solutions using AI. Required Technical Expertise: Knowledge of AI/ML/DL, Jupyter Notebooks, Linux Systems, Kubernetes, Container technologies, REST API, UI skills, Strong programming skills like – C, C++, R, Python, Go Lang and well versed with Linux platform. Strong understanding of Data Science, modern tools and techniques to derive meaningful insights Understanding of Machine learning (ML) frameworks like scikit- learn, XGBoost etc. Understanding of Deep Learning (DL) Frameworks like Tensorflow, PyTorch Understanding of Deep Learning Compilers (DLC) Natural Language Processing (NLP) skills Understanding of different CPU architectures (little endian, big endian). Familiar with open source databases PostGreSQL, MongoDB, CouchDB, CockroachDB, Redis, data sources, connectors, data preparations, data flows, Integrate, cleanse and shape data. IBM Storage Engineer: As a Storage Engineer Intern in a Storage Development Lab you would support the design, testing, and validation of storage solutions used in enterprise or consumer products. This role involves working closely with hardware and software development teams to evaluate storage performance, ensure data integrity, and assist in building prototypes and test environments. The engineer contributes to the development lifecycle by configuring storage systems, automating test setups, and analyzing system behavior under various workloads. This position is ideal for individuals with a foundational understanding of storage technologies and a passion for hands-on experimentation and product innovation. Preferred Technical Expertise: Practical working experience with Java, Python, GoLang, ReactJS, Knowledge of AI/ML/DL, Jupyter Notebooks, Storage Systems, Kubernetes, Container technologies, REST API, UI skills, Exposure to cloud computing technologies such as Red Hat OpenShift, Microservices Architecture, Kubernetes/Docker Deployment. Basic understanding of storage technologies: SAN, NAS, DAS Familiarity with RAID levels and disk configurations Knowledge of file systems (e.g., NTFS, ext4, ZFS) Experience with operating systems: Windows Server, Linux/Unix Basic networking concepts: TCP/IP, DNS, DHCP Scripting skills: Bash, PowerShell, or Python (for automation) Understanding of backup and recovery tools (e.g., Veeam, Commvault) Exposure to cloud storage: AWS S3, Azure Blob, or Google Cloud Storage Linux Developer: As a Linux developer, you would be involved in design and development of advanced features in the Linux OS for the next generation server platforms from IBM by collaboration with the Linux community. You collaborate with teams across the hardware, firmware, and upstream Linux kernel community to deliver these capabilities. Preferred Technical Expertise Excellent knowledge of the C programming language Knowledge of Linux Kernel internals and implementation principles. In-depth understanding of operating systems concepts, data structures, processor architecture, and virtualization Experience with working on open-source software using tools such git and associated community participation processes. Hardware Management Console (HMC) / Novalink Software Developer: As a Software Developer in HMC / Novalink team, you will work on design, development, and test of the Management Console for IBM Power Servers. You will be involved in user centric Graphical User Interface development and Backend for server and virtualization management solution development in Agile environment. Preferred Technical Expertise Strong Programming skills in in Core Java 8, C/C++ Web development skills in JavaScript (Frameworks such as Angular.js, React.js etc),, HTML, CSS and related technologies Experience in developing rich HTML applications Web UI Frameworks: Vaadin, React JS and UI styling libraries like Bootstrap/Material Knowledge of J2EE, JSP, RESTful web services and GraphQL API AIX Developer: AIX is a proprietary Unix operating system which runs on IBM Power Servers. It’s a secure, scalable, and robust open standards-based UNIX operating system which is designed to meet the needs of Enterprises class infrastructure. As an AIX developer, you would be involved in development, test or support of AIX OS features development or open source software porting/development for AIX OS Preferred Technical Expertise Strong Expertise in Systems Programming Skills (C, C++) Strong knowledge of operating systems concepts, data structures, algorithms Strong knowledge of Unix/Linux internals (Signals, IPC, Shared Memory,..etc) Expertise in developing/handling multi-threaded Applications. Good knowledge in any of the following areas User Space Applications File Systems, Volume Management Device Drivers Unix Networking, Security Container Technologies Linkers/Loaders Virtualization High Availability & clustering products Strong debugging and Problem-Solving skills Performance Engineer: As a performance Engineer , you will get an opportunity to conduct experiments and analysis to identify performance aspects for operating systems and Enterprise Servers. where you will be responsible for advancing the product roadmap by using your expertise in Linux operating system, building kernel , applying patches, performance characterization, optimization and hardware architecture to analyse performance of software/hardware combinations. You will be involved in conducting experiments and analysis to identify performance challenges and uncover optimization opportunities for IBM Power virtualization and cloud management software built on Open stack. The areas of work will be on characterization, analysis and fine-tune application software to help deliver optimal performance on IBM Power. Preferred Technical Expertise Experience in C/C++ programming Knowledge of Hypervisor, Virtualization concepts Good understanding of system HW , Operating System , Systems Architecture Strong skills in scripting Good problem solving, strong analytical and logical reasoning skills Familiar with server performance management and capacity planning Familiar with performance diagnostic methods and techniques Firmware Engineer: As a Firmware developer you will be responsible for designing and developing components and features independently in IBM India Systems Development Lab. ISDL works on end-to-end design, development across Power, Z and Storage portfolio. You would be a part of WW Firmware development organization and would be involved in designing & developing cutting edge features on the open source OpenBMC stack (https://github.com/openbmc/) and developing the open source embedded firmware code for bringing up the next generation enterprise Power, Z and LinuxONE Servers. You will get an opportunity work alongside with some of the best minds in the industry, forum and communities in the process of contributing to the portfolio. Preferred Technical Expertise Strong System Architecture knowledge Hands on programming skills with C, C++ , C on Linux Distros. Experience/exposure in Firmware/Embedded software design & development, Strong knowledge of Linux OS and Open Source development Experience with Open Source tools & scripting languages: Git, Gerrit, Jenkins, perl/python Other Skills (Common For All The Positions): Strong Communication, analytical, interpersonal & problem solving skills Ability to deliver on agreed goals and the ability to coordinate activities in the team/collaborate with others to deliver on the team vision. Ability to work effectively in a global team environment Enterprise System Design Software Engineer: The Enterprise Systems Design team is keen on hiring passionate Computer science and engineering graduates / Masters students, who can blend their architectural knowledge and programming skills to build the complex infrastructure geared to work for the Hybrid cloud and AI workloads. We have several opportunities in following areas of System & chip development team : Processor verification engineer Needs to develop the test infrastructure to verify the architecture and functionality of the IBM server processors/SOC or ASICs. Will be responsible to creatively think of all the scenarios to test and report the coverage. Work with design as well as other key stakeholders in identifying /debugging & Resolving logic design issues and deliver a quality design Processor Pre / Post silicon validation engineer As a validation engineer you would design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. Electronic design automation – Front & BE tool development. EDA tools development team is responsible for developing state of the art Front End verification , simulation , Formal verification tools , Place & Route, synthesis tools and Flows critical for designing & verifying high performance hardware design for IBM's next generation Systems (IBM P and Z Systems) which is used in Cognitive, ML, DL, and Data Center applications. Required Professional And Technical Skills: Functional Verification / Validation of Processors or ASICs. Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Strong C/C++programming skills in a Unix/Linux environment required Great scripting skills – Perl / Python/Shell Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow. Understand Verilog / VHDL , verification coverage closure Proven problem-solving skills and the ability to work in a team environment are a must

Rambus, a premier chip, and silicon IP provider, is seeking to hire an exceptional mid-level Design and Verification Engineer to join our PHY integration team The successful candidate will participate in pre-silicon RTL Design and Verification activities related to PCIe and CXL Controller Soft IP development and PHYs integrations, on leading-edge PCI-Express and CXL controller technologies This is a Full Time position Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles Responsibilities Verilog RTL design in order to integrate different IPs together such as PCIe IP with vendor PHY module Verifying the IP integration with dedicated simulation environment Development and support test cases of different verification environments Support worldwide customers on the IP integration Get familiar to existing verification process, propose improvements Maintain the traceability from the customer specification or the product specification to the architecture and verification results Track and maintain verification productivity metrics Reporting periodically on progress and difficulties Qualifications Positive and self-driven achiever with: "Can Do" Attitude Bachelor or Master's degree in Electronics Engineering, Computer Science, or related disciplines Strong analytical and problem-solving skills Excellent interpersonal skills Open for traveling abroad Work in international organization and specially with teams in France, USA, Taiwan and India Because Rambus operates internationally, very good English is important for the position Your technical experience: 6+ years experience verification with Verilog, SystemVerilog, FPGA prototyping 6+ years experience with complex ASIC/VLSI verification 6+ years experience with Avery or UVM Any 3rd party VIP experience is a plus 6+ years experience in multinational company Experience with creating documentation, python, shell & etc About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrows systems Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures If you require assistance or an accommodation due to a disability, please feel free to inform us in your application Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services For more information about Rambus, visit rambus, For additional information on life at Rambus and our current openings, check out rambus,/careers/

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: FPGA Design engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: Strong in digital design. Strong in Xilinx Vivado IP & IPI tools till bit-generation. Knowledge of VHDL/Verilog/System Verilog. Knowledge of Validating IP/IP Example designs on Xilinx boards, debugging of failures on target boards, board bring up. Proficiency in Linux environment. Good communication skills. Basic Job Deliverable: RTL coding, IP design, Modify/update existing IP as per requirements. Qualification: Bachelors/Master’s in ECE TekWissen® Group is an equal opportunity employer supporting workforce diversity.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - SENIOR SILICON DESIGN ENGINEER The Role AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS Work with multi-functional teams and handling schedules The successful candidate may also be responsible of: Debugging and verifying block-/chip-level DFT/DFX features Porting or creating the DFT/DFX verification environment Block/Chip test plan creation and development Stimulus writing and debug, and regression clean-up Generating high quality manufacturing test patterns for stuck-at, transition fault models and using on-chip test compression techniques Stimulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Provide technical support to other teams Preferred Experience Minimum 5 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Strong problem-solving skills. Team player with strong communication skills. Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission Responsibilities Functional validation of ASIC SOC at Block, Cluster or Fullchip using UVM/C test bench Develop Test Plan and write unit tests for functional validation Create and Manage regression suites, debug failures, and drive timely resolution Innovate to improve validation efficiency through methodologies and tools Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion Qualifications Required Qualifications: Bachelor's degree or above in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience. Experience in Logic Design or Verification. Expereince with ASIC verification flow. Experience with Verilog, System Verilog, and UVM based testbench environment. Preferred Qualifications Knowledge of one of Ethernet, TCP/IP, PCIe, or High Speed Memory Technologies Good understanding of Computer Architecture Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Embedded Hardware strong in Project Management, Team Leading, Individual Contributor, Embedded Firmware, Embedded Hardware, Embedded Software, Embedded Systems, Agile Methodology etc.

Embedded Hardware strong in Project Management, Team Leading, Individual Contributor, Embedded Firmware, Embedded Hardware, Embedded Software, Embedded Systems, Agile Methodology etc.

Senior SOC Verification Engineer Bangalore, Karnataka, India Date posted Jul 22, 2025 Job number 1848626 Work site Up to 50% work from home Travel 0-25 % Role type Individual Contributor Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Compute Development Organization (CCDO) team is instrumental in defining and delivering silicon solutions for the Cobalt program through hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. CCDO is at the forefront of innovation and application of AI to silicon development workflows. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for an Individual contributor to join the team. Qualifications Required Qualification 10+ years in ASIC verification, with deep expertise in performance validation across IP, subsystem, and SoC levels. Strong background in SystemVerilog, UVM, and simulation tools. Strong C and C++ Coding skills Experience with server-class SoCs, including Intel and ARM architectures. Familiarity with protocols such as PCIe, DDR, AXI, CHI and CXL. Proven track record in leading verification teams and delivering high-quality silicon. Strong analytical and debugging skills, with experience in correlating RTL vs C-model performance. Preferred Qualification Experience in one or more of the following: coherency, caches, fabrics, reset, power management, design for debug (DFD), Double Data Rate (DDR) controllers, and PH, virtualization, interrupts, security, Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Universal Serial Bus (USB), low speed IOs (SPI, I3C, etc.), AXI/CHI protocol bridges or other complex IP/blocks or subsystems Hands-on technical leadership experience such as creating bottom’s up schedules, coordinating work across a team, driving verification closure, or solving cross-team technical problems Experience with verification for multiple product cycles from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff Experience in creating, maintaining, or integrating test benches, checkers and stimulus using System Verilog Test Bench (SVTB), Universal Verification Methodology (UVM), Formal Verification and/or C Experience in automating verification processes using Python or another scripting language Publications or presentations in industry forums (e.g., SNUG, User2User). Experience with AI-based verification technologies . Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Responsibilities Lead performance verification strategy and execution for server-class SOC's in a multi-die simulation environment. Collaborate with SoC/IP architects to define performance limits and resolve debug issues. Develop and manage test plans, model strategies, and infrastructure across various flows including DV, power, and performance. Coordinate with cross-functional stakeholders to manage dependencies, schedules, and deliverables. Drive automation for regression management, post-processing, and streamlined execution. Resolve infrastructure challenges to ensure high-quality, single-step production readiness. Contribute to technical readiness studies for new server product proposals and silicon lifecycle planning. Architect reusable verification environments and system-level use cases for performance validation. Make use of and contribute to industry-leading Generative AI verification tools and flows Deploy project planning methodologies and define verification strategies, resource allocation, and risk mitigation plans Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

You will be responsible for executing customer projects independently with minimum supervision, guiding team members technically in various fields of VLSI Frontend Backend or Analog design. As an individual contributor, you will take ownership of tasks/modules such as RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc., leading the team to achieve results. Your responsibilities will include completing assigned tasks successfully and on-time within the defined domain(s), anticipating, diagnosing, and resolving problems, coordinating with cross-functional teams as necessary, delivering on-time quality work approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost accepted by UST Manager and Client. Additionally, you will be expected to write papers, file patents, and devise new design approaches. Your performance will be measured based on the quality of deliverables, timely delivery, reduction in cycle time and cost, number of papers published, number of patents filed, and number of trainings presented to the team. You will be expected to ensure zero bugs in the design/circuit design, deliver clean design/modules for ease of integration, meet functional specifications/design guidelines without deviation, and document tasks and work performed. Furthermore, you will be responsible for meeting project timelines, facilitating other team members" progress by delivering intermediate tasks on time, and seeking help and support in case of any delays. Your role will also involve active participation in team work, supporting team members as needed, anticipating when support may be required, and being able to explain project tasks and support delivery to junior team members. Your creativity and innovation will be showcased through tasks such as automating processes to save design cycle time, participating in technical discussions, training forums, white paper or patent filings, and contributing to technical discussions. Your skill set should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, Makefile, Spice, and familiarity with EDA Tools like Cadence, Synopsys, Mentor tool sets, and various simulators. You should have strong technical knowledge in IP Spec Architecture Design, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, Analog Layout, Synthesis, DFT, Floorplan, Clocks, P&R, STA, Extraction, Physical Verification, Soft/Hard/Mixed Signal IP Design, and Processor Hardening. Additionally, you should possess communication skills, analytical reasoning, problem-solving skills, and the ability to interact effectively with team members and clients. Your knowledge and experience should reflect leadership and execution of projects in areas such as RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and understanding of design flow and methodologies. Independent ownership of circuit blocks, clear communication, diligent documentation, and being a good team player are essential attributes for this role. Overall, your role will involve circuit design and verification of Analog modules in TSMC FinFet technologies, developing circuit architecture, optimizing designs, verifying functionality, performance, and power, as well as guiding layout engineers. Strong problem-solving skills, results orientation, attention to detail, and effective communication will be key to your success in this position.,

As the owner of Ethernovia's India digital hardware team, you will be responsible for all aspects of digital design and digital verification. This position requires both hands-on technical contribution as well as managerial and technical leadership. You will hire and build your own team to plan and execute the design, verification, and validation of advanced automotive communication semiconductors and systems. Key Qualifications: - BS and/or MS in Electrical Engineering, Computer Science, or related field - Minimum 15+ years combined of ASIC design, verification, and leadership experience - Strong understanding of ASIC design and verification fundamentals and industry standard methodologies - Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++ - Experience with the full verification flows, from spec to coverage analysis to gate level sims with SDF - Experience with all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals - Successful track record of leading and growing a digital hardware team - Debugging failures in simulation to root cause problems - Self-motivated and able to work effectively both independently and collaboratively - Startup attitude and expected compensation required Additional Success Factors: - Experience in any of the following areas: Networking (PCIe, Ethernet, MAC, PHY, Switching, TCP/IP, security, and other industry standard protocols), Video standards, protocols, processing, Digital signal processing filters, Third party IP (SerDes, controllers, processors, etc.), Modular and Reusable Testbench architecture, Design for re-use of pre and post-silicon tests and infrastructure, Automation of testbench creation, tests, regression, or EDA tools, Knowledge of SystemC and/or DPI Personal Skills: - Excellent communication/documentation skills - Attention to details - Collaboration across multidisciplinary and international teams What you'll get in return: - Technology depth and breadth expansion that can't be found in a large company - Opportunity to grow your career as the company grows - Pre-IPO stock options - Cutting-edge technology - World-class team - Competitive base salary - Flexible hours - Flexible vacation time to promote a healthy work-life balance,

Cadence Design Systems is seeking a Lead Hardware Engineer for their DFT IP R&D team in Noida with 4-6 years of experience. As a member of the R&D staff, you will be working on Cadence's MODUS DFT software solution, a comprehensive product designed to achieve high coverage, reduced test time, and superior PPA. We are looking for candidates with expertise in various areas such as RTL design, DFT architecture, verification, power analysis, and optimization. This role involves developing cutting-edge DFT tools, designing and verifying RTL and test benches, and providing support to application and product engineers. You will be part of a team responsible for creating innovative technologies in the DFT space. Your responsibilities will include designing, developing, and supporting the MODUS software product. This position offers an opportunity to build a solid foundation in logic circuits and contribute to DFT IP tool development. The role involves enhancing usability and quality through feature enhancement and rigorous verification. You will also provide R&D support, problem analysis, debugging, and develop new features to optimize synthesis results for timing, area, and power. At Cadence, we value innovation and research. The successful candidate will receive mentoring and support to contribute to the EDA problem domain and enhance their problem-solving skills. The ideal candidate should be proficient in RTL design using Verilog and SystemVerilog, have knowledge of front-end EDA tools, SystemVerilog assertions, and advanced verification techniques. Familiarity with scripting languages like Perl or Python, DFT methodologies, and synthesis tools is desirable. Excellent communication skills are essential, along with a strong foundation in data structures and algorithms. Qualifications for this position include an M.Tech, M.E, B.Tech, or B.E. in EE/ECE/CS or equivalent, a good understanding of Digital Electronics, prior knowledge of Verilog/System Verilog, and EDA tools. Join us at Cadence to work on projects that truly matter and help us solve challenges that others can't.,

As a member of the QuestaSim (Simulation) R&D team at Siemens EDA, you will play a crucial role in designing and developing AI/ML-driven algorithms and solutions to enhance the performance and capabilities of simulation tools. Your contributions will involve creating cutting-edge engines and components, integrating machine learning techniques into simulation and verification workflows, and enhancing existing codebases. In this role, you will collaborate with a team of experienced engineers to solve complex problems in a dynamic environment. Your expertise in AI/ML frameworks, data-driven problem solving, and traditional simulation technologies will be key in achieving project milestones. Your ability to stay self-motivated, disciplined, and innovative will drive progress within the team. To excel in this position, you should hold a Bachelors or Masters degree in Computer Science, Artificial Intelligence, Electrical Engineering, or a related technical field. Your hands-on experience with AI/ML techniques such as supervised and unsupervised learning, neural networks, and reinforcement learning will be essential. Proficiency in programming languages like C/C++ and Python, along with a strong foundation in algorithms and data structures, is required. Knowledge of machine learning and deep learning frameworks, compiler concepts, optimizations, parallel computing, UNIX/Linux platforms, and problem-solving skills are also crucial for this role. Additionally, familiarity with Digital Electronics, SystemVerilog, Verilog, VHDL, simulation technologies, and formal-based verification methodologies will be advantageous. At Siemens, we value diversity and inclusion, and we are committed to creating a workplace where all individuals are respected and empowered. If you are passionate about shaping the future through innovation and technology, we encourage you to join us on this exciting journey. Your curiosity and creativity will help us build a better tomorrow.,

You will be joining a company specializing in the design and development of applications for FPGA target platforms. As an Engineer, your primary focus will be on programming in VHDL or Verilog and Matlab, specifically for working on FPGA platforms for communication protocol/algorithm development. Your responsibilities will include designing, developing, and debugging VHDL or Verilog based systems, while possessing a strong understanding of the FPGA platform development lifecycle. The ideal candidate will have hands-on expertise in FPGA-based system design and development. This is a full-time position.,

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be an integral part of the Circuit Technology team, focusing on DFT Methodology/Architect/RTL execution for high-speed SERDES Phys, Next-gen Memory Phys, and Die-to-Die interconnect IPs. Your responsibilities will include defining the DFX architecture for high-speed PHYs and die-to-die connectivity IP designs, RTL coding, supporting scan stitching, developing timing constraints, assisting with ATPG, and post-silicon bringup. Join a dynamic team that delivers cutting-edge IPs crucial for every SOC developed by AMD. The ideal candidate possesses strong analytical and problem-solving skills with keen attention to detail. You must demonstrate the ability to work hands-on, be a self-starter, a leader, and independently drive tasks to completion. Key Responsibilities: - Lead and define Design for Test/Debug/Yield Features specific to PHYs. - Implement DFX features into RTL using Verilog. - Comprehend DFX Architectures and micro-architectures. - Utilize JTAG (1149.1/1687/1500)/IJTAG, Scan Compression (EDT, SSH), and at-speed scan testing implementation. - Conduct gate-level simulation using Synopsys VCS and Verdi. - Perform Spyglass bringup and analysis for scan readiness/test coverage gaps. - Plan, implement, and verify MBIST. - Assist Test Engineering in planning, patterns, and debug. - Support silicon bring-up and debug. - Develop efficient DFx flows and methodology compatible with front-end and physical design flows. Preferred Experience: - Proficiency in industry-standard ATPG and DFx insertion CAD tools. - Familiarity with industry-standard DFX methodology: e.g., Streaming Scan Network (SSN), IJTAG, ICL/PDL, etc. - Knowledge of SystemVerilog and UVM. - Expertise in RTL coding for DFx logic, including lock-up latches, clock gates, and scan anchors. - Understanding of low-power design flows such as power gating, multi-Vt, and voltage scaling. - Strong grasp of high-performance, low-power design fundamentals. - Familiarity with fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware. - Exposure to post-silicon testing and tester pattern debug is advantageous. - Excellent problem-solving and debug skills across various design hierarchies. Academic Credentials: - BS/MS/PhD in EE/ECE/CE/CS with industry experience in advanced DFx techniques. Join AMD and be a part of a culture that values innovation, problem-solving, and collaboration. Together, we can advance technology and shape the future of computing.,

Dear Candidate , Greeting from HCL Tech!!!!!!! We have come across your profile in Portal. Please Ignore if you already shared or submitted Details or Applied. As its a default retrigger. We are hiring on below Design Verification Engineer - Engineer/Lead/Senior Lead . Please find the JD Details below - Please share us your details below in Table with your update resume. JD - Design Verification Engineer - Engineer/Lead/Senior Lead Qualifications: Bachelors degree in electrical engineering, Computer Engineering, or a related field (masters degree a plus) Experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Please fill the details in below table Full Name (As per Passport/10th Class ) Highest Qualification(Distance/Regular) Total Exp Years Relevant Exp Years Exp Design Verification Engineer(Please specify) Years/Months Exp ASIC Years/Months Exp SOCS Years/Months Exp simulation tools : Please specify tools exp, which you hold Years/Months Exp scripting languages Years/Months Exp digital design principles Years/Months Exp verification methodologies (e.g., UVM) Years/Months Exp Verilog or VHDL Years/Months Mobile Number – Alternate Mobile Number – Mail ID Alternate Mail ID CTC ECTC (Please share expectation in number not in % or as per standards) Notice Period(Buyout options/on Bench/Currently serving(Please specify lwd) Current Company Current Location Have you attend Interview at HCL- Have you worked for HCL if Yes(Please share EX- HCL EMPID- Duration ) Preferred Location Reason for leaving Holding any offers /Any Pipeline :

Position: Project Lead – MEO SATCOM Network & SCPC Platform Integration Location: Bangalore, KA Duration: 6+ months Mode: 3 days onsite We are seeking a dynamic and technically astute Project Lead to manage a cutting-edge satellite communications initiative supporting a Medium Earth Orbit (MEO) constellation designed for third-party SATCOM network hosting. This program is a strategic response to defense industry demand for extending existing modem capabilities beyond traditional GEO environments. The project will deliver a DVB-S2X-based SCPC solution using 450mp modems, integrated at both hub and terminal levels, and supporting OpenAMIP and OpenBMIP protocols for seamless terminal mobility and control within the MEO network architecture. This role requires full ownership of the project lifecycle—from planning through execution—while providing hands-on technical leadership and oversight to a blended across both US and India. Lead the design, integration, and deployment of SCPC modem systems compatible with a generic MEO network infrastructure. Manage cross-functional teams developing: Microservices in Go, Python, and other languages. External APIs using GraphQL and internal services using RESTful APIs. Embedded system components in C++, Go, and Python. Oversee design and verification of FPGA-based DSP algorithms using Verilog, System Verilog, or VHDL targeting Xilinx/Altera platforms. Coordinate efforts involving OpenAMIP and OpenBMIP integration for automated terminal configuration and mobility support. Drive system validation and automation testing using tools such as Behave/Cucumber, Jira, Bitbucket, Jenkins, Artifactory, and Docker. Required Qualifications: · Bachelor’s or Master’s degree in Computer Science, Engineering, or a related field. · 8+ years of experience in software development and architecture. · 5+ years of experience leading projects of similar complexity and scope.

We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world. Apprenticeship Experience: At Synopsys, apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today! Mission Statement: Our mission is to fuel today’s innovations and spark tomorrow’s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive—both at work and beyond. What You’ll Be Doing: Troubleshooting software programs. Managing R&D regressions. Creating validation suites for feature enhancements. Learning and exploring new technologies. Networking with internal and external personnel on assigned tasks. What You’ll Need: Should be a fresh graduate engineer in Computer Science or Electronics (2025). Knowledge of coding (C/C++) and scripting (Perl, Python). Understanding of Data Structures and Basic Operating Systems Concepts. Knowledge of Verilog/VHDL and EDA tools is a plus. Key Program Facts: Program Length: 12 months Location: Noida, India Working Model: In-office Full-Time/Part-Time: Full-time Start Date: Aug/Sep 2025 Equal Opportunity Statement: Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.

B.E./B.Tech or M.E./M.Tech in Electrical/Electronics Engineering or Physics5+ years of hands-on experience in analog circuit design and EDA toolsStrong command over circuit simulation, layout porting, and analog front-end development Required Candidate profile Develop and support new design/technology porting flows Collaborate with PDK, Modeling, and Device teams Enable and validate schematic layout porting, set up analog simulations