2300 Verilog Jobs - Page 12

As a Silicon Design Engineer with over 5 years of experience in RTL design and development, you will be responsible for creating RTL designs and developing various documents such as requirements specification, design, user guides, etc. Your expertise in FPGA VHDL and/or Verilog design using Xilinx technology and tools will be crucial in this role. Additionally, your experience with Ethernet, PCIe, SPI, I2C, USB, GPIO, Memory architectures, DDR, SDRAM, DMA technologies, and hardware testing will be valuable assets. You should be adept at HW testing, including working with test equipment such as logic and traffic analyzers, test generators, etc. Strong debugging skills at both device and board levels will be essential. Proficiency in scripting languages like Perl, Python, or TCL will be beneficial. Your excellent interpersonal, written, and verbal communication skills will enable you to collaborate effectively with cross-functional teams. Moreover, your problem-solving and analytical skills will be put to good use in this dynamic role. If you are interested in this opportunity, please submit your updated resume to janagaradha.n@acldigital.com. Your contributions as a Silicon Design Engineer will play a vital role in the successful development of cutting-edge technology solutions.,

At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Location: Bangalore/Kolkata Experience: 3+ years Opportunity Snapshot: We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills. You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems. You will have a significant opportunity to interact with system design teams across geographies. Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture. Thus, you set your own limits for learning, achievements and rewards. Responsibilities: Define and architect high-performance blocks for the latest, most advanced networking ASICs Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power Collaborate with the verification team in the development of the testplan and assist in debugging test failures Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes Required Skills: 3+ years of ASIC design experience Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus Knowledge of high performance memory subsystems Knowledge of multi-domain clock synchronization and high-speed serial interfaces Strong problem solving and ASIC debugging skills Excellent written and verbal communications skills MSEE or BSEE is required About Juniper Networks Juniper Networks challenges the inherent complexity that comes with networking and security in the multicloud era. We do this with products, solutions and services that transform the way people connect, work and live. We simplify the process of transitioning to a secure and automated multicloud environment to enable secure, AI-driven networks that connect the world. Additional information can be found at Juniper Networks (www.juniper.net) or connect with Juniper on Twitter, LinkedIn and Facebook. WHERE WILL YOU DO YOUR BEST WORK? Wherever you are in the world, whether it's downtown Sunnyvale or London, Westford or Bengaluru, Juniper is a place that was founded on disruptive thinking - where colleague innovation is not only valued, but expected. We believe that the great task of delivering a new network for the next decade is delivered through the creativity and commitment of our people. The Juniper Way is the commitment to all our colleagues that the culture and company inspire their best work-their life's work. At Juniper we believe this is more than a job - it's an opportunity to help change the world. At Juniper Networks, we are committed to elevating talent by creating a trust-based environment where we can all thrive together. If you think you have what it takes, but do not necessarily check every single box, please consider applying. We’d love to speak with you. Additional Information for United States jobs: ELIGIBILITY TO WORK AND E-VERIFY In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire. Juniper Networks participates in the E-Verify program. E-Verify is an Internet-based system operated by the Department of Homeland Security (DHS) in partnership with the Social Security Administration (SSA) that allows participating employers to electronically verify the employment eligibility of new hires and the validity of their Social Security Numbers. Information for applicants about E-Verify / E-Verify Información en español: This Company Participates in E-Verify / Este Empleador Participa en E-Verify Immigrant and Employee Rights Section (IER) - The Right to Work / El Derecho a Trabajar E-Verify® is a registered trademark of the U.S. Department of Homeland Security. Juniper is an Equal Opportunity workplace. We do not discriminate in employment decisions on the basis of race, color, religion, gender (including pregnancy), national origin, political affiliation, sexual orientation, gender identity or expression, marital status, disability, genetic information, age, veteran status, or any other applicable legally protected characteristic. All employment decisions are made on the basis of individual qualifications, merit, and business need.

"> Search Jobs Find Jobs For Where Search Jobs Sr. Engineer - Verification Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12162 Remote Eligible No Date Posted 20/07/2025 Alternate Job Titles: ASIC Verification, Sr. Engineer Sr. Engineer, Digital Verification We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and innovative engineer with a strong background in high-speed protocols and a keen interest in growing your expertise through verification-related work. You thrive in a collaborative environment, working alongside experienced digital design and verification professionals. With a solid foundation in Verilog, VHDL, and/or SystemVerilog, you are eager to expand your knowledge and apply your skills to state-of-the-art products. Your excellent problem-solving abilities and strong communication skills enable you to identify and address design issues effectively. You are organized, detail-oriented, and capable of managing multiple tasks efficiently. With your passion for learning and exploring new technologies, you are committed to contributing to the success of our projects and the broader goals of Synopsys. What You ll Be Doing: Identify verification environment requirements from various sources, including specifications, design functionality, and interfaces. Generate verification test plans, environment documentation, and usage documentation. Define, develop, and verify complex UVM verification environments. Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics. Identify design problems, propose corrective actions, and address inconsistencies in documented functionality. Collaborate with cross-functional teams to ensure the successful integration and verification of projects. The Impact You Will Have: Ensure the robustness and reliability of our digital designs through meticulous verification processes. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enhance the overall quality and performance of our silicon IP products. Help our customers bring differentiated products to market quickly and with reduced risk. Drive continuous improvements in our verification methodologies and practices. Support the growth and success of Synopsys by contributing to our reputation for innovation and excellence. What You ll Need: Proven desire to learn and explore new state-of-the-art technologies. Demonstrated proficiency in Verilog, VHDL, and/or SystemVerilog. Experience with scripting languages such as BASH, TCSH, PERL, PYTHON, or TCL is a plus. Understanding of verification methodologies such as UVM is a plus. Strong organizational and communication skills. 3+ years of relevant experience in ASIC digital verification. Who You Are: A passionate and innovative engineer with a strong technical background. Detail-oriented and capable of managing multiple tasks efficiently. Excellent problem-solving abilities and a proactive approach to addressing challenges. Strong communication skills, both written and spoken. A collaborative team player who thrives in a dynamic and fast-paced environment. The Team You ll Be A Part Of: You will join an experienced and dedicated digital design and verification team focused on developing state-of-the-art products. Our team is committed to excellence and continuous improvement, working collaboratively to achieve our goals. You will have the opportunity to learn from experts in various fields and contribute to the success of our projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

"> Search Jobs Find Jobs For Where Search Jobs Staff RTL Design Engineer Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12211 Remote Eligible No Date Posted 21/07/2025 Alternate Job Titles: Senior Digital Design Engineer ASIC Design Engineer High-Speed SerDes Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces. You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards, and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure, sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You ll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage, and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You ll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities. The Team You ll Be A Part Of: You will be part of the High-Speed SerDes Digital Design Team, a group of talented engineers dedicated to developing high-performance serial link PHY IPs. The team focuses on innovation, quality, and collaboration to deliver industry-leading solutions. Together, you will work on challenging projects that push the boundaries of technology and make a significant impact on the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Data Centre Engineering Group develops Custom Silicon products tailored for the Data Centre market, focusing on cutting-edge Accelerated Infrastructure solutions for Networking, Switching, Connectivity, and Compute. The team works on high-performance and scalable architectures, ensuring optimized performance, power efficiency, and reliability to meet evolving data center demands. By collaborating across multiple teams, the group delivers best-in-class silicon solutions that drive innovation in next-generation data center applications. What You Can Expect Architect and implement simulation test bench in UVM. Develop and execute test-plans for verifying correctness and performance of the design. Own and debug failures in simulation to root-cause problems Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations What We're Looking For Bachelor’s degree in CS/EE with 13–15 years of relevant experience, or Master’s degree in CS/EE with 10–12 years of relevant experience Strong background in IP and SoC verification, including methodology and testbench development Proficient in hardware verification languages such as Verilog, SystemVerilog, UVM, and C/C++ Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations Experience in Unix/Linux environments; scripting skills in Shell, Perl, or Python are a plus Strong analytical and problem-solving skills Ability to manage multiple tasks in a fast-paced environment Excellent communication, interpersonal, and teamwork skills Capable of interfacing effectively at all levels within and outside the organization Proactive in participating in problem-solving and quality improvement initiatives Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Category Engineering Hire Type Employee Job ID 12211 Remote Eligible No Date Posted 21/07/2025 Alternate Job Titles: Senior Digital Design Engineer ASIC Design Engineer High-Speed SerDes Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces. You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards, and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure, sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You’ll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage, and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You’ll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities. The Team You’ll Be A Part Of: You will be part of the High-Speed SerDes Digital Design Team, a group of talented engineers dedicated to developing high-performance serial link PHY IPs. The team focuses on innovation, quality, and collaboration to deliver industry-leading solutions. Together, you will work on challenging projects that push the boundaries of technology and make a significant impact on the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Alternate Job Titles: ASIC Verification, Sr. Engineer Sr. Engineer, Digital Verification We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and innovative engineer with a strong background in high-speed protocols and a keen interest in growing your expertise through verification-related work. You thrive in a collaborative environment, working alongside experienced digital design and verification professionals. With a solid foundation in Verilog, VHDL, and/or SystemVerilog, you are eager to expand your knowledge and apply your skills to state-of-the-art products. Your excellent problem-solving abilities and strong communication skills enable you to identify and address design issues effectively. You are organized, detail-oriented, and capable of managing multiple tasks efficiently. With your passion for learning and exploring new technologies, you are committed to contributing to the success of our projects and the broader goals of Synopsys. What You’ll Be Doing: Identify verification environment requirements from various sources, including specifications, design functionality, and interfaces. Generate verification test plans, environment documentation, and usage documentation. Define, develop, and verify complex UVM verification environments. Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics. Identify design problems, propose corrective actions, and address inconsistencies in documented functionality. Collaborate with cross-functional teams to ensure the successful integration and verification of projects. The Impact You Will Have: Ensure the robustness and reliability of our digital designs through meticulous verification processes. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enhance the overall quality and performance of our silicon IP products. Help our customers bring differentiated products to market quickly and with reduced risk. Drive continuous improvements in our verification methodologies and practices. Support the growth and success of Synopsys by contributing to our reputation for innovation and excellence. What You’ll Need: Proven desire to learn and explore new state-of-the-art technologies. Demonstrated proficiency in Verilog, VHDL, and/or SystemVerilog. Experience with scripting languages such as BASH, TCSH, PERL, PYTHON, or TCL is a plus. Understanding of verification methodologies such as UVM is a plus. Strong organizational and communication skills. 3+ years of relevant experience in ASIC digital verification. Who You Are: A passionate and innovative engineer with a strong technical background. Detail-oriented and capable of managing multiple tasks efficiently. Excellent problem-solving abilities and a proactive approach to addressing challenges. Strong communication skills, both written and spoken. A collaborative team player who thrives in a dynamic and fast-paced environment. The Team You’ll Be A Part Of: You will join an experienced and dedicated digital design and verification team focused on developing state-of-the-art products. Our team is committed to excellence and continuous improvement, working collaboratively to achieve our goals. You will have the opportunity to learn from experts in various fields and contribute to the success of our projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Excellent understanding of embedded system development and real-time application development. •Hands-on experience in bare-metal code development using C over an embedded platform, D0-178C compliance and certification,FPGA design flow

Location: Bengaluru, Karnataka Experience: Minimum 2 to 5 Years of EdTech/IT/Corporate/Institutions Qualification: BE, BTECH, ME, MTECH, MCA (Any Degree) Shift Timing: 9:00 am to 6:00 pm (Mon to Fri) 9:00 am to 1:00 pm ( Sat ) Skills & Requirements: Create training programs according to requirements. Excellent knowledge of C, C++ and coding platforms. Managerial skills required to train Graduate Engineers, Working professionals, corporate freshers & Laterals. Excellent self-management skills (prioritizing the task). Content Development, Technical Assessment and Evaluation, Project development. Roles & Responsibilities: Strong Training experience in C Programming, Python or Advanced Python Experience in Coding platforms like - LED code/ Code chef/ Hacker rank. Perform testing, debugging and fixing applications using C platform. Design, develop, test, implement and code solutions on C programs like Unix, SQL, .net. Review, analyse and assess programs, designs and specifications for own programs on C applications. Hands on programming with C, C++, Verilog, Linux operating systems, Expertise in handling multiple inhouse and corporate trainings with quality delivery. Experienced in course content development based on the training requirements Experience in developing Hands-on projects and hand-holding large groups of students simultaneously Experienced in all phases of product life cycle including requirements, design, coding. Managing all aspects of the training cycle i.e. Training need analysis, course development, implementation and delivery, monitoring and evaluation. Ensuring quality delivery to students and corporates. Establish Coordination with project members and provide timely feedback Manage the work of developer resources, mentoring and coaching upon requirement. Provide programming direction to a team of trainers. Job Type: Full-time Pay: ₹40,000.00 - ₹65,000.00 per month Education: Bachelor's (Preferred) Experience: C++: 2 years (Preferred) C: 2 years (Preferred) Linux: 2 years (Preferred) Language: English (Preferred) Work Location: In person

Experience -3+ years Experience in RTL coding using Verilog Experience on development on Xilinx MPSoC (ZCU 106/104) Hands on experience on Xilinx Vivado and Vitis, experience on Microblaze, experience on security aspects of authentication

Dear Connections, We are Hiring " Position: RTL Design Engineer" Location: Ahmedabad and Noida (No other locations will be considered) Start Date: Immediate or Aug Experience: 3- 8 Years without any training or internship Job Description: Expertise and strong hands-on experience in RTL design using System Verilog or VHDL Digital system architecture, Processor subsystem architecture and block definition Experience working on complex SoCs RTL design quality analysis – Lint, CDC, RDC Good understanding of digital design Synthesis, DFT and Static Timing Analysis Basic understanding of mixed-signal designs Experience with gate level simulations [GLS] and debug Experience in digital verification is a plus Strong written and verbal communication skills If you are looking for job change share your updated resume to vagdevi@semi-leaf.com “Your reference would be greatly appreciated”

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER The Role The verification team at AMD is looking for a Member of Technical Staff to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs. THE PERSON: You have a passion for modern, complex digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications Interact with architects and design engineers to create a comprehensive verification testplan Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools Debug tests with design engineers to deliver functionally correct design blocks Identify and write coverage measures for stimulus quality improvements Perform coverage analysis to identify verification holes and achieve closure on coverage metrics PREFERRED EXPERIENCE: Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs. Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification. Strong understanding of different phases of ASIC and/or full custom chip development is required. Experience in block level NOC (Net work on Chip) verification is a plus. Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus. Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus. Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus. Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job Description Key Responsibilities – AMS Verification Work in Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs. Hands-on experience with AMS simulation environments using Cadence, Synopsys, or Mentor tools. Solid understanding of analog and mixed-signal circuits, including comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators. Strong knowledge of Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling. Experience in block-level and chip-level AMS verification, including top-level testbench development, self-checking testbenches, and regression suites. Exposure to SystemVerilog (SV) and UVM from an AMS perspective is a plus. Proficiency in scripting languages such as Python, Perl, TCL, or SKILL for automation. Fluency with Cadence Virtuoso-based analog design flow, including schematic capture, simulator/netlist configuration, and SPICE simulation. Ability to extract, analyze, and document simulation results and present findings in technical reviews. Familiarity with test plan development, AMS modeling, and verification methodologies. Supporting post-silicon validation and correlating measurement data with simulations. Team-oriented, proactive, and able to contribute in a multi-site development environment.

To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. • Leading a project for AMS requirements is a value add. • Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools • Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. • Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) • Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus • Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected • Experience working on AMS Verification on multiple SOC’s or sub-systems • Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus • Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment • Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations • Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. • Develop and execute top-level test cases, self-checking test benches and regressions suites • Developing and validating high-performance behavior models • Verifying of block-level and chip-level functionality and performance • Team player with good communication skills and previous experience in delivering solutions for a multi-national client • Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience • Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc. • Ability to extract simulation results, capture in a document and present to the team for peer review • Supporting silicon evaluation and comparing measurement results with simulations • UVM and assertion knowledge would be an advantage

😊Greetings of the day😊!!! This is regarding a Job opportunity with eInfochips as we are having a position of ASIC/FPGA RTL DESIGN ENGINEERS Experience- 3 to 9 Years Location- Noida, Ahmedabad Job Description: Experience in RTL design Verilog/VHDL Simulation tools, Modeslim/VCS etc. Basic protocols, I2C, UART, PCIe, SPI etc. Micro-Architecture experience is a plus CDC/Lint tools Timing analysys CDC design ISO26262 is plus SOC integration Interested candidates share resume at medha.gaur@einfochips.com

1. Strong coding with Verilog and SystemVerilog 2. Good knowledge of AHB,AXI, AMBA protocol, exp in Ethernet 3. Many experiences with sequence creation, functional cover groups and assertion coding. 4. Strong C/C++ software development experiences 5. Be familiar with scripting language, such as Perl, C shell, Makefile, Ruby.

To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. • Leading a project for AMS requirements is a value add. • Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools • Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. • Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) • Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus • Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected • Experience working on AMS Verification on multiple SOC’s or sub-systems • Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus • Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment • Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations • Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. • Develop and execute top-level test cases, self-checking test benches and regressions suites • Developing and validating high-performance behavior models • Verifying of block-level and chip-level functionality and performance • Team player with good communication skills and previous experience in delivering solutions for a multi-national client • Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience • Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc. • Ability to extract simulation results, capture in a document and present to the team for peer review • Supporting silicon evaluation and comparing measurement results with simulations • UVM and assertion knowledge would be an advantage

Qualcomm India Private Limited is seeking a skilled ASIC IP cores design engineer to join their Hardware Engineering team. In this role, you will be responsible for designing and working independently on peripheral IPs, developing design and microarchitecture solutions, guiding and mentoring junior team members, and collaborating with external teams to drive and resolve cross-team dependencies. You will take complete ownership of one or more projects and drive them independently, with the ability to provide schedule estimates and potentially manage people. To be successful in this role, you should have 5-8 years of work experience in ASIC IP cores design and hold a Bachelor's degree in Electrical Engineering, with a preference for a Master's degree. Knowledge of AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking/reset/debug architecture and peripherals like USB, PCIE, and Ethernet, is preferred. Experience in low power design, multi-clock designs, and asynchronous interface is required. You should also have hands-on experience with ASIC development tools like Lint, CDC, Design compiler, and Primetime. Additionally, you should possess strong problem-solving skills, excellent communication abilities, and be a team player. Self-driven individuals who can work with minimal supervision and have experience in System Verilog, Verilog, C/C++, Perl, and Python are preferred. The ability to lead a small design team is also a plus. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities during the application and hiring process. If you require accommodation, you can contact Qualcomm for assistance. It is important to note that Qualcomm expects all employees to adhere to company policies and procedures, including those related to the protection of confidential information. If you are a proactive and experienced ASIC IP cores design engineer looking to work in a challenging and collaborative environment, this position at Qualcomm India Private Limited may be the right fit for you.,

Qualcomm India Private Limited is seeking a talented individual to join our Engineering Group, specifically focusing on Hardware Engineering. In this role, you will be responsible for developing micro-architecture and RTL design for Cores related to security, with a primary focus on block level design. Your responsibilities will also include enabling software teams to utilize hardware blocks effectively, as well as running ASIC development tools such as Lint and CDC. Additionally, you will be expected to report progress status and communicate effectively against set expectations. To be considered for this position, you must hold a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field, along with a minimum of 5 years of Hardware Engineering experience. Preferred qualifications include 5 to 10 years of work experience in ASIC/SoC Design, proficiency in RTL design using Verilog/System Verilog, and knowledge of cryptography concepts such as public/private key, hash functions, and encryption algorithms. Experience in Root of Trust and HW crypto accelerators, defining HW/FW interfaces, Linting, CDC, and LEC will be advantageous. Proficiency in database management flows using tools like Clearcase/Clearquest, as well as programming skills in Verilog, C/C++, Python, and Perl are highly desirable. Excellent oral and written communication skills, along with a proactive and collaborative approach to work, will also be key to success in this role. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please reach out to disability-accommodations@qualcomm.com. It is essential that all employees adhere to applicable policies and procedures, particularly those concerning the protection of confidential information. Please note that Qualcomm does not accept unsolicited resumes or applications from staffing and recruiting agencies. If you have any inquiries about this role, please contact Qualcomm Careers directly.,

Job Requirements Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills. Work Experience Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills.

We are seeking a highly skilled SOC Functional Verification Engineer with expertise in UVM, Verilog/SystemVerilog , and AMBA bus protocols . The ideal candidate will have a strong background in SOC and ASIC verification and be capable of independently handling complex testbench environments and verification tasks. Key Responsibilities Develop and execute functional verification plans for SOC/ASIC designs using SystemVerilog and UVM methodologies. Design, develop, and maintain testbenches, scoreboards, and checkers. Write and run directed and random tests, analyze results, and debug functional failures. Collaborate closely with design, architecture, and software teams to ensure comprehensive verification coverage. Implement code and functional coverage metrics and drive improvements. Work with AMBA bus protocols (AXI, AHB, APB) and verify IP-level and SOC-level integrations. Contribute to verification methodology improvements and reusable IP verification components. Required Skills Strong hands-on experience with SystemVerilog/UVM for functional verification. Solid understanding of ASIC/SOC verification flows. Familiarity with AMBA bus protocols (AXI, AHB, APB). Experience with Verilog for RTL understanding and analysis. Proficient in debugging using simulators and waveform viewers (e.g., VCS, ModelSim, Questa). Knowledge of functional coverage and assertions (SVA) is preferred. Experience with version control and scripting (e.g., Python, Perl, Shell) is a plus. Skills: shell,amba bus protocols,dv,axi,perl,systemverilog,amba,asic,python,functional coverage,soc,functional verification,verilog,apb,ahb,assertions,uvm,debugging

Alternate Job Titles: Senior Digital Design Engineer ASIC Design Engineer High-Speed SerDes Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces. You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards, and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure, sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You’ll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage, and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You’ll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities. The Team You’ll Be A Part Of: You will be part of the High-Speed SerDes Digital Design Team, a group of talented engineers dedicated to developing high-performance serial link PHY IPs. The team focuses on innovation, quality, and collaboration to deliver industry-leading solutions. Together, you will work on challenging projects that push the boundaries of technology and make a significant impact on the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Alternate Job Titles: ASIC Verification, Sr. Engineer Sr. Engineer, Digital Verification We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and innovative engineer with a strong background in high-speed protocols and a keen interest in growing your expertise through verification-related work. You thrive in a collaborative environment, working alongside experienced digital design and verification professionals. With a solid foundation in Verilog, VHDL, and/or SystemVerilog, you are eager to expand your knowledge and apply your skills to state-of-the-art products. Your excellent problem-solving abilities and strong communication skills enable you to identify and address design issues effectively. You are organized, detail-oriented, and capable of managing multiple tasks efficiently. With your passion for learning and exploring new technologies, you are committed to contributing to the success of our projects and the broader goals of Synopsys. What You’ll Be Doing: Identify verification environment requirements from various sources, including specifications, design functionality, and interfaces. Generate verification test plans, environment documentation, and usage documentation. Define, develop, and verify complex UVM verification environments. Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics. Identify design problems, propose corrective actions, and address inconsistencies in documented functionality. Collaborate with cross-functional teams to ensure the successful integration and verification of projects. The Impact You Will Have: Ensure the robustness and reliability of our digital designs through meticulous verification processes. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enhance the overall quality and performance of our silicon IP products. Help our customers bring differentiated products to market quickly and with reduced risk. Drive continuous improvements in our verification methodologies and practices. Support the growth and success of Synopsys by contributing to our reputation for innovation and excellence. What You’ll Need: Proven desire to learn and explore new state-of-the-art technologies. Demonstrated proficiency in Verilog, VHDL, and/or SystemVerilog. Experience with scripting languages such as BASH, TCSH, PERL, PYTHON, or TCL is a plus. Understanding of verification methodologies such as UVM is a plus. Strong organizational and communication skills. 3+ years of relevant experience in ASIC digital verification. Who You Are: A passionate and innovative engineer with a strong technical background. Detail-oriented and capable of managing multiple tasks efficiently. Excellent problem-solving abilities and a proactive approach to addressing challenges. Strong communication skills, both written and spoken. A collaborative team player who thrives in a dynamic and fast-paced environment. The Team You’ll Be A Part Of: You will join an experienced and dedicated digital design and verification team focused on developing state-of-the-art products. Our team is committed to excellence and continuous improvement, working collaboratively to achieve our goals. You will have the opportunity to learn from experts in various fields and contribute to the success of our projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Troubleshooting software programs. Managing R&D regressions. Creating validation suites for feature enhancements. Learning and exploring new technologies. Networking with internal and external personnel on assigned tasks. What You ll Need: Should be a fresh graduate engineer in Computer Science or Electronics (2025). Knowledge of coding (C/C++) and scripting (Perl, Python). Understanding of Data Structures and Basic Operating Systems Concepts. Knowledge of Verilog/VHDL and EDA tools is a plus.

Ansys is looking for Principal R&D Engineer - Implementation flow (physical synthesis / clock tree synthesis) to join our dynamic team and embark on a rewarding career journey Analyzing customer needs to determine appropriate solutions for complex technical issues Creating technical diagrams, flowcharts, formulas, and other written documentation to support projects Providing guidance to junior engineers on projects within their areas of expertise Conducting research on new technologies and products in order to recommend improvements to current processes Developing designs for new products or systems based on customer specifications Researching existing technologies to determine how they could be applied in new ways to solve problems Reviewing existing products or concepts to ensure compliance with industry standards, regulations, and company policies Preparing proposals for new projects, identifying potential problems, and proposing solutions Estimating costs and scheduling requirements for projects and evaluating results