To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. • Leading a project for AMS requirements is a value add. • Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools • Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. • Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) • Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus • Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected • Experience working on AMS Verification on multiple SOC’s or sub-systems • Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus • Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment • Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations • Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. • Develop and execute top-level test cases, self-checking test benches and regressions suites • Developing and validating high-performance behavior models • Verifying of block-level and chip-level functionality and performance • Team player with good communication skills and previous experience in delivering solutions for a multi-national client • Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience • Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc. • Ability to extract simulation results, capture in a document and present to the team for peer review • Supporting silicon evaluation and comparing measurement results with simulations • UVM and assertion knowledge would be an advantage
You will be responsible for the design and development of critical analog, mixed-signal, custom digital blocks, and providing full chip-level integration support. Your expertise in Cadence VLE/VXL and Mentor Graphics Caliber DRC/LVS is essential for this role. You will be required to perform layout verification tasks such as LVS/DRC/Antenna checks, quality assurance, and support documentation. It is crucial to ensure on-time delivery of block-level layouts with high quality standards. Your problem-solving skills will be put to the test in the physical verification of custom layouts. Your role will involve demonstrating high-quality and accurate execution to meet project schedules and milestones in a multi-project environment. You must possess the ability to mentor junior team members in executing sub block-level layouts and reviewing critical items. Contribution to effective project management and clear communication with local engineering teams will be key to the success of layout projects. To be eligible for this position, you should have a BE or MTech degree in Electronic/VLSI Engineering and a minimum of 5 years of experience in analog/custom layout design in advanced CMOS processes. The hiring process will involve CV screening followed by a face-to-face interview.,
Responsibility: Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. • Contribute to effective project-management. • Effectively communicating with Local engineering teams to assure the success of layout project. Educational Background • BE or MTech in Electronic/VLSI Engineering • 5 + year experience in analog/custom layout design in advanced CMOS process. Hiring progress Cv screen+F2F interview.
Skills: Hands-on knowledge to Handle High End Lab equipment such as Scope, JBERT, power supplies. Automation: Python/C++/LabView or VBA based code structure usage. Experience in High Speed Interfaces like PCIe, DDR, USB Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results, prepare reports and have good communication skill with shown dedication in past.
Experience : 7-10 years Number of Positions : 3 Role and Responsibilities : Individual contributor role with ability to perform assigned DV tasks independently Collaborate with other team members to perform DV activities. Skills and Qualification : Domain : CPU/Cache Coherency ,PCIe , SoC DV, CPU DV, NoC/NIC(Interconnects) , DDR/HBM Demonstrate a solid understanding of the CPU/CPU Based SoC Verification. Must have good understanding of one or more of the following domains o ARM v8/v9, RISC-V, x86 Architecture o Memory Architecture(DRAM, Cache, MMU), GIC, SoC Debug Architecture o Cache Coherent Architectures o PCIe OSCI Layer and its functionality o PCIe Phy , Bring up and trainin o SoC DV, BUS Interconnects Understand architecture and micro-architecture specifications. Work closely with Architects and Logic Designers. Develop Unit Level and/or Subsystem Level Test plans, Coverage Plans and checker Plans needed to target zero defect post-silicon quality. Develop scalable Test benches in System Verilog and UVM. Develop Tests, Functional Coverage Models and System Verilog Assertions. Root cause regression failures by debugging Tests/Sequences, RTL and C++ Models. Maintain higher regression efficiency via Test/Coverage Grading, Compute Farm and Disk utilization, etc. Drive Code and Functional Coverage closure. Support debug of Unit RTL/Checkers at higher levels of integration such as Subsystem/Top. Solid understanding of Computer Architecture. Understanding of SoC Architecture ,micro-architecture, logic design, FSMs. Strong functional verification experience including Test planning, Test bench Architecture, Test/Coverage Model/Assertion Development. Strong debugging skills. Proficient in System Verilog/UVM/OVM, OOP/C++ and Python scripting. Previous scripting experience is desirable
Job Description: You will be responsible for testing hardware, identifying observations, and debugging issues in the field of HW Testing. Key Responsibilities: - Possess a BTech/MTech degree in ECE disciplines, preferably 2025 graduates. - Prefer candidates from reputed colleges with a CGPA of 8.0 and above. - Internship/project experience with TI, MaxLinear, or chip-related work is an added advantage. - 02 years of hands-on experience in RF and Wireless domains is desirable. - Must be enthusiastic and ready to work with HW equipment. Qualifications Required: - BTech/MTech degree in ECE disciplines, preferably 2025 graduates. - Candidates from reputed colleges with a CGPA of 8.0 and above preferred. - Internship/project experience with TI, MaxLinear, or chip-related work is an added advantage. - 02 years of hands-on experience in RF and Wireless domains is desirable. - Enthusiastic and ready to work with HW equipment. Location: HYD,
About the Company ThunderSoft is a provider of operating system technologies, superior products and solutions, experts in mobile, IoT, automotive, and enterprise. Founded in 2008, through ThunderSoft’s expertise in edge intelligence and operating systems including Android, Linux, Windows and others, a profound middleware, application, and algorithm technology portfolio, strategic partnerships with key semiconductors, components, terminals, software and Internet vendors, and mobile carriers, give us a unique vertical integration advantage across industries. ThunderSoft is a value-added scaling partner, bringing our customers with innovative, reliable, and commercial-ready products and solutions for the fields of IoT and Intelligent connected vehicle. ThunderSoft has established joint ventures individually with Qualcomm, Arm and Intel. Meanwhile, the company operates joint laboratories with Qualcomm, Intel, Microsoft, Arm, Samsung, and Sony, among many others. The extensive collaboration with industries empowers ThunderSoft to accelerate the development of the smart industry. Job Description : Knowledge related to ML systems Domain knowledge of AI/ML+Embedded systems Programming- C/C++ (Preferred) +TensorFlow / kERAS/PYTORCH DS+OS ML tools
The Role We are seeking an experienced Physical Design Manager to lead SoC/IP implementation on advanced nodes (7nm and below). The role requires strong technical expertise, leadership, and ownership of execution from RTL to GDSII for first-pass silicon success. Key Responsibilities Lead end-to-end Physical Design flow (RTL-to-GDSII) for SoCs/IPs. Own floorplanning, placement, CTS, routing, STA, IR/EM, and signoff. Drive PPA optimisation, ECO closure, and physical verification. Collaborate with RTL, verification, architecture, and packaging teams. Lead EDA flow automation and scripting for efficiency. Mentor and manage a high-performing physical design team. Key Skills & Experience Our USP 10+ years in Physical Design with multiple advanced node tapeouts (7nm & below). Deep expertise in floorplanning, PnR, STA, low-power (UPF), and signoff. Strong knowledge of industry-standard tools (Innovus, PrimeTime, Calibre, Voltus/RedHawk). Proficiency in scripting (TCL/Perl/Python) for automation. Excellent leadership, communication, and cross-functional skills.