2300 Verilog Jobs - Page 14

FPGA Development Vivado is must. Zynq is must plus - Xilinx UltraScale+ AXI interfaces is must RTL design using VHDL and Verilog

Solid Experience in DFT Architecture. The candidate should have experience with ATPG, JTAG, BSCAN, BIST and MBIST flows. Experience on Hierarchical DFT techniques using Pattern Retargeting in Tessent flow Strong knowledge of the Tessent Shell environment and Tessent tools The desired candidate must have specific emphasis on the following tools Test Kompress / Fastscan ATPG, MBIST, Boundary scan. Hands on experience in simulating scan patterns and debugging pattern mismatches during verification process Experience in helping to debug failing scan patterns on the ATE is highly desirable. Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys) Must be able to simulate and debug MBIST testbenches. Ability to come up with a detailed test plan based on the Arch specs Should be knowledgeable in all SOC functions such as Digital design, STA, Synthesis, PnR, DV and ATE test. The candidate should have prior experience in managing and developing teams Required Qualification B.E / B.Tech / M.E / M.Tech in Electrical / Electronic Engineering.experience-10-16 years Preferred experience of handling 10+ team members. Good understanding and exposure to SoC design and architecture Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects Comfortable with VCS / Verdi and excellent debugging skills Logical in thinking and ability to gel well within a team and be a proactive member of the team. Good communication and leadership skills Excellent team player High Integrity Job Type Full Time Job Location Hubballi

SE NIOR SILICON DESIGN ENGINEER Responsibilities: In this role, he/she would be responsible for verification of GPU Design by meeting the demands of the constantly evolving project schedule. The successful candidate will be a member of the GFX team. He/she will demonstrate passion towards design, design verification, be a teammate, a problem solver with independence, creativity, and interpersonal skills. Working with all partners such as lead architects and block design teams to understand features to be implemented and verified. Developing robust test plan for both synthetic testing and real workload trace Debug verification test failures, working with the verification team to accurate defects. Make sure AMD next generation GFXIP can meet performance/power/function expectation. Requirements: Must have Min 8 years of experienced in ASIC verification. Must be proficient in Verilog and System Verilog language Must be good at optimizing timing in digital design. Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools and develop optimal microarchitecture specification that meets PPA goals. Be proficient of script language like Perl, Python. Must demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail. Must have good English hearing, speaking, reading, and writing capabilities. Must have good teamwork and interpersonal skills. Graphics pipeline experience is preferred. Good knowledge of computer architecture is preferred. Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required. #LI-NS1

Front-End Silicon Design Integration (FEINT) Manager The role: A Front-End Silicon Design and Integration (FEINT) Manager role in our Security IP (SECIP) development team, where a large number of embedded micro-processor subsystems, hardware accelerators and other IPs vital to improve system performance and functionality are designed and verified. These IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. As a hands-on FEINT manager, you will lead a number of FEINT engineers, work on performing RTL synthesis and PPA (performance, power, area) analysis in order to improve the QoR (quality of result) of RTL designs, creating, adopting and automating RTL static design rule checks, conducting ECO and LEC validations, as well as supporting SOC integration of the IPs. The person: An experienced FEINT engineering leader with strong records of technical leadership and hands-on execution to drive RTL synthesis, PPA analysis, ECO, and static verification tasks to timely completion. A technical mentor and forward-thinking leader who demonstrated strong capability in establishing advanced FEINT methodology and workflow, anticipating / analyzing / resolving technical and planning issues, and enjoyed interacting with team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. Key responsibilities: Develop, adopt strategy, concept and scripting solutions for RTL synthesis, timing path analysis and PPA analysis at the subsystem level as well as at the block level RTL designs to drive for continued improvement of QoR Develop, adopt ECO strategy, concept and scripting solutions for netlist and/or conformal assisted RTL ECO and LEC validations Develop, adopt strategy, concept and scripting solutions for RTL static design rule checks in collaboration with RTL design team and the corporate methodology team Manage FEINT regression process, create and improve FEINT workflow, processes, and quality metrics, to drive continuous improvement and positive changes Manage IP integration support with SoC team, coordinate resolution of IP integration issues with SoC teams Collaborate with project management and other team leads on FEINT deliverables to the project milestones and on quality metrics Preferred experience: A minimum of equivalent 10 years relevant experience in FEINT engineering. Proven understanding of RTL design, synthesis, and ECO principles Excellent knowledge with FE design tools such as Design/Fusion Compiler, Prime Time, Power Artist, Conformal, Formality, etc. Familiar with VCS/Verdi and SPG based (dynamic/static) verification environments Proficient with Verilog, C/C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile) Excellent skills with Unix/Linux environment Familiar with RTL coding techniques for improved PPA-measured QoR Familiar with RTL coding style for cleanness on design rule checks (LINT, CDC, RDC, etc.) Good understanding of gate level circuit design and physical level design concept and methodology Excellent communication skills (both written and oral) Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, a positive influencer on team morale and culture Prior technical management experience is a plus asset Academic credentials: Major in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field Masters Degree preferred Location: Bangalore India #LI-RR1 #LI-Linkedin

Role Description Share point developer with good experience in Pages and Workflow. Excellent Communication skills. Offshore resource who specializes in Sharepoint (i.e. Pages, workflow) development, etc.). 5-6 yrs of experience.

We are hiring on below Design Verification Engineer/ RTL Design Engineer - Engineer/Lead/Senior Lead . Please find the JD Details below - Please share us your details below in Table with your update resume. Job Descriptions : Please specify for which role your application is for - DV/RTL JD - Design Verification Engineer - Engineer/Lead/Senior Lead JD - RTL Design Engineer- Engineer/Lead/Senior Lead Qualifications: Bachelors degree in electrical engineering, Computer Engineering, or a related field (masters degree a plus) Experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Qualifications: Bachelor’s degree in electrical engineering, Computer Engineering, or a related field (Master's degree a plus) Experience in RTL design for ASICs/SoCs Proven experience in designing and verifying complex digital circuits Proficiency in Verilog or VHDL Experience with verification methodologies (e.g., UVM) Strong understanding of digital design concepts (combinational logic, sequential logic, state machines) Experience with SDC (Standard Delay Constraint) format for timing closure Experience with scripting languages (e.g., Python, Perl) is a plus Excellent communication, teamwork, and problem-solving skills Benefits: Competitive salary and benefits package Opportunity to work on cutting-edge technologies Collaborative and fast-paced work environment Potential for professional growth and development

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Verification of processor-based subsystem :(Running /debugging testcases). Skills Must have 5-8y exp Good verification skills (Verilog, system Verilog). Strong Knowledge of UVM methodology, with hands on experience of coding testbenches. with Good debug skills. AMBA (AXI, AHB, APB) Good to have protocol knowledge Exposure to Arm based SOC preferred but not a must Well versed with digital design fundamentals Scripting perl, tcl, Make, shell scripting Nice to have Experience with any other scripting language is a plus

Educational Qualification: Bachelor's degree in Electrical Engineering, Computer Science, or a related field. Work Experience : 2 to 4 years of industry experience . Role Description : Pixxel is widely considered to be one of the fastest-growing aerospace start-ups. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of earth observation. Come join our Avionics team and help us build future architectures that will continue to drive us forward in the field. Responsibilities Duties : Participate in next-generation system architecture a full system effort spanning mission planning, software, hardware, and other sub-systems. Develop custom IP for new features of the Pixxel camera payload and satellite bus. Understand the design requirements, establish the design infrastructure, support verification engineers, and test the correctness of the design. Realize high-reliability digital design targeting state-of-the-art Xilinx FPGAs. Participate in conceptual design studies of new spacecraft. Desirable Skills Certifications: Comfortable working with Xilinx Vivado Design Suite. Experience with external memories (SSD, FLASH, etc.); high-speed transceivers for protocols such as PCIe, SATA; and memory-mapped interfaces such as AXI, Wishbone, Avalon. Using advanced design methodologies like Hierarchical Design. Experience using lab equipment: high-speed oscilloscopes, logic and protocol analyzers, spectrum analyzers, etc. Experience with schematic design and board bring-up is a plus point. Would be great if you have A Bachelors Degree in EE, CS or CE (or a related field) with at least 2+ years of relevant experience or an Advanced Degree (Masters or PhD). Excellent knowledge of hardware description languages (Verilog/System Verilog/VHDL). Strong understanding of computer architecture and logic design, and serial interfaces SPI, I2C, LVDS, etc. Solid understanding of timing principles, including clock domain crossing and timing closure. Experience with FPGA tools (e.g Vivado) and HDL Simulation Tools (ModelSim). Strong debugging and analytical skills. Strong communication skills and the ability to work in a small team are a huge plus. Solid programming skills (C / C++, Python, Matlab). Candidate Acumen : A strong desire to work in an unstructured, high-growth, fast-paced start-up environment Benefits: Health insurance coverage Unlimited leaves flexible working hours Role-based remote work and work-from-home benefit Relocation assistance Professional Mental Wellness services Creche facility for primary caregivers (limited to India) Employee Stock Options for all hires

Role - Micro Loan Officer - Field Officer Reporting To Branch Manager 1. Starting business in a new village a. Village identification within the radius b. Feasibility study of the village based on demographics, activities and financial needs ofthe customers c. Assist the MC-IC in making the village approval 2. Sourcing of business a. Identification of customers and forming of Joint Liability Groups b. Filling up of the application form c. Verification of the residence and business of the customer d. KYC verification e. Pre-disbursement training f. Visiting potential customers in order to develop business 3. Disbursements a. Collection of KYC documents b. Assisting the MC-IC for disbursement activity completion c. Loan documentation 4. Collection of current dues a. Collect the collection sheets and stickers from MC-IC b. Group-wise collection as per scheduled time by following the process c. Deposit of collection money d. MERC entry 5. Collection of over dues a. Follow up with the customers with updated data report of assigned portfolio b. Collection of money as per process c. Depositing the money in bank d. MERC entry e. Assist the MC-IC in initiating action against the defaulters Eligibility:Interested in Sales and CollectionsGraduate / Post Graduate / 12 th / Diploma

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

SENIOR VERIFICATION ENGINEER- SV UVM SmartSoC is looking for smart and enterprisingDesign Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. SmartSoCs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM. Job Responsibilities- Build SV, SV UVM, OVM based environments. Work with many different networking and other protocols Desired Skills and Experience- 3 to 10 years of experience in IP verification Good experience in SV/ UVM based verification project. Good debug skills is a must. Experience in building components like Scoreboard, functional coverage & writing sequences using SV/UVM based Verification environment One of the following experiences is important: Experience in Video/Display domain in particular DP, oLDI, MIPI CSI/ DSI Experience in any one high speed protocol like USB3, PCIe, MIPI, Unipro etc Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USADelaware

Analog Layout Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech ESSENTIAL DUTIES AND RESPONSIBILITIES: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

SR. VERIFICATION ENGINEER – SOC VERIFICATION SmartSoC is looking for smart and enterprising SOC Verification experts to come and work on complex SOC Verification projects. This role will include- Technical execution of SOC Verification projects of complex ARM based SOCs Test Planning, Environment Architecture, SV-UVM environments Desired Skills and Experience- 3 – 10 years experience in Design Verification Excellent Communication and Presentation Skills Expert Knowledge in SOC Verification Expert at Verification – Coverage Driven Test Planning, Architecting Environments, Verification Flow Strong knowledge in System Verilog Knowledge in at least one methodology, OVM, UVM, VMM or RVM Very Good knowledge of protocols, at least one protocol of SATA, USB, Ethernet, PCIE Ability and desire to learn new methodologies, languages, protocols etc. is required Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida SwedenStockholm USATexas

RTL DESIGN LEAD ENGINEER The ideal candidate will be required to work on both IP development and integration into SoCs catering to various markets and tech nodes. The job will involve RTL design, front-end tools flow, and SoC integration/porting-related tasks. Desired Skills and Experience- 8+ years of Experience Engineering experience with exposure to front end ASIC tool flows Should be self-driven and independent in tracking and closing tasks with respective holders. In depth knowledge of AHB and bus infrastructures like matrix and fabrics Good understanding of ARM based SoC Architecture Exposure to ARM Cortex A/M integration or support Good understanding of SoC DV methodology Good experience in Low-Power design methodology Hands-on experience with ASIC tools Lint, CDC etc System Verilog/Verilog RTL coding Power aware RTL coding/design knowledge Understanding of Clock-Structures/Scheme Good Communication Skills Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USATexas

TECHNICAL LEAD – DFT SmartSoC is looking for a smart and enterprising leader with expert knowledge in DFT to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking. You will be responsible for leading and managing a team, client communication, and project execution. Job Responsibilities- Lead an internal DFT team, executing projects for an offshore client Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 7+ years of experience in DFT, mainly Scan Architecture, ATPG & MBIST Experience in planning scan chains, running scan insertion flow Experience in latest Cadence tool set Genus & Modus Experience in ATPG for Stuck@, TFT, IDDQ & Path delay faults with tough coverage targets Experience in MBIST architecture, generation and implementation Experience in AECQ100 requirement standard is a big plus Experience in working with a multi-site team is a big plus Experience in working on critical time-bound projects is a big plus Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

VERIFICATION LEAD – IP VERIFICATION SmartSoC is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution. This role will include- Lead an internal IP Verification team, executing projects for an offshore client Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects Guide team members in verifying IP’s and delivering zero bug IP’s Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 8 – 12 years experience in Design Verification Expert Knowledge in IP Verification Very strong knowledge in multiple protocols is highly desired, AMBA protocols and at least one high speed interface Must have expert knowledge in coverage driven test planning Must have expert knowledge in architecting configurable environments Must have very strong System Verilog and UVM background Must be able to lead the team technically in all aspects, must be able to drive multiple projects Past experience leading and managing teams highly desired Excellent Communication and Presentation Skills Ability and desire to learn new methodologies, languages, protocols etc. is required Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Pre-Silicon Validation Engineer Experience4 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Creating test environments, checker strategies, and test generators for validating embedded power management firmware in the SOC Communicating effectively, coordinating and working with firmware developers and SOC integration teams Potentially participating in the debug of failures in silicon and developing new testing strategies to detect these failures on pre-silicon models Mentoring junior members of the team in their development You should have 3-5 years of experience in the following areas: SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM Reading and interpreting technical specs and Register Transfer Level (RTL) code SW development skills (Unit Testing, Test Driven Development) Hands-on Debug Preferred Skills and Experience: Expertise in any of one domain like Audio, Performance, power management will be a huge plus 4+ years’ experience with writing validation plans and implement those validation plans Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul USATexas

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

1-3 years of experience in RTL DFT Verification (DFx). Good Understanding of JTAG IEEE-1149.1 and IJTAG IEEE P1687 standard. Understanding of using ICL and PDL files for verification and knows to create a testbench. Experience in JTAG RTL verification within any UVM. Able to debug simulation fails effectively utilizing debug tools like Synopsis Verdi. Basics of system Verilog, Basics of UVM, and preferably System Verilog assertions Scripting knowledge of TCL/Perl. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

We are seeking a highly skilled and motivated Mixed Signal Verification Engineer to join our team with 8+ years of expeirence. As a Mixed Signal Verification Engineer, you will be responsible for developing and implementing testbenches, checkers, and tests using System Verilog. You will also play a key role in creating and utilizing real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations. Ownership of Analog/Mixed designs at the chip and/or block level will be an important aspect of this role. Responsibilities: Develop and build Mixed-Signal testbenches, checkers, and tests using System Verilog. Create and utilize real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations. Take ownership of Analog/Mixed designs at the chip and/or block level, ensuring successful verification. Good Understandingof GLS simulations Collaborate with design engineers to understand design tradeoffs and create high-level models for design analysis. Perform behavioral modeling for verification simulations to validate the functionality and performance of mixed-signal designs. Debug and resolve issues arising from verification simulations and work closely with the design team to address any design-related concerns. Stay updated with the latest advancements in mixed-signal verification methodologies and tools, and drive continuous improvement initiatives. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). The primary focus of this role will be on Ethernet protocol verification, ranging from 100G to 800G standards. Key Responsibilities: Ethernet Protocol Expertise Demonstrate expertise in Ethernet standards, encompassing 100G to 800G. In-depth knowledge of specific standards, including 100GE (cl45, cl49, CL82, CL91, CL119), 200GE, 400GE (cl161, cl116), and 800GE (802.df/800ETA). Proficiency in PTP 1588 standard and various Ethernet frame types. Competence in packet insertion/extraction techniques. (Additional knowledge of AXI protocol would be considered an advantage) UVM/SV Proficiency Showcase strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM). Architectural Skills Proven ability to architect, build, and maintain a comprehensive verification stack. Test Development Extensive experience in developing a set of regression tests for verification purposes. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). Excellent understanding of Ethernet protocols, ranging from 100G to 800G. Proficiency in PTP 1588 standard and various Ethernet frame types. Experience with packet insertion/extraction techniques. Knowledge of AXI protocol (preferred). Proven ability to architect, build, and maintain verification stacks. Demonstrated expertise in developing a comprehensive set of regression tests. If you are a talented Design Verification Engineer with a passion for ensuring the reliability and performance of cutting-edge technology, we encourage you to apply. Join our dynamic team and contribute to the advancement of next-generation technologies. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Candidates need to have good experience in Tessant tools Candidates need to have good experience in ATPG pattern generation and simulation(both timing and no timing) Candidates need to have good experience in Scan insertion Experience should be more than 6+ years Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience Level: Over 4 years Location: Bangalore Skills: Proficiency in SystemC, C++, and SV/Verilog, coupled with hands-on coding experience in these languages. Strong aptitude for debugging and effective communication. Familiarity with scripting languages (desirable). Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Emulation Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: should have emulation experience working on available platforms such as; Palladium, Veloce, or Zebu, as well as experience with compilation, debug, performance, and throughput tuning Experience using Verilog, VHDL design Experience with C/C++ and System Verilog, UVM verification environments Experience writing scripts using Perl, Python, Makefile Debugging experience using tools like waveform, Verdi, Simvision Strong communication skills and ability to work as a team Description You’ll support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches). You’ll be bringing up SOCs on emulation, root causing SoC/Processor test fails and emulator environment issues. – We are in constant collaboration with Design, DV, Power, Silicon Validation, Performance, and Software teams. – Your strong design, debug, communication, and teamwork skills will be essential. – You will also work with leading emulation vendors to debug issues. Skills Experience Zebu Verilog, Python Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore USADelaware USATexas

We are seeking a highly skilled and experienced Lead Verification Engineer with expertise in USB/LPDDR and a strong knowledge of Cadence VIP. The ideal candidate will have a deep understanding of low-power design and verification techniques. Responsibilities: Develop and execute comprehensive verification strategies for USB/LPDDR subsystem designs, considering low-power design requirements. Collaborate with cross-functional teams to define verification goals and ensure alignment with project objectives. Design and implement reusable, scalable, and efficient verification testbenches using SystemVerilog/UVM or C based . Leverage Cadence VIP and other verification IPs to accelerate the verification process. Low-Power Design VerificationApply expertise in low-power design and verification techniques to ensure accurate and reliable verification of power management features, including power states, power domains, and power-aware verification methodologies. : Extensive experience (8+ years) in verification. Strong knowledge of Cadence VIP and verification methodologies (SystemVerilog/UVM). Proficiency in low-power design techniques and power-aware verification methodologies. Hands-on experience with industry-standard simulation and verification tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Questa). Solid understanding of verification languages (SystemVerilog, VHDL) and scripting languages (Perl, Python, TCL). Familiarity with industry standards and protocols related to USB (USB 2.0, USB 3.x) and LPDDR (LPDDR4, LPDDR5). Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore