2286 Verilog Jobs - Page 9

Job Title: RTL Design Engineer Experience: 3–5 Years Company: eInfochips (An Arrow Electronics Company) Location: Ahmedabad/ Noida Job Type: Full-Time Job Description: eInfochips is looking for talented RTL Design Engineers with 3–5 years of experience in digital design. You will be working on IP and SoC-level RTL development for leading semiconductor clients across domains like Automotive, Consumer, Industrial, and AI. Key Responsibilities: RTL design using Verilog/SystemVerilog for IP and SoC subsystems Perform synthesis, linting, CDC/RDC analysis Interface with verification, physical design, and architecture teams Support SoC integration and debug Ensure design quality and timing closure Required Skills: 2+ years of hands-on RTL design experience Strong in digital design concepts (FSMs, pipelining, FIFOs) Proficient with tools like Synopsys Design Compiler, SpyGlass, VCS Experience with standard protocols (AXI, AHB, APB) Basic scripting skills (TCL, Perl, Python) How to Apply: 📩 Send your resume to: Nshalini.singh@einfochips.com

JOB NAME : AMS Verification Engineer (Mandatory to have AMS verification with UVM test : As per market : Hyderabad Please Note : it will be virtual interview, WFO initially later depends on the project and project manager, General Description : The position involves design verification of next generation IPs /SoCs with emphasis on verifying and signing off performance and power along with functionality by developing the needed RNM models . This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS . Candidate Will Require Close Interactions With Design, SoC , Validation, Synthesis PD Teams For Design Convergence. Candidate Must Be Able To Take Ownership Of IP/Block/SS To work in AMS Verification domain with UVM test batch relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Experience working on AMS Verification on multiple SOCs or sub-systems. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations. Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. Develop and execute top-level test cases, self-checking test benches and regressions suites. Developing and validating high-performance behavior models. Verifying of block-level and chip-level functionality and performance. Team player with good communication skills and previous experience in delivering solutions for a multi-national client. Tool suites : Predominantly analog (Cadence Virtuoso). SPICE simulator experience. Fluent with Cadence-based flowCreate schematics, Simulator/Netlist options etc.. Ability to extract simulation results, capture in a document and present to the team for peer review. Supporting silicon evaluation and comparing measurement results with simulations. UVM and assertion knowledge would be an Level : 8-12 years in Industry(3+yrs Requirements : Bachelor or Masters degree in Electrical and/or Computer Qualifications : Proficient in at least one of the following languages : Verilog, System Verilog, Verilog AMS. Strong understanding of analog circuits, digital design processes, and top-level integration. Basic knowledge of PMIC and DC-DC converters. Excellent simulation debugging skills, with the ability to analyze waveforms and identify issues in schematics, models, or RTL. Proficient in Unix environment and shell scripting, with a basic understanding of Qualifications : Mentoring skills. Exceptional problem-solving skills. Good written and oral communication Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs). Employee Stock Purchase Plan (ESPP). Insurance plans with Outpatient cover. National Pension Scheme (NPS). Flexible work policy. Childcare support. (ref:hirist.tech)

Selected Intern’s Day-to-day Responsibilities Include Working on various electronics projects and ensuring timely completion Applying knowledge or demonstrating interest in fields such as embedded systems, Internet of Things (IoT), robotics, FPGA, Verilog, PCB designing, and artificial intelligence/machine learning (AI/ML) Being available to work from the office as required Criteria - The applicant can work from Home only if he/she can purchase the project materials by themselves; otherwise, they have to work from the office. Candidates from any location other than Silvassa may apply, but only if they are willing to purchase the components on their own Note: The cost of components/project materials will be reimbursed after the successful delivery of the correct project About Company: LearnElectronics is an educational platform where all students can learn and practice electronics. The site focuses on basic electronics, the Internet of Things (IoT), and embedded systems for now and provides DIY projects and free courses.

As a Hardware Architect at Kinara, a Bay Area-based venture backed company, you will play a crucial role in developing game-changing AI solutions that revolutionize what people and businesses can achieve. Your primary responsibility will be to develop architecture models for AI chips, ensuring that they accurately reflect design specifications and requirements. Collaborating with cross-functional teams, including hardware and software departments, you will work towards cohesive and efficient chip design and functionality. In addition to architecture modeling, you will conduct in-depth performance analysis to identify and resolve bottlenecks in AI chip designs. Using simulation and analytical methods, you will predict and enhance chip performance while working closely with software teams to validate performance models with real-world applications and workloads. Furthermore, you will perform detailed power analysis to ensure that AI chips meet stringent power consumption targets. To be successful in this role, you should hold a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, along with a minimum of 8 years of experience in hardware architecture/design of silicon chips. You must possess a strong understanding of computer architecture principles and AI chip design, as well as proficiency in C/C++/Verilog. Preferred qualifications for this position include excellent analytical and problem-solving skills, strong communication and teamwork abilities, the ability to work in a fast-paced, collaborative environment, and a detail-oriented approach with a focus on delivering high-quality results. At Kinara, we have an innovative environment that encourages technology experts to tackle exciting challenges while sharing responsibilities and valuing every point of view. If you are passionate about making a mark in the field of AI hardware architecture and are looking for a dynamic team to join, we look forward to reviewing your application. Join us at Kinara and be a part of creating a smarter, safer, and more enjoyable world through cutting-edge edge AI solutions.,

As a Senior SoC/CPU Verification Engineer at NVIDIA, you will have the opportunity to work on verifying the world's most powerful CPUs/Socs with AI capabilities for applications such as self-driving cars, gaming consoles, and other automated machines. NVIDIA, as a learning machine, constantly seeks new opportunities that are challenging, unique, and have a significant impact on the world. Join our diverse team and contribute to amplifying human creativity and intelligence. In this role, you will collaborate with a team of exceptional engineers to verify micro-architecture and architecture features at various levels, including unit, subsystem, and full chip testbenches. You will also work closely with CPU architects to ensure verifiable designs and contribute to full-stack development, from verifying sequences at the software simulator level to implementing end-to-end sequences on silicon with a complete software stack. To excel in this position, you should have a strong foundation in verification principles and the ability to transition between working on software simulators and silicon. Proficiency in CPU architecture, particularly ARM knowledge, Verilog, System Verilog, and robust debugging skills are essential. A minimum of 5 years of experience in Computer Science, Electronics Engineering, or related fields is required, along with a Bachelor's or Master's degree. To distinguish yourself as a standout candidate, showcase your experience in verifying various aspects of CPU unit/microarchitecture, involvement in complex coverage-driven verification projects, and a track record of collaborating with diverse multi-functional teams across different locations. If you are looking to be part of a team that pushes the boundaries of what is achievable today and shapes the future of computing, consider joining NVIDIA as a Senior SoC/CPU Verification Engineer. Your contributions will play a key role in defining the platform for the next generation of computing technology.,

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and integrating them into full-chip designs. Your expertise in lower technology nodes, physical layout techniques, and verification processes will be crucial for success in this role. You will collaborate with circuit design teams to optimize layout quality and performance, ensuring that layouts meet design matching and parasitic constraints. Working with advanced nodes like 7nm, 16nm, and 28nm, you will play a key role in advancing the company's cutting-edge projects. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Perform and resolve LVS/DRC violations independently - Collaborate with circuit design teams to optimize layout quality and performance - Ensure layouts meet design matching and parasitic constraints - Work with advanced nodes like 7nm, 16nm, and 28nm Required Skills: - 3+ years of relevant Analog Layout experience - Proficiency in LVS/DRC checks and EDA tools - Experience with lower technology nodes (3nm, 5nm, 7nm, 10nm, 16nm, 28nm, etc.) - Good understanding of layout matching, parasitic extraction, and floor planning - Strong verbal and written communication skills - Ability to work independently and within cross-functional teams In this role, you will be a Circuit Design Engineer at ARF Design, working on the design of building blocks used in high-speed IPs such as DDR/LPDDR/HBM/UCIe/MIPI/PCIe. You will derive circuit block-level specifications from top-level specifications and perform optimized transistor-level design of analog and custom digital blocks. Running SPICE simulations to meet detailed specifications and guiding layout design for best performance, matching, and power delivery will be part of your responsibilities. You will also characterize design performance across PVT + mismatch corners and conduct design reviews at various phases/maturity of the design. Qualifications: - BE/M-Tech in Electrical & Electronics - Strong fundamentals in RLC circuits, CMOS devices, and digital design concepts (e.g., counters, FSMs) - Experience with custom design environments (e.g., Cadence Virtuoso, Synopsys Custom Design Family) and SPICE simulators - Collaborative mindset with a positive attitude If you have 3+ years of experience and possess the required skills, please share your updated resume [Name_Post_Exp] to divyas@arf-desgn.com. This is a full-time, permanent position located in person at Bhubaneswar and Ranchi.,

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Developing best-in-class architecture for Analog Mixed Signal IPs and high-speed parallel PHY interface solutions for next generation NAND flash memory controllers in advanced CMOS technology nodes. Interact with cross-functional teams to define requirements/specs, conceive the optimal solution by evaluating architectures, drive implementation, closely work with layout designers in guiding and reviewing the layouts, ensure timely and high-quality deliverables, extend SOC integration support and review and provide support for post-silicon activities from IP characterization to yield improvement and RMA. Provide good technical leadership in problem solving, planning and mentoring junior and senior engineers. Propose innovative design solutions and design methodologies. Fostering innovation culture and developing efficient processes by adopting state-of-the-art technologies. Qualifications Must have Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Working experience (20+ years) in IO including 5+ years as a project leader Should have architected and lead high speed interface design solutions from specification through Silicon debug and characterization Should have hands-on experience in TX and RX design architectures for high speed applications such as DDR4/DDR5/LPDDR4/LPDDR5 along with timing budget analysis. Should be experienced in high speed design architectures such as SERDES, Equalization schemes Should have hands-on experience in IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration, HV tolerant and Fail-safe IOs, Crystal oscillator etc. Should have extensive experience in ESD circuits design, Associated ESD guidelines and recommendations in different process nodes, IO and SOC level ESD review and signoff Experience in full custom high speed data path design such as DDR PHY will be of advantage. Conversant with tools such as Cadence Virtuoso/Synopsys custom compiler/Hspice/Spectre/Finesim including statistical simulation methodologies Experience in Mixed-mode simulation and analog/digital co-simulation will be of added advantage. Experience in creating EDA model such as Verilog model, Liberty etc will be of added advantage. Should have deep understanding and working knowledge of CMOS process including FINFET technologies such as 16nm/7nm/5nm and the associated DFM issues. Very analytical in nature and able to work in a multi-disciplinary environment Creative, out-of-the-box thinker with a high level of personal involvement Strong theoretical background with a pragmatic approach. Good verbal and written communication skills and experience working with different geographies. Good mentoring, documentation and presentation skills Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Role & responsibilities Strong verification expertise using Verilog and SystemVerilog, with solid understanding of UVM methodology and hands-on experience writing test-benches. Proficient in debugging testcases and verifying processor-based subsystems. Knowledge of AMBA protocols (AXI, AHB, APB) is a plus. Exposure to Arm-based SoCs and strong grasp of digital design fundamentals. Experience with scripting in Perl, TCL, Make, and Shell.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. Our Silicon Design & Verification business leads the industry in enabling customers to design and verify advanced silicon chips—faster and with more reliability. We develop the next-generation processes and models that optimize chips for power, cost, and performance, shaving months off project schedules for our global clientele. We believe in fostering an inclusive and diverse environment where every voice is valued and innovation thrives. You Are: You are a passionate and experienced Analog/Mixed-Signal (A&MS) Circuit Design Engineer with a track record of excellence in high-speed physical interface development. With a deep foundation in CMOS circuit design, device physics, and nanometer technologies, you thrive on solving complex challenges at the intersection of analog and digital domains. You are energized by working on industry-leading projects and are adept at architecting, designing, and validating advanced circuits such as transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends. Your expertise allows you to optimize for performance, area, and power, and you are comfortable with layout considerations and parasitic optimizations. You value diversity and inclusion, recognizing the strength that comes from varied perspectives and backgrounds. You are ready to contribute to a culture of innovation, respect, and excellence—helping Synopsys remain at the forefront of the smart everything revolution. What You’ll Be Doing: Designing and developing high-speed analog and mixed-signal full-custom circuit macros, including transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends for PHY IPs in advanced CMOS technologies (planar and finFET). Analyzing and implementing various analog circuit techniques to optimize dynamic/static power, enhance performance, and reduce silicon area. Collaborating with global teams to define micro-architectures from specifications and create robust simulation environments for design verification. Performing transistor-level circuit design, simulation, and troubleshooting in nanometer processes, with a focus on reliability and manufacturability. Working closely with layout engineers to optimize parasitics, ensure design closure, and address layout-dependent effects. Participating in design reviews, providing technical guidance, and mentoring junior engineers within a high-performing, diverse team. Adopting and developing automation and scripting to streamline design and verification flows, leveraging languages such as Verilog-A and others as needed. The Impact You Will Have: Advance the state-of-the-art in high-speed PHY IP development, contributing directly to next-generation technology in AI, IoT, 5G, and automotive industries. Enable Synopsys customers to achieve faster time-to-market with optimized, reliable, and high-performance silicon solutions. Drive innovation in low-power and high-speed circuit design, helping customers meet stringent power and area targets. Enhance Synopsys’ reputation as a global leader in silicon design and verification through technical excellence and customer success. Mentor and elevate the skills of team members, fostering a collaborative and growth-oriented culture. Contribute to a diverse and inclusive workplace, ensuring a wide range of perspectives and ideas inform our solutions. What You’ll Need: BE + 5 years or MTech + 4 years of relevant experience in Electrical/Electronics/VLSI Engineering or closely related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron/nanometer methodologies. Hands-on experience in analog transistor-level circuit design for high-speed applications (Multi-Gbps, PAM4 SERDES architectures). Proficiency in SPICE simulations, reliability analysis, and optimizing for layout parasitics. Ability to micro-architect circuits from specifications, set up verification environments, and debug complex analog/mixed-signal circuits. Basic proficiency with automation/scripting languages and familiarity with Verilog-A is a plus. Experience collaborating with cross-site, multicultural teams and strong documentation skills. Who You Are: Innovative thinker with a problem-solving mindset and a passion for continuous learning. Collaborative team player who values diversity, inclusion, and open communication. Detail-oriented, quality-focused, and committed to delivering results on time. Strong interpersonal and mentoring skills, able to guide and support less experienced team members. Adaptable and resilient, comfortable working in a fast-paced, dynamic environment. The Team You’ll Be A Part Of: You will join a dynamic, high-performing team dedicated to the design and development of high-speed physical interfaces for advanced semiconductor products. Our team is composed of talented engineers with deep expertise in analog and mixed-signal design, working collaboratively across multiple sites worldwide. We value innovation, knowledge-sharing, and a culture of mutual respect, enabling every team member to grow and contribute to industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

. Location: Bangalore/Kolkata Experience: 3+ years Opportunity Snapshot: We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills. You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems. You will have a significant opportunity to interact with system design teams across geographies. Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture. Thus, you set your own limits for learning, achievements and rewards. Responsibilities: Define and architect high-performance blocks for the latest, most advanced networking ASICs Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power Collaborate with the verification team in the development of the testplan and assist in debugging test failures Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes Required Skills: 3+ years of ASIC design experience Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus Knowledge of high performance memory subsystems Knowledge of multi-domain clock synchronization and high-speed serial interfaces Strong problem solving and ASIC debugging skills Excellent written and verbal communications skills MSEE or BSEE is required WHERE WILL YOU DO YOUR BEST WORK

Candidate will be responsible for building/maintaining highlyconfigurable and reusable IO Subsystems (Note: An IO Subsystem is alogic IP that processes the IO Pads/IO Ring information and requiredlogic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner) Job Description In your new role you will: Candidate will be responsible for building/maintaining highly configurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes the IO Pads/IO Ring information and required logic to allow multiple on-chip peripherals to share the same IOs in a configurable manner) Candidate will be responsible for RTL design for integration of IO pads into SoC, building the required multiplexing logic and necessary power control signals integration. Strong fundamentals in DFT/Fault-grading and/or hands on experience. Sound & Practical Written and Verbal Communication Skills. Your Profile You are best equipped for this task if you have: Must have worked in ASIC Design flow, with ASIC experience of upto 5years. Must be strong in scripting using Perl/Python Must be familiar with RTL design for for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

NVIDIA has been transforming computer graphics, PC Gaming, and accelerated computing for more than 25 years. It s a unique legacy of innovation that s motivated by great technology and amazing people. Today, we are tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what s never been done before takes vision, innovation, and the world s best talent. As an NVIDIAN, you ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. The HWPM Team at NVIDIA is seeking an excellent ASIC Senior Verification Engineer to drive high-quality, robust verification of system-level IP across unit, subsystem, and SoC levels. This role is ideal for someone passionate about ground-breaking hardware, sophisticated verification methodologies, and crafting the future of computing. Come join the team and see how you can make a lasting impact on the world. What You ll Be Doing: Play a key role in the Hardware Performance Monitor (HWPM) team, helping define and develop system-level RTL and performance measurement methodologies for NVIDIA s industry-leading SoCs and GPUs. Develop comprehensive test plans, implement tests, and apply robust verification strategies to validate microarchitecture and design functionality. Design and implement reusable, scalable testbenches and testbench components using System Verilog and UVM. Collaborate with architects, RTL designers, and software engineers to drive feature completeness, performance visibility, and verification closure. What we need to see: M. Tech. (or equivalent) in VLSI or Electronics Engineering with 2+ years of relevant industry experience OR B. Tech with 4+ years of experience in a similar domain Proven experience in unit, sub-system or SoC Level Verification Hands-on expertise in building and maintaining testbench environments for both unit and system-level verification Proficiency in Python or industry-standard scripting languages for automation and test development Strong debugging and analytical skills Familiarity with industry-standard design and verification tools like VCS, Xcelium, etc. Solid understanding of RTL Design Principles and Verilog Experience with UVM (Universal Verification Methodology) is a strong plus Excellent communication & collaboration skills, with ability to work effectively across cross-functional teams Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. Also, we have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our outstanding engineering teams are growing fast. If you are creative, curious, and motivated with a real passion for technology, we want to hear from you! #LI-Hybrid

We are looking for a seasoned Senior Design Verification Engineer with 8+ years of experience in verifying complex digital IPs and SoCs. The ideal candidate will have strong expertise in developing UVM-based verification environments and driving functional coverage closure. Key Responsibilities: Develop and maintain constrained-random and directed testbenches using System Verilog/UVM Define verification plans and test strategies based on specifications Write test cases, checkers, and functional coverage models Perform RTL simulations, debug failures, and ensure coverage closure Collaborate with RTL, DV, and firmware teams across verification lifecycle Support gate-level simulation, regression management, and post-silicon bring-up Requirements : 8+ years of hands-on experience in digital design verification Expertise in System Verilog, UVM, and verification methodology Strong debugging skills using simulators like VCS, Questa, or Incisive Good understanding of protocols like AMBA (AXI/AHB/APB), PCIe, Ethernet, etc. Experience with coverage tools, version control, and regression systems Strong communication, collaboration, and documentation skills

NVIDIA has been redefining computer graphics, PC Gaming, and accelerated computing for more than 25 years. It s a unique legacy of innovation that s motivated by phenomenal technology and outstanding people. Today, we are tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what s never been done before takes vision, innovation, and the world s best talent. As an NVIDIAN, you ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. The HWPM Team at NVIDIA is seeking an excellent ASIC Verification Engineer to drive high-quality, robust verification of system-level IP across unit, subsystem, and SoC levels. This role is ideal for someone passionate about ground-breaking hardware, sophisticated verification methodologies, and crafting the future of computing. Come join the team and see how you can make a lasting impact on the world. What You ll Be Doing: Play a key role in the Hardware Performance Monitor (HWPM) team, helping define and develop system-level RTL and performance measurement methodologies for NVIDIA s industry-leading SoCs and GPUs. Develop comprehensive test plans, implement tests, and apply robust verification strategies to validate microarchitecture and design functionality. Design and implement reusable, scalable testbenches and testbench components using System Verilog and UVM. Collaborate with architects, RTL designers, and software engineers to drive feature completeness, performance visibility, and verification closure. What we need to see: M. Tech. (or equivalent) in VLSI or Electronics Engineering OR B. Tech with 2+ years of experience in a similar domain Hands-on experience in unit and/or system level verification Ability to contribute to testbench development and maintenance, preferably using System Verilog and standard methodologies Proficiency in Python or industry-standard scripting languages for automation and test development Proven debugging fundamentals ability to read waveforms, analyze logs, and isolate issues effectively Familiarity with industry-standard tools such as VCS, Xcelium, Verdi, or similar simulation/debug environments Good understanding of RTL design concepts and experience working with Verilog or SystemVerilog Experience with UVM (Universal Verification Methodology) is a strong plus Clear communication skills and collaborative attitude, with ability to work alongside design, DV, and automation teams Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. Also, e have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our outstanding engineering teams are growing fast. If you are creative, curious, and motivated with a real passion for technology, we want to hear from you! #LI-Hybrid

NVIDIA System-On-Chip (SOC) group is hiring for a Design Engineer! The complexity of the chips we build has increased manifold over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand. We are looking for a top ASIC Design Engineer. In this role, you should have real passion for RTL design implementation and methodologies that enable high quality system-level IP design. What youll be doing: Be an integral part of the team defining and developing system-level RTL and methodologies to measure performance on the industrys leading GPUs/SOCs. Design and implement RTL features - work through the entire design cycle for SOC. Run and debug RTL checks to ensure design quality (e. g. CDC, RDC, Lint, Synthesis, Logic-Equivalence and more) Define, develop, and automate flows and methodologies to efficiently build and support a system-level IP Work with architects, designers, verification and SW engineers to accomplish your tasks. What we need to see: B. Tech or M. Tech in Electronics or Computer Engineering. 2+ years of relevant industry experience. Experience in RTL design (Verilog), System-On-Chip design/implementation flow, and design automation. Good understanding of SOC architecture (e. g. , CDC, multiple-power domains, performance analysis, latency, and data flow). Strong coding skills in Perl, Python or other industry-standard scripting languages. Excellent debugging and analytical skills. Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB). Exposure to AI tools is a plus Great communication and collaboration skills to interact within the team and with cross functional teams NVIDIA is widely considered one of the technology world s most desirable employers. We employ some of the most forward-thinking and innovative people in the world. Are you passionate about joining our life work to amplify human imagination and intelligenceIf you are creative, collaborative, and have real passion for design, methodology, and automation, we want to hear from you! #LI-Hybrid

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI the next era of computing. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can address, and that matter to the world. This is our life s work, to amplify human creativity and intelligence. As an engineer of our Software Quality Assurance (QA) team, you will orchestrate the process of Software Quality for our CAD tools and flows. We develop and support flows for all of NVIDIAs semiconductor products. In addition, the CAD group also develops in-house tools in the area of Design for Test (DFT) using C++, Python, and TCL. You will work on infrastructure and software used to test our complex semiconductor devices. Below are some of the CAD teams activities. We are a diverse team, looking for someone who is not afraid of a challenge. If this is you, come join us today. What you will be doing: Providing hardware, software, and lab support for testing and validation processes. Architecting highly automated and customizable Software Quality processes for design flows using software engineering with modular design and object-oriented techniques. Crafting feature test plans, identifying, and writing test cases based on user requirements, and providing automation of testing. Maintaining regression testing frameworks and developing test reporting mechanisms Performing code reviews, static analysis, and dynamic testing. Continuously delivering high-quality, bug-free Software Applications. Working closely with our diverse team members on flows to provide DFT and methodologies for industry-leading chip designs. Supporting the development of tools using C++/Python/TCL. Working cross-functionally with DFT Methodology, Implementation, and design teams with important DFT tools support. What we need to see: A BS or MS in Electrical Engineering, Computer Science, or Computer Engineering with at least 4+ years of relevant work experience in Software QA role. Knowledge of different software testing techniques, code reviews, code coverage, unit and flow testing, use case testing, random, white, and black box testing. Experience with test management tools such as TestRail or Zephyr. Familiarity with CI/CD tools like Jenkins and GitLab. Strong GenAI, LLM, AI Code Generation skills desirable. Good software design, algorithms, programming and scripting skills in Python, Tcl, or C++ desired. Experience with defect tracking tools such as JIRA. Experience in providing lab software and hardware Ways to stand out from the crowd: Knowledge or experience with DFT is a plus. Knowledge of BDD processes is desirable. Verilog and ASIC design principles, including knowledge of logic cells is a plus. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If youre creative and autonomous, we want to hear from you! #LI-Hybrid

NVIDIA System-On-Chip (SOC) group is hiring for a Senior Design Engineer! The complexity of the chips we build has increased manifold over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand. We are looking for a top ASIC Design Engineer. In this role, you should have real passion for RTL design implementation and methodologies that enable high quality system-level IP design. What youll be doing: Be an integral part of the team defining and developing system-level RTL and methodologies to measure performance on the industrys leading GPUs/SOCs. Design and implement RTL features - work through the entire design cycle for SOC. Run and debug RTL checks to ensure design quality (e. g. CDC, RDC, Lint, Synthesis, Logic-Equivalence and more) Define, develop, and automate flows and methodologies to efficiently build and support a system-level IP Work with architects, designers, verification and SW engineers to accomplish your tasks. What we need to see: B. Tech or M. Tech in Electronics or Computer Engineering. 5+ years of relevant industry experience. Experience in RTL design (Verilog), System-On-Chip design/implementation flow, and design automation. Good understanding of SOC architecture (e. g. , CDC, multiple-power domains, performance analysis, latency, and data flow). Strong coding skills in Perl, Python or other industry-standard scripting languages. Excellent debugging and analytical skills. Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB). Great communication and collaboration skills to interact within the team and with cross functional teams. Exposure to AI tools is a plus NVIDIA is widely considered one of the technology world s most desirable employers. We employ some of the most forward-thinking and innovative people in the world. Are you passionate about joining our life s work to amplify human imagination and intelligenceIf you are creative, collaborative, and have real passion for design, methodology, and automation, we want to hear from you! #LI-Hybrid

We are seeking a highly skilled Senior Analog Design Engineer with 6+ years of experience in designing, simulating, and validating analog and mixed-signal circuits. The ideal candidate should have hands-on expertise across the full custom design flow, from specification to silicon validation. Key Responsibilities: Design and develop analog/mixed-signal IPs such as ADCs, DACs, LDOs, Bandgaps, PLLs, Op-Amps, etc. Perform schematic entry, simulations (pre-layout/post-layout), and layout supervision. Drive transistor-level design using industry-standard tools (Cadence/Synopsys). Lead block-level design reviews, documentation, and verification. Collaborate with layout, digital, and validation teams across the project lifecycle. Support silicon bring-up, debug, and characterization. Requirements: 6+ years of hands-on analog IC design experience in CMOS processes (28nm/65nm/180nm, etc.) Strong knowledge of analog fundamentals and design trade-offs. Experience with simulation tools like Spectre, HSPICE, and Monte Carlo analysis. Proven tape-out and silicon success experience. Good communication and team leadership skills. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers.Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLLAdditional responsibilities:logic (RTL) design, timing closure, CDC analysis etc.Understand and Design Power efficient logic.Agile project planning and execution.RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. Collaborate with cross-functional teams to achieve design goals. Close the design to meet timing, power, and area requirements. Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Master's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure.

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to handle the challenging problems in future technologies and designs. We are also looking for candidates with Strong C/C++background to lead our leading-edge algorithmswithin our EDA solutions to increase our design team’s productivity and chip quality and performance. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions. Individuals who are chosen to become a part of our world class development teams will be helping advance IBM’s leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMerCome THINK with us! Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4+ years of IT experience Strong C/C++programming skills in a Unix/Linux environment is a must. VLSI knowledge, Knowledge in front end linting tools and checkers and RTL Checkers. Great scripting skills – Perl / Python/Shell Proven problem-solving skills and the ability to work in a team environment are a must Preferred technical and professional experience RTL Lint Checkers , Front end verification flow, VLSI knowledge, VHDL/Verilog, computer architecture

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to handle the challenging problems in future technologies and designs. We are also looking for candidates with Strong C/C++background to lead our leading-edge algorithmswithin our EDA solutions to increase our design team’s productivity and chip quality and performance. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions. Individuals who are chosen to become a part of our world class development teams will be helping advance IBM’s leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMerCome THINK with us! Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4+ years of IT experience Strong C/C++programming skills in a Unix/Linux environment is a must. VLSI knowledge, Knowledge in front end simulation tool development isadditional plus. Great scripting skills – Perl / Python/Shell Proven problem-solving skills and the ability to work in a team environment are a must Preferred technical and professional experience Simulation tool development, Front end verification , VLSI knowledge, VHDL/Verilog, computer architecture

Your Role and Responsibilities Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. . Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Technical and Professional Expertise 4 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications,processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Nice to haves -Knowledge of verification principles and coverage. -Knowledge of test generation tools and working with ISA reference model. -Experience with translating ISA specifications to testplan. -Understanding of Agile development processes. -Experience with DevOps design methodologies and tools. Preferred technical and professional experience Work with Hiring Manager to ID up to 3 bullets max (encouraging then to focus on required skills) Advanced Verification Techniques: Familiarity with advanced verification techniques such as RAS verification is a plus Experience with Hardware Description Languages (HDLs): Proficiency in hardware description languages like Verilog and VHDL, enabling seamless collaboration with design teams and enhancing verification effectiveness. Experience in System-Level Verification: Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design abstraction.

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. . Required education Master's Degree Preferred education High School Diploma/GED Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design,

Your Role and Responsibilities Lead the unit level pre-silicon functional & performance verification the Instruction Sequencing Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for ISU which covers the Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Technical and Professional Expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of Instruction Dispatch verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Nice to haves - Knowledge of instruction dispatch and Arithmetic units. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Knowledge of verification principles and coverage. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.