1574 Verilog Jobs - Page 9

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for an experience Verification Staff/Architect Engineer, who will be responsible Verification of next generation Infrastructure IPs (DDRSS, Memory Controllers etc.) which goes into System-on-chip (SoC) for smartphones, tablets and other product categories. In this position you will be expected to plan and implement IP/Cluster/Formal verification flows for the Infra IPs. Also expected to coordinate with different Design and SOC teams throughout the IP development cycle. Job responsibilities include Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure Debug of regression signatures and identifying bug fixes Responsible for Quality sign off and required documentation Developing/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan) Debug and root cause post silicon issues in collaboration with Design, SW and test teams Work with SoC level performance modeling team on latency, bandwidth analysis " Required skillset include Strong debugging, Analytical and problem-solving skills Expertise on UVM based verification Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Communication and collaboration skills to work with a large world-wide design organization " Desired skillset includes Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse Experience in verifying designs meeting Automotive Safety Integrity Levels (ASIL) Proficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Qualification : Bachelor/Masters Degree in Electronics & Communication / Micro Electronics 9 -12 years of experience Experience with UVM and ARM Bus protocols. tor, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Adreno GPU has been the industry leading mobile graphics solution and has been the dominating GPU in todays smart phone market. Our power efficient GPU solution is fundamental to enable the exciting new markets like VR, IoT, AI, drone, autonomous driving etc. We are looking for talented Graphics System engineers to create world class GPU products to enable high performance graphics and compute with low power consumption. As a member of our Graphics System team, you will help create the simulator of our next generation graphics core for mobile devices. In this position, you will be responsible for development of the GPU architecture design using advanced modeling methodologies. You are expected to understand the design and implementation, define the development scope, develop the algorithm for some functional blocks, and verify the correctness of the design. You will be working with architects, designers, driver, and compiler teams to accomplish your tasks. Develop bitwise accurate functional models (C-model) (by using C/C++ etc.) to simulate our new architectures and solutions Develop solid test suites and perform functional verification & validation with the C-Model and RTL simulation Perform conformance tests, stress & random tests and stabilize GPUs & Compute systems Additional Additional Critical "Must Have" skills/experience for role Good understanding of modern 3D graphics pipeline. Programming experience in graphics or compute using API like DirectX, OpenGL OpenCL, Vulkan. Programming experience in modeling using C++ and good understanding of computer/GPU architecture and pipeline. Debugging and problem-solving skills. Ability to write clean, professional & maintainable code in C++. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. Preferred skills/experience for role Knowledge on graphics/ray-tracing/compute architecture & pipeline (e.g., DirectX, OpenGL, OpenCL, Vulkan, etc.) C/C++/Perl/Python programming language Good communication skills and ability & desire to work as a team player. SystemC and TLM experience are desirable Agile development methodology experience is preferable Graphics & compute driver or compiler experience is a plus Verilog/Vera/System Verilog experience is a plus Required : Minimum Qualifications - Bachelor's or higher degree in Computer Engineering, Computer Science, Electrical Engineering, or related field. 8+ years Systems Engineering or related work experience Preferred Qualifications - Master's or higher degree in Computer Engineering or Computer Science. 7+ years Systems Engineering or related work experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle. Roles And Responsibilities Performance exploration. Explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional verification strategy. Performance verification support. Help verify that the RTL design meets the performance goals. Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and po Preferred Qualifications Thorough knowledge of microprocessor architecture including expertise in one or more of the following areasinstruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using a scripting language such as Perl or Python Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 8+ years of Hardware Engineering or related work experience. 2+ years of experience with circuit design (e.g., digital, analog, RF). 2+ years of experience utilizing schematic capture and circuit simulation software. 2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 1+ year in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products. Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area. Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules. Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues. Writes detailed technical documentation for complex Hardware projects. Level of Responsibility: Works independently with minimal supervision. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a DV Engineer with a focus on SOC design verification, you will work to understand the internal requirements and complexities of our highly complex auto, compute, mobile, XR-VR, IoT SOCs and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle. Preferred qualifications B.E/B.Tech/M.E/M.Tech in Electronics with 5+ year experience in verification domain. Strong fundamentals in digital ASIC verification Experience in IP/SS/SoC level verification of medium to high complexity design Familiarity with system level HW and SW Debug techniques and Verification requirements A good understanding of the complete verification life cycle (test plan, testbench through coverage closure) Strong System Verilog/UVM based verification skills & Experience with Assertion & coverage-based verification methodology Experience w/ PSS or higher-level test construction languages is an added advantage Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI Good understanding of low power design techniques Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells. Experience with UPF/CPF based power aware verification. Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus Prior work on NoC/Interconnects end to end verification with solid understanding on to Bus protocols, Coherency, Performance, Latency, clock gating etc. Knowledge of one or more of Multimedia design blocks such as Display/Camera/Video/GFx Knowledge of one or more of peripheral blocks verification such as PCIe/USB/UFS/I3C Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Roles and Responsibilities Define verification architecture, develop test plans and build verification environment Work with design team to understand design intent and bring up verification plans and schedules Verify Subsystems and Full SoC using advanced verification methodologies Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard Develop test plan to verify all low power aspects across all modes of verification- RTL, PA-RTL, PA-GLS and Formal Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals Assist in silicon bring-up, debug and bring-up activities

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. systems architecture.ADAS/Autonomy/Infotainment Qualcomm is utilizing its traditional strengths in digital wireless technologies to play a central role in the evolution of automotive infotainment and autonomous driving. We are investing in several supporting technologies including 4G, 5G, ADAS, and Deep Learning. The Qualcomm Automotive Security team is engaged in offering optimized solutions built on Safety CPU cores, DSP, computer vision and machine learning algorithms for the Qualcomm We are seeking engineers with experience in system and SoC level automotive cybersecurity concepts and implementations and knowledge of the ISO21434 cyber security standards and process. This position will be a hands-on role in in analyzing and improving the current cybersecurity hardware development process to meet ISO 21434. Candidate must have thorough knowledge on ISO 21434 and ISO 26262 standards to independently perform functional safety and cybersecurity audits and assessments. Responsibilities shall include the following Development/ enhancement of hardware development process and related work products meeting cyber security standards. Provide training on ISO 21434/ ISO 26262 with respect to application of Qualcomms best practices. Facilitate TARA and VARA and review them Independently carry out cybersecurity audits and assessments, guiding the hardware design and development teams in the process. Provide feedback and identify process improvements and follow up with internal teams. Work closely with SoC Design and IP teams, 3rd party IP vendors, Software team, the functional safety and cybersecurity manager(s), Quality team as well as customers to ensure the defined process is deployed. Participate in external and customer cybersecurity and functional safety audits and assessments and assist in corrective actions. Maintain a strong knowledge of Automotive Industry cybersecurity best practices. Influence internal stakeholders with actionable data to ensure gaps to expectations are closed in a timely fashion. Establish and maintain healthy relationships with influential/decision making on Cybersecurity, Functional Safety, and ongoing Quality assessments throughout the organization. Facilitate in qualitative and quantitative safety analyses and review of them. Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field. 8+ years Systems Engineering / VLSI design or related work experience. Has knowledge of product development flow and validation. Has led audits of different development processes and is comfortable with assessments and reporting Quality metrics. Hands-on experience with automotive quality processesISO 21434, ISO 26262, TARA, VARA, DFMEA, FTA, FMEDA, 8D, quality agreements, PCNs / EOLs, customer audits, AEC- Q100 requirements, ISO9001, IATF 16949, etc. Structured problem-solving capability and ability to work with teams on root cause analyses. Excellent verbal/written communication, interpersonal skills, and presentation skills

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Systems Engineer, you will research, design, develop, simulate, and/or validate systems-level software, hardware, architecture, algorithms, and solutions that enables the development of cutting-edge technology. Qualcomm Systems Engineers collaborate across functional teams to meet and exceed system-level requirements and standards. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. SOC Architect SoC Architect Staff /Sr-Staff Eng Bangalore Vivek Sheel Mittal Company - Division Qualcomm Technologies, Inc.- Platform Architecture Division Job PositionSenior/Staff Engineer 10-15 years in SOC Architecture/Systems Engineering or related work experience. Job Area Engineering - Systems Location Bangalore Educational Bachelors or Masters in computer engineering and/or Electronics Engineering (or related fields). Overview Work with Qualcomm's Platform Architecture team on next generation System-on-chip (SoC) for Compute, smartphone, IoT and other product categories. Candidate will be involved in architecture and/or microarchitecture of various subsystems and interfaces of the SoCs, e.g. reset, boot, power management, security, access control, debug services, various processing subsystems like CPU, DSP, GPU and AI Accelerator subsystems etc. The successful candidate will - Be part of Qualcomm Platform Architecture Team Work with Hardware and Software teams to understand the design requirements, specification, and interface details. Validate architecture/ microarchitecture models for multiple peripherals, interconnects, and IPs for Qualcomm SoC platforms. Work with team to integrate these models to the SoC platform and validate IP/ System Level use cases. Perform area, power, performance trade-offs and analysis of HW/SW re-usability requirements for IP/Cores and complete SoC. Develop Specification, system level architecture/micro-architecture of system use-cases, working with cross functional teams. Have experience working with ARM-based SoC architectures, in-depth understanding of computer architecture fundamentals, the ability to develop complex systems. Skills/Experience: Bachelors Degree required, Master or PhD degree in related field highly desired. SOC Architecture Background, preferably Compute SOC Architecture. Excellent communication and interpersonal skills Demonstrated ability to collaborate on projects with multiple teams and disciplines. Ability to develop and improve methodologies for experiments and analysis in the specific area of expertise. Have the communication and collaboration skills to work with a large world-wide design organization. Experience or Education involving hardware, System architecture and software. Areas of Expertise (the more the better): Candidates should have one or more of the following areas of knowledge and/or expertise: ARM and RISC-V Architecture expertise specifically in areas of Coherency, Signaling, Memory Management, Virtualization, etc DSPs, CPUs (ARM preferred), High and Low Speed peripherals DDR, Interconnect, System Cache, QOS. Power, Boot, Debug, Security, Access Control Architecture. Power and/or performance analysis, simulation, and modelling. Understanding of VLSI flow from spec to tape out with proficiency in digital design, HDL languages, Scripting languages is preferred.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: GPU Verification Engineer ------ Selected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR/VR. The overall GPU pre-Si verification team in Bangalore is currently heavily involved in the following Formal verification- Block level property based FV sign-off UVM/SV based constrained random test bench for functional verification Subsystem level TB for complete GPU workload analysis and compliance Emulation platforms to analyze performance and pipeline bottlenecks Power Aware & Gate level simulations to deliver a high-quality GPU implementation Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug triage. In the role of GPU Formal Verification Engineer , your project responsibilities will include the following, Develop high quality formal verification test benches to verify complex designs in GPU. It will involve creating & owning the test plan, test bench, performing debugs , deep bug hunting using formal tools and developing sign off quality testbenches and ensuring coverage closure & convergence metrics Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality Collaborate with worldwide architecture, design, and systems teams to achieve all project goals Currently, we are looking for candidates who can match one or more of the profiles listed below, Strong knowledge of Formal Property Verification & Assertion Based Verification, Formal Test planning and coverage analysis, Formal sign off & proof convergence strategies Hands-on experience with industry standard formal tools, such as JasperGold, VCFormal or Questa Formal Strong System Verilog Assertions knowledge, proficiency in Verilog, and scripting (Python, Perl, Tcl) is required Knowledge of GPU pipeline design is a plus, not mandatory Understanding of equivalence based methodologies such as DPV and SEQ is desired Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver Experience Minimum 5 years of Design verification experience Senior positions will be offered to candidates with suitable years of experience and proven expertise matching the profiles listed above Education BE/ME/M.Sc. in Electrical, Electronics, VLSI, Microelectronics, or equivalent courses from reputed universities Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field.

Title : Graphics ASIC RTL Design Engineer- Sr Engineer /Sr Lead / Staff / Sr Staff Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. Qualcomm CDMA Technologies (QCT) is a global leader in Multimedia integrated circuits (ICs), software and systems for wireless consumer devices including Smartphones, Netbooks and E-readers. Our teams are developing advanced technologies to enhance mobile devices in areas including 2D and 3D graphics, audio/video, display and architecture. These Multimedia ASICS are co-designed with our Modems, Applications Processors, Analog Codecs and Power Management ICs to deliver highly-integrated, high-performance and low-cost chipsets to our customers and partners. You will be implementing the industry's leading edge graphics processor, specific areas include 2D and 3D graphics, streaming processor, high speed IO interface and bus protocols. In this position, the designer will be responsible for architecture and micro-architecture design of the ASIC, RTL design and synthesis, logic and timing verification. The successful candidate for this position will specify and design digital blocks in our Multimedia Graphics team that will be integrated into a broad range of devices. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field Previous experience in designing GPU or CPU cores and ASICs for Multimedia and Graphics applications in deep sub-micron CMOS processes for volume productionExperience with Verilog/VHDL design, Synopsys synthesis, static timing analysis, formal verification, low power design, test plan development, coverage-based design verification, and/or design-for-test (DFT)Experience with Computer Architecture, Computer Arithmetic, C/C++ programming languages is desiredExposure to DX9~12 level graphics HW development is big plusGood communication skill and desire to work as a team player RequiredBachelor's degree in Computer Science, Electrical Engineering, Information Systems, or related field.PreferredMaster's degree in Computer Science, Electrical Engineering, Information Systems, or related field. ASIC, hardware, design, GPU, OpenGL, DirectX, RTL, Verilog, SystemVerilog Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle. Roles And Responsibilities Performance exploration. Explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional verification strategy. Performance verification support. Help verify that the RTL design meets the performance goals. Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and po Preferred Qualifications Thorough knowledge of microprocessor architecture including expertise in one or more of the following areasinstruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using a scripting language such as Perl or Python Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 15+ years of Hardware Engineering or related work experience. 4+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF). 4+ years of experience utilizing schematic capture and circuit stimulation software. 4+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 4+ years in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: Leverages expert Hardware knowledge and experience to plan, optimize, verify, and test highly critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Drives the development of design rules and processes for electronic hardware, equipment, and/or integrated circuitry. Serves as an expert resource for conducting highly complex simulations and analyses of designs as well as for the implementation of designs with the best power, performance, and area. Collaborates with high-level representatives across functions (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement and drive new requirements and the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops the novel manufacturing solutions for leading edge products in highly advanced processes and bring-up product to meet customer expectations and schedules. Serves as an expert resource for the evaluation of reliability for highly critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Advises multiple teams of engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues. Writes detailed technical documentation for highly complex Hardware projects; reviews technical documentation for experienced engineers. Level of Responsibility: Provides supervision to direct reports. Decision-making is critical in nature and highly impacts program, product, or project success. Requires verbal and written communication skills to convey highly complex and/or detailed information. May require strong negotiation and influence with large groups or high-level constituents. Works within the prescribed budgetary objectives of the department. Has a great degree of influence over key organizational decisions. Tasks often require multiple steps which can be performed in various orders; extensive planning, problem-solving, and prioritization must occur to complete the tasks effectively.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Qualcomm's XR Technology Systems team is seeking motivated engineers with who will work on driving next generation technologies & platforms enabling the future of Augmented Reality / Virtual Reality / Mixed Reality applications. This team interfaces with product management, platform architecture, technology/IP and software implementation leads. The successful candidate will be responsible for one or more of the following roles Driving technical workstreams across key technology tracks (perception, rendering, composition, reprojection, split-processing, user input interfaces, camera & display processing). Key role here is to have forward looking perspective and identify opportunities for prototyping, demonstrating the system level trade-offs (working with respective technology team(s), helping define the feature goodness criteria from end use case perspective. Collaborating with technology experts to drive strategic direction in cross-functional AR/MR/VR areas. Working with technology, hardware, and software experts to translate use-case requirements into implementation specifications and contributing to reference design planning. Engaging on identifying and scoping new use-cases Early engagement with customers and works on aligning with product management on platform requirements. Working with technology tracks to drive the system level what-ifs/trade-offs and helping with competitive analysis. For this multi-disciplinary role an ideal candidate has experience in AR/VR, computer vision, perception, camera technology, hardware design, SoC architecture, HW/SW partitioning, and/or system modeling (power, performance, thermal). Minimum Qualifications Bachelors degree in Electrical Engineering, Information Systems, Computer Science, or related field, and project experience in architecture/micro-architecture 1+ years of system engineering or related work experience Excellent problem solving and communication skills Preferred Qualifications Masters and/or PhD degree in Electrical Engineering, Information Systems, Computer Science 1+ years experience in HW architecture/design with emphasis on areas listed above Proven experience in conducting architectural trade-offs, power/performance analysis and/or SW-HW trade-offs Extensive knowledge of graphics pipeline, computer vision pipelines, machine learning methods and/or camera pipelines Experience with system level modeling (performance and/or power) C/C++ programming Keywords Camera, ISP, display, composition, rendering, video coding, computer vision, embedded, multimedia, image, algorithms, SOC architecture, micro-architecture Educational RequiredBachelors, Computer Engineering and/or Electrical Engineering or equivalent experience PreferredMasters / Doctorate, Computer Engineering and/or Computer Science and/or Electrical Engineering Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. Qualcomm IPCAD team is developing products and features for Qualcomms in-house validation and release platform for IPs for the next generation System-on-chip (SoC) for smartphones, laptops and other categories. This tool provides libraries and IPs a platform to validate the data before they are integrated with SoC. It also provides release vehicles to make IPs available for SoC in the most seamless way. We are seeking ambitious, bright and innovative engineers with experience in software design, CAD and implementation. Job activities span the whole product life cycle from early requirement gathering to in-house deployment. The environment is fast-paced and requires cross-functional interaction on a daily basis so good communication, planning and execution skills are a must. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Responsibility include : The responsibilities of this role include: Interacting with SoC and IP to understand requirement, define and implement quality enforcing checks. Involved in analyzing field issues and proposing new quality requirements. Making decisions that are moderate in impact; errors may have financial impact or effect on projects, operations, or customer relationships; errors may require involvement beyond immediate work group to correct. Using verbal and written communication skills to convey complex and/or detailed information to multiple individuals/audiences with differing knowledge levels. May require strong negotiation and influence, communication to large groups or high-level constituents. Completing tasks that do not have defined steps; simultaneous use of multiple mental abilities is generally required to determine the best approach; mistakes may result in significant rework. Exercising substantial creativity to innovate new processes, procedures, or work products within guidelines or to achieve established objectives. Working independently with little supervision. Minimum Qualifications Bachelors degree in Electronics engineering, Information Systems, Computer Science, or related field 3-7 years VLSI or related work experience Experience in programming using Python. Preferred Qualifications The person hired in to this role will be contributing to IP validation toolset. 3+ years in software development using Python/Perl. Strong development skill in Python is must. Good understanding of the VLSI design flow in terms of physical implementation, physical verification, signoff. Candidate can have depth in one domain and readiness to pick up another domain. 3+ years in backend CAD flows for STA, DRC/LVS/ERC Working experience in any of STA, DRC, LVS is a plus. Good knowledge on both Front End and Back End ASIC Design flow Basic understanding of Digital Design, Verilog and System Verilog, Assertions Exposure to RTL quality checks like Lint, CDC, Synth, Compilation and Elaboration etc. Good documentation skills. Experience in RTL Design, IP Development or Verification is a plus

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: We are seeking a highly skilled and experienced SoC Management IP Design lead to join our team. This position requires overseeing the development of all SoC Management IPs primarily Debug and Timer IPs, which includes creating micro-architecture specifications, IP design and verification. The ideal candidate will have a strong background in IP development and SoC Management Architecture, with a focus on both technical leadership and management responsibilities. Key Skills Required IP Design /Micro Architecture/ Verification and Delivery Additional Skills (Preferred) SoC Architecture Key Responsibilities Leadership and Management Lead and manage the development of SoC management IPs, Primarily Debug and Timer IPs IP Design, Verification and Delivery Provide technical leadership and guidance to the IP development team. Oversee the entire lifecycle of IP development, from concept to implementation and validation. Collaborate with cross-functional teams to ensure seamless integration of IPs into SoC designs. Technical Expertise Experience of RTL design for complex SoC development using Verilog and/or SystemVerilog Experience with Arm-based designs and/or Arm System Architectures Drive the architecture and design of SoC Management IPs. Ensure the IPs meet performance, power, and area requirements. Stay updated with the latest industry trends and technologies in SoC management and IP development. Troubleshoot and resolve complex technical issues related to IPs. Collaboration and Communication Work closely with other engineering teams, including SoC design, verification, and validation teams. Foster a collaborative and innovative work environment. Communicate effectively with team members, management, and external partners. Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience (10+ years) in SoC Management IP development, including debug and timers IPs. Strong technical leadership and management skills. Excellent understanding of SoC architecture and design principles. Strong problem-solving and analytical skills. Excellent communication and interpersonal skills. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle. Roles And Responsibilities Performance exploration. Explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional verification strategy. Performance verification support. Help verify that the RTL design meets the performance goals. Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and po Preferred Qualifications Thorough knowledge of microprocessor architecture including expertise in one or more of the following areasinstruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using a scripting language such as Perl or Python Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Expertise in AMBA protocols (CHI/AXI/AHB) Excellent analytical skills, should have an experience of leading a team of 7-8 engineers Knowledge of ARM architecture be an added advantage Exposure to low power methodology with understanding of UPF Handson experience of GLS and timing simulations Exposure to Formal verification Self-driven and motivated to work in a high pressure environment Good at stakeholder management with good communication skills Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Working with product engineers, customer support, and R&D to determine training requirements. Creating and updating training lectures, labs, exams, and demos aligned with software releases and with high levels of quality. Designing and developing lectures, labs, and demos deployed online and in the classroom. Delivering courses in a classroom or virtual setting, as required Creating narrated online videos educating customers on how to use tools, languages, and methodologies. Supporting online training customers when there are questions related to lectures and labs. Enjoys various activities – authoring content, learning new tools and methodologies, “being the expert,” teaching and interacting with customers, and working with highly competent and experienced engineers. Given clear goals, can work independently to accomplish such goals. Is aware of analog/mixed-signal design, simulation, and verification flows/methodologies. Has experience in designing and analyzing analog and mixed-signal circuits. Can model and create test benches for mixed-signal, mixed-language designs using Verilog-A and Verilog-AMS. Should be able to model DUT and testbench for Top Level Verification of mixed-signal designs. Has working knowledge of analog/mixed-signal Cadence design tools and simulators such as Virtuoso, AMS Designer, and Spectre. Understands SystemVerilog/real-number modeling capabilities (SVRNM/Wreal). Exposure to UVM-MS would be a plus. Is aware of low-power mixed-signal design requirements with CPF and UPF. Should have a Bachelors’ or Master's degree in Electrical/Electronics Engineering with a minimum 4-6 years of related working experience. Has strong written and verbal English communication skills. Be proud and passionate about the work you do. Together, our One Cadence -- One Team culture drives our success. We’re doing work that matters. Help us solve what others can’t. Show more Show less

Apply now » Technical Product Development Company: NEC Corporation India Private Limited Employment Type Office Location: Kandanchavadi, Perungudi, TN, IN, 600096 Work Location: Hybrid Req ID: 4514 Description Job title: FPGA Architect (Telecom/Aerospace) Reporting Relationship: Reporting to Project Manager Job Summary NEC Corporation India Pvt. Ltd is looking for an experienced and highly talented FPGA Architect with strong telecom or aerospace expertise at NEC Mobile Network Excellence Center (NMEC), Chennai Scope of work System modeling, architecture, and implementation of high-performance FPGA designs for wireless communication and aerospace system Conducting research and development of logical synthesis, netlist partitioning, placement, and routing optimizations for FPGA prototyping. Optimize FPGA designs for latency, throughput, power, performance, and area efficiency Evaluate and select appropriate technologies and tools to support the development process Work with cross-functional teams to align on product requirements and technical specifications. Qualifications BE/B.Tech/M.E/M.Tech Or Its Equivalent Experience 12+ years Domain Skills Strong knowledge of SoC architecture, including CPU, GPU, memory hierarchy, interconnects, and accelerators. Hands-on experience in hardware simulators, SoC design (SoC integration, peripherals, bus design, RTL coding in Verilog/VHDL, CDC, LINT) Experience in RTL coding, synthesis, place-and-route, STA, power analysis, back-end flow, implementing designs in hardware, and advanced digital verification methodology(UVM) Prior experience in integrating Nios, MPIS, MicroBlaze, ARM Cortex, GTX/GTH transceivers, and 10GE MAC/DMA controller/PCIe /CPRI/JESD/FFT IP core. Knowledge of AXI/AHB AMBA bus-based complex multi-master and slave systems, L2/L3 switching, TCP/IP, and network protocols. Experience with EDA tools such as Xilinx Vivado, SystemGenerator, ModelSim/QuestaSim. Proficiency in MATLAB and Python for modelling, simulation, and analysis. Specialization Description Responsible for improving or developing new products, components, equipment, systems, technologies, or processes including: Ensuring that research and design methodologies meet established scientific and engineering standards Assisting with formulating business plans and budgets for product development Analyzing quality/safety test results to ensure compliance with internal and external standards Keeping abreast of new developments in the industry and translating those developments into new and viable options for the organization and customers Organizing technical presentations to customers and/or industry groups Monitoring product development outcomes to ensure technical, functional, cost, and timing targets are met In some organizations, may be responsible for managing product regulatory approval process Level Description Senior level professional that applies advanced knowledge of job area typically obtained through advanced education and work experience. Works independently applying an advanced knowledge of a job area typically obtained through advanced education and work experience. Works to achieve results in a job area, overseeing and managing projects/ processes independently with limited supervision. Problems faced are difficult and are sometimes complex, though are routine. Coaching and reviewing the work of lower level professionals. Headquartered in Japan, NEC is a leader in the integration of IT and network technologies. With over 123 years of expertise in providing solutions for empowering people, businesses, and society, NEC stands tall as a champion in enabling change and transformation across the globe. Present in India since 1950, NEC has been instrumental in burgeoning India’s digitization journey continually for the past 70 years. NEC India has proved its commitment to orchestrating a bright future through its diverse businesses from Telecommunications to Public Safety, Logistics, Transportation, Retail, Finance, Unified Communication and IT platforms , serving across the public and private sectors. NEC India, through the deployment of cutting-edge technology, has been powering India in seminal ways, making lives easier, safer, and more productive for all. With its Centre of Excellence for verticals like Analytics platform solutions, Big Data, Biometrics, Mobile and Retail , NEC India brings to the table, innovative, seamless solutions for India and across the world. NEC India is headquartered in New Delhi and has its offices panned across the country. It has branches in Ahmedabad, Bengaluru, Chennai, Mumbai, Noida and Surat. Specialties IT & Networking Solutions, Unified Communication Solutions, Safety and Security Solutions, Integrated Retail Solutions, Data Centre Solutions, Safe and Smart City Solutions, Transportation Solutions, SDN Solutions, Carrier Telecom Solutions, and Solutions for Society. NEC Career Site - LinkedIn Apply now » Show more Show less

Hiring Remote Software Engineers With Minimum 3 Years Of Experience | Earn ₹ 1,30,000/Month *Educational background should be in Computer Science About the Role: We're hiring a Software Engineer with relevant experience of 3 years to join our growing team of passionate technologists. This is an ideal role for early-career developers seeking to gain real-world experience , contribute to live projects, and grow under the guidance of experienced engineers, all while working remotely. Whether you're a recent graduate, self-taught programmer, or switching into tech, this role allows you to build your skills in a real development environment , on a flexible schedule that fits your lifestyle. What You'll Do: Work on real coding projects in collaboration with cross-functional remote teams Write, test, and debug code in modern programming languages like JavaScript, Python, or Java Learn version control (Git), issue tracking, and agile workflows Participate in virtual meetings, peer code reviews, and guided mentorship sessions Contribute to web or software development projects and gain experience across front-end and back-end systems Receive structured feedback and continuous learning support What Were You Looking For: Proficiency in at least one of the following programming languages: Java / Python / JavaScript / TypeScript / C++ / Swift / Verilog. Must have a minimum of 3 years of experience in Software Development Must have an educational background in Computer Science Basic familiarity with version control (Git), databases, or web development is a plus Strong desire to learn and grow in a remote tech environment Ability to communicate clearly and collaborate asynchronously A proactive mindset and consistent access to a computer and stable internet Compensation & Benefits Earn ₹1,30,000/month. Flexible remote work schedule (5–10 hours/week). Free access to advanced AI tools and platforms. 🌍 Why Join Us? Be part of a global network of coding experts advancing AI with flexibility, transparency, and cutting-edge resources. Show more Show less

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network-on-Chip (NoC), and cutting-edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. KEY RESPONSIBILITIES: Verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: Require experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus. Require familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate-level simulation, power-aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. Technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs . ACADEMIC CREDENTIALS: Require BS w/ 4+ yrs or MS w/ 3+ yrs or PhD in Electrical Engineering, Computer Engineering or Computer Science. #LI-MK1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job Requirements KEY RESPONSIBILITIES Good knowledge of front-end design construction and verification. Experience in SoC Build, infrastructure tools & debugging integration issues o Knowledge of AMD flow and infrastructure. Familiarity with DJ Expertise in SoC/IP register methodology and & hands-on in IP-SoC integration, related issues & debugging failures A working knowledge of IP-XACT focused on interfaces and register descriptions. Hands on knowledge and experience with C, C++, Perl, Python, Ruby, TCL, and any other scripting languages Familiarity with design Infrastructure such as lsf, parallelism. Familiarity with Verilog, SV and Testbench languages. Work Experience PRIOR EXPERIENCE 3-5 years of Experience with EDA software development or support, ability to architect solutions to deep problems in front end design construction and verification and implementing infra are a must. Key items of interest are Excellent communication and writing skills Project execution. Customer and partner relations. Proposals and strong new initiatives impacting DV methodology

MTS Silicon Design Engineer Hyderabad, India Engineering 66137 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the Design and support verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be designed Execute design plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to design the new features tests and any required changes to the design environment Debug test failures to determine the root cause; work with Verif and firmware engineers to resolve design defects and test issues Review functional and code coverage metrics PREFERRED EXPERIENCE: Proficient in IP level ASIC Design Proficient in debugging firmware and RTL code using simulation tools Proficient in using Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PK2 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Amrita Vishwa Vidyapeetham, Amritapuri Campus is inviting applications from qualified candidates for the post of IoT and Embedded Systems Developer (Rural Technologies Team). For Details Contact: careers@ammachilabs.org Job Title IoT and Embedded Systems Developer (Rural Technologies Team) Location Kollam , Kerala Required Number 1 Job description As a Developer, you will be responsible for designing, developing, and maintaining innovative IoT solutions and hardware-accelerated systems that serve diverse user needs. You will also contribute to integrating AI features at the hardware level to enhance the overall user experience and system efficiency. Your work will play a key role in building scalable, efficient, and innovative digital solutions that improve access, engagement, and service delivery, particularly in rural contexts. The ideal candidate will have hands-on experience in IoT, digital electronics, a foundational interest in AI technologies, and a passion for creating impactful applications. Responsibilities Design, develop, and maintain high-performance IoT devices and embedded systems. Collaborate with hardware and software teams to translate project requirements into functional systems. Integrate sensor data and manage IoT connectivity to extend application functionalities. Implement hardware-accelerated AI and machine learning algorithms for tasks such as data classification and pattern recognition. Optimize embedded systems for performance, speed, and reliability across various applications. Write clean, scalable, and maintainable code in languages such as C and Verilog HDL. Conduct thorough testing and debugging to ensure hardware and software quality and reliability. Stay updated on the latest trends in IoT, embedded systems, and AI technologies. Work closely with cross-functional teams to define, design, and ship new features. Maintain clear and organized documentation of code, hardware designs, and development processes. Qualification Bachelor’s or Master’s degree in Electronics and Communication Engineering, Computer Science, Software Engineering, or a related field. Strong proficiency in C and Verilog HDL. A strong foundation in AI concepts, including machine learning algorithms like k-Nearest Neighbors, demonstrated through hardware implementation projects. Experience 0–2 yrs in in developing projects in IoT and digital electronics, such as smart assistance systems, waste management solution; experience with development tools like Arduino IDE, Questa SIM, and Tinkercad.s, and real-time monitoring systems. Last date to apply June 16, 2025

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Sr SILICON DESIGN ENGINEER The Role As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence. The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Job Deliverables Setup ASIC QA flows for RTL design quality checks. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps. Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers. Checking the flow errors, design errors & violations and reviewing the reports. Debugging CDC, RDC issues and come up with the RTL fixes. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks. Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc. Flows or Design porting to different technology libraries. Generating RAMs based on targeted memory compilers and integrating with the RTL. Running functional verification simulations as needed. Job Requirements B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes Digital design and experience with RTL design in Verilog/SystemVerilog Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation Preferred experience in AXI4 or NOC protocols or DRAM memory interfaces. TCL, Perl, Python scripting Preferred Experience Project level experience with design concepts and RTL implementation for same Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics Good understanding of computer organization/architecture Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less