2286 Verilog Jobs - Page 6

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Required Qualifications Bachelor's degree /masters degree in Electronics & Tele Engineering, Microelectronics, Computer Science, or related field. 9+ years RTL Design/Hardware Engineering experience or related work experience. Skills/Experience Required Strong Domain Knowledge on RTL Design , implementation, and integration. Experience with RTL coding using Verilog/VHDL/System Verilog. Experience in micro-architecture & designing cores and ASICs. Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc. Exposure in scripting (Pearl/Python/TCL). Strong debugging capabilities at simulation, emulation, and Silicon environments. Collaborate closely with cross-function team located in different time zone to research, design and implement performance and power management strategy for product roadmap. Good team player. Need to interact with the other teams/verification engineers proactively. Responsibilities Design and lead all Front-end design activities for Display Sub-system that deliver cutting edge solution for various Qualcomm business unit like VR, AR, Compute, IOT, Mobile. Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks. Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation. Support SoC team to integrate Display Sub-system IP solution into various SoC chips and front-end design flows. Work closely with system/software/test team to enable the low power feature in wireless SoC product. Evaluate new low-power technologies and analyze their applications to address requirements. Understand and perform block & chip-level performance analysis & identify performance bottleneck and provide required solution. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational Requirements2+ years of experience with a Bachelors/ Masters degree in Electrical engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Highly skilled SystemC Modeling Engineer is required to join dynamic and innovative NoC Systems team in Qualcomm Bangalore Design Center. The ideal candidate will have a strong background in digital design and a deep understanding of SystemC for hardware modeling and simulation. This role involves developing and maintaining high-quality SystemC models for complex digital systems, collaborating with cross-functional teams, and ensuring that Qualcomm products meet the highest standards of performance and reliability. Key Responsibilities: Model Development: Design and implementation of SystemC models for digital systems, including processors, memory controllers, and peripheral interfaces. Methodology Awareness of Virtual prototypes and Performance modeling using C++/SystemC/TLM 2.0. Approximately timed and Loosely Timed(LT) style of coding for software development when using Virtual Prototype Verification: Development and executution of testbenches to verify the correctness and performance of SystemC models. Optimization: Optimization of models for simulation speed and resource efficiency. Documentation: Creation and maintenance of detailed documentation for models, testbenches, and verification plans. Collaboration: Work closely with hardware and software engineers to ensure seamless integration of SystemC models into the overall system design. Troubleshooting: Identify and resolve issues in the modeling and simulation process. Research: Stay updated with the latest advancements in SystemC and digital design techniques. Technical Skills Proficient in SystemC and C++. Strong understanding of digital design principles and techniques. Experience with hardware description languages (HDLs) such as Verilog is a plus. Familiarity with simulation tools and environments is a plus. Soft Skills Excellent problem-solving and analytical skills. Strong communication and collaboration abilities. Ability to work independently and in a team environment. Attention to detail and a commitment to quality. Preferred Skills Experience with Network-on-chip, high-performance computing and parallel processing. Knowledge of ASIC design. Familiarity with scripting languages (e.g., Python, Perl). Experience with version control systems (e.g., Git). Qualifications: Education: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 5 to 10 years of experience in digital design and SystemC modeling. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Principal Design Verification Engineer Job Overview MIPS is seeking a highly experienced Senior Staff Design Verification Engineer with over 15 years of industry experience to lead verification efforts focused specifically on Coherency Manager and Cache Controller components. The successful candidate will have extensive hands-on experience utilizing advanced verification methodologies, including constrained random testing, formal verification, and coverage-driven verification. This senior role involves close collaboration with CPU architects, designers, and cross-functional global teams to ensure high-quality, high-performance processor designs. Key Responsibilities Lead and drive verification activities for Coherency Manager and Cache Controller IP to closure. Collaborate closely with design teams and architects to thoroughly understand and interpret microarchitectural and functional specifications. Develop comprehensive verification plans and execute these plans through testbench creation, test case development, and rigorous analysis. Create directed and constrained random test cases in SystemVerilog, Assembly, and C to verify complex coherency and cache management behaviors. Employ formal verification techniques to augment random verification and ensure exhaustive coverage. Analyze verification coverage metrics to identify and close coverage gaps efficiently. Automate and optimize verification flows and regression environments using scripting languages like Python, Perl, TCL, or Shell. Mentor junior verification engineers, providing technical guidance and leadership within the verification team. Qualifications Master`s degree or higher in Electronics, Electrical, Computer Engineering. 15+ years of relevant verification experience, specifically in CPU or complex SoC verification. Proven expertise in verification of Multicore and Multicluster Coherency, Cache Controllers, or similar blocks. Deep knowledge and practical experience with verification methodologies such as UVM, constrained random, and formal verification. Proficiency in SystemVerilog, Verilog, C, C++, and Assembly. Solid understanding of interconnect and coherency protocols such as AXI, ACE, OCP, CHI. Strong scripting skills in Python, Perl, TCL, or Shell. Experience with CPU architectures, particularly RISC-V, ARM, or MIPS. Preferred Experience Experience with RISC-V architecture. Familiarity with functional safety standards (e.g., ISO 26262). Prior exposure to FPGA prototyping and emulation platforms. What MIPS Offers Opportunity to be part of a dynamic team creating industry-leading RISC-V processors. Autonomy with extensive support from industry experts. Opportunities for significant career growth and technical advancement. Competitive compensation and comprehensive benefits package About MIPS MIPS is a pioneer in RISC-based computing with a legacy of innovation in high-performance microprocessor design. Today, MIPS continues this legacy by leading the adoption and advancement of the RISC-V architecture, delivering scalable processor solutions for cutting-edge computing applications.

Where Technical / Product Publications, Staff Engineer Bengaluru, Karnataka, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 12356 Date posted 07/24/2025 Share this job Email LinkedIn X Facebook Who we are: Synopsys (NASDAQ: SNPS) is the biggest ASIC EDA software company and the 2nd largest semiconductor IP provider in the world. Founded in 1986, $5B+ Synopsys employs 20,000+ headquartered in Mountain View, California, located globally in over 25 countries with 113+ offices throughout North America, Europe, Japan, Asia, and India. We enable companies to create the leading-edge micro-chips found in the latest smartphones, data center servers; and automobile smart systems. Synopsys is committed to fostering an environment that treats people with respect, honesty, and professionalism. We only want the best of the best to join our team. Be ready to produce results; bring innovation, creativity, and passion to work every day. What you will do: As a tech savvy and passionate Technical Writer in the Solutions Group at Synopsys, you will be part of a group responsible for developing and writing user documentation for various Digital and Mixed Signal IPs. You will have an opportunity to work across the various IP product lines of USB, PCIe, Ethernet, DDR, HDMI, MIPI etc., You will be responsible for planning, organizing, writing, and editing the technical specifications, engineering schematics, application notes, and user guides. You will be interfacing with our Design Engineering team to collect the raw content of technical specification and to effectively transform this into user consumable collateral by following the doc-processes. You will work independently, interacting, and collaborating with multi-site teams and you will deliver high quality documentation by demonstrating strict adherence to the style guide and other doc-processes followed by the group. As a writer, you will collaborate with other teams and have a significant and immediate impact on all customer documentation produced and the documentation roadmap. Hard skills we are looking for: Degree or masters in any electronics, science, hardware, computing, software, physics, mathematics, or engineering discipline. Other technical disciplines also considered. 3-7 years technical writing experience in software or hardware industry Excellent problem-solving skills; strong logical reasoning and solution-oriented Experience with authoring tools such as FrameMaker Excellent English writing and speaking skills Soft skills we are looking for: Has excellent communication and interpersonal skills Energetic and capable of learning new technologies as necessary Team player and able to work independently with minimal supervision You care (about others, about doing a good job, about details) You take ownership of projects and tasks assigned to you with little to no supervision and have pride in quality work done correctly the first time Advantageous skill areas that will give you the edge: Familiarity with Verilog and ASIC digital design flows TCL Structured FrameMaker. XSLT and XPATH Structured FrameMaker EDD and DTD DITA, DocBook, or IP-XACT XML schemas FrameScript, ExtendScript, or FDK DITA Open Toolkit At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Analog Design, Sr Engineer Bengaluru, India Engineering Analog Design, Sr Engineer Bengaluru, India Engineering R&D Engineering, Sr Engineer Bengaluru, India Engineering

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you? We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Looking for Siemens EDA ambassadors We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us – whichever path you take, we’re looking forward to seeing your point of view! Veloce Transactors (Accelerated Verification IPs) Veloce Transactor Group is part of Mentor Emulation Division R&D located in Noida. Group develops transactors (RTL based IPs/VIPs) for various protocol solutions in Networking, Display, Storage, Mobile, Automobile etc. At present Veloce Transactor Library supports more than 25 protocol solution and growing further. This is your Role Individual will be responsible for developing transactor (xVIP) solutions for CCIX or PCIe based interconnect technology. Primary responsibilities include understanding standard specifications, develop architecture and micro-arch for the design and writing a synthesized design using Verilog/System Verilog. Required Experience: We seek a graduate with at 5-8 years of relevant working experience with (BE/BTech/ME/MTech/MS) from a reputed engineering college. We value your experience on the protocol e.g. PCIe, USB, Ethernet, AMBA in Design or Verification. Good understanding of IP Verification Methodologies, Verification procedures and practices are plus! Experience in one or more verification techniques such as simulation, emulation, acceleration, formal, etc We value expertise in Verilog, SystemVerilog, and SystemC, as well as experience in developing RTL for FPGAs, ASICs, and IPs, as this will greatly contribute to the quality of our products. We expect candidates to be able to build verification test plans and environments, develop test cases, utilize VIPs, and efficiently debug defects identified during verification processes. We consider exposure to object-oriented programming languages like C++ an advantage, and experience in scripting languages such as Perl will also be valuable in automating tasks and improving efficiency. You need to engage with customers for Deployment and R&D assistance. We've got quite to offer, how about you? We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.

You are a passionate and innovative engineer with a strong foundation in digital and analog design You have a knack for developing complex arithmetic and logic operations and are adept at translating algorithmic flowcharts into pseudo code Your background in Electrical Electronics Engineering, Electronics and Telecommunication Engineering, or a related field has equipped you with the skills necessary to excel in high-speed serial link design and verification You thrive in a collaborative environment and have a continuous improvement mindset, always eager to learn and grow Your knowledge of hardware description languages like Verilog and SystemVerilog, combined with your understanding of protocols such as PCIe and IEEE8023, makes you a valuable asset to any team You are ready to take on challenges and contribute to the success of cutting-edge technology What Youll Be Doing: Designing and verifying high-speed serial links for inter and intra chip communication Developing finite state machines for complex digital and analog operations Translating algorithmic flowcharts into efficient pseudo code Conducting functional verification using methodologies like UVM, OVM, and VMM Collaborating with cross-functional teams to ensure design and verification accuracy Staying updated with the latest industry protocols and standards to meet technical requirements The Impact You Will Have: Enhancing the performance and reliability of high-speed data transfer systems Contributing to the development of innovative technologies that shape the future of connectivity Ensuring the successful integration of high-speed serial links in various applications Improving product quality and efficiency through rigorous design and verification processes Setting new benchmarks in the industry for data transfer speed and reliability Driving continuous improvement and innovation within the team and organization What Youll Need: 2-3 yrs with Bachelors or Masters degree in Electrical Electronics Engineering, Electronics and Telecommunication Engineering, or a related field Strong fundamentals in digital and analog design Proficiency in hardware description languages, especially Verilog and SystemVerilog Experience with functional verification methodologies like UVM, OVM, and VMM Knowledge of high-speed serial data protocols such as PCIe and IEEE8023 Who You Are: Innovative and passionate about technology Detail-oriented with strong problem-solving skills Collaborative and team-oriented Adaptable and eager to learn new skills Effective communicator with the ability to convey complex ideas clearly The Team Youll Be A Part Of: You will be part of the Solutions Group (SG) at Synopsys India Pvt Ltd, a team of experts dedicated to pushing the boundaries of high-speed serial link design, verification, validation, and packaging This team is committed to meeting industry standards and protocol requirements, ensuring our consumer and enterprise products lead the market in performance and reliability

To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people It requires a consistent and committed practice, something we call the Juniper Way ASIC Engineer Design Silicon Systems Technology Group (SST) seeks ASIC Design Engineers to develop next generation of ASICs for new core routers, switches, and firewalls Opportunity Snapshot: We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems You will have a significant opportunity to interact with system design teams across geographies Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture Thus, you set your own limits for learning, achievements and rewards Responsibilities: Define and architect high-performance blocks for the latest, most advanced networking ASICs Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power Collaborate with the verification team in the development of the testplan and assist in debugging test failures Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes Required Skills: 5+ years of ASIC design experience Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus Knowledge of high performance memory subsystems Knowledge of multi-domain clock synchronization and high-speed serial interfaces Strong problem solving and ASIC debugging skills Excellent written and verbal communications skills MSEE or BSEE is required

• Experience in behavioural, post synthesis verification/ simulation with Xilinx FPGA tools. • Good knowledge in static timing analysis and clock domain crossing techniques. • Experience in writing Verilog/ VHDL code for peripheral interface like LCD/ LED Displays/ Keypads, serial memories over Parallel/ SPI/ UART, I2C interfaces. • Good experience in porting and validating the code on custom hardware boards. • Knowledge and experience of defining HW/ FW interfaces. • Experience in on board debugging using chipscope,ILA and data capture tools. • Experience in the following is a plus: - AMBA protocols (AXI, AHB, APB) - In hardware design involving FPGA and associated component selection, schematic preparation, PCB artwork guidance and board testing will be supplemental. - Experience in writing code for digital signal processing techniques (like FIR, CIC filters, Equalizer and MODEM) in FPGAs. - Knowledge in Matlab scripting language.

Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : PySpark Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your typical day will involve collaborating with various stakeholders to gather requirements, overseeing the development process, and ensuring that the applications meet the specified needs. You will also be responsible for troubleshooting issues and providing guidance to team members, fostering a collaborative environment that encourages innovation and efficiency in application development. Roles & Responsibilities:- Expected to perform independently and become an SME.- Required active participation/contribution in team discussions.- Contribute in providing solutions to work related problems.- Facilitate knowledge sharing sessions to enhance team capabilities.- Mentor junior team members to support their professional growth. Professional & Technical Skills: - Good to have skills - AWS S3, DeltaLake, Airflow- Experience should be 4+ years in Python- Candidate must be a strong Hands-on senior Developer- Candidate must possess good technical / non-technical communication skills to highlight areas of concern/risks- Should have good troubleshooting skills to do RCA of prod support related issues Additional Information:- The candidate should have minimum 3 years of experience in PySpark.- This position is based at our Bengaluru office.- A 15 years full time education is required.- Candidate must be willing to work in Shift B i.e. from 11 AM IST to 9PM IST. Also, do the weekend support as per a pre-agreed rota. Compensation holiday may be provided for the weekend shift Qualification 15 years full time education

Job Description and Requirements : Education B.E./B.Tech/ME/M.Tech Electronics and Communication Experience 3-8 years’ experience in the verification domain Deep protocol insight in NVMe, DDR4/5, DIMMs, HBM2/3 protocol Hands on experience of developing complex protocols verification components with System Verilog, Verilog and OVM/UVM methodology; C/C++ knowhow is plus Good knowledge of simulation and/or emulation technologies with proven triage skills Well versed with new product deployment challenges at customers across geographies Scripting skills Job responsibilities Successfully deploy emerging protocol standards solutions for simulation and emulation platforms. Publishing success stories on each successful deployment. Periodic protocol spec upgrade and latest product offering training to field AEs for scalability in deployments Tracking protocol evolution in standards org meetings and bringing that insight to marketing, engineering, and application engineering teams Technical publications in standards conferences, DVCon, DAC, SNUG for promoting Synopsys solutions visibility. Validates field of use by expert testing for leading edge solution prior early adopter releases and effective reviewer of user APIs, test plans Ensure solutions collateral readiness by contributing/reviewing datasheets, feature specific pdfs and user guides step locked to latest release offerings Help drive product direction and product roadmap based on customers’ requirements and market size and adoption assessment. Own setting up right priorities based on business requirements Should be able to travel international and domestic

Must Have: SV/UVM, Test Bench Development , Any Protocols Must be able to own and drive the verification of a block / subsystem or a SOC. Must have extensive experience in verification Share resume to mansoor@hisoltech.com

About Scaledge: Scaledge is one of the fastest growing product engineering services companies focused on Semiconductor Chip - Design & Verification, Processors, System design and related Embedded Software development for domains like Storage, RISC-V, AI/ML, Automotive, Consumer, Networking and IoT. We are headquartered in Silicon Valley, USA with multiple design centers across India, UK and Canada. Scaledge has a strong history of technology, methodology & domain expertise in IP/ASIC/SOC verification in Storage, Networking, Mobile & Consumer industry About Opportunity: Scaledge is looking for experienced, talented Verification Engineers (ASIC/IP/SOC/CPU/GLS) for dynamic and innovative Team. As a member of the team, you will be responsible for verifying the design, architecture and micro-architecture using advanced verification methodologies Requirements Experience 5+ years. Hiring for Senior Engineer, Technical Lead, and Architect levels Dedicated/hands-on ASIC/IP/SOC DV experience. Experience working on block level UVM test benches - writing drivers, scoreboards, sequences, constraints, and functional coverage models Strong interest in understanding the architectural and micro-architectural details of a design. Strong interest in debugging complex issues Drive and adopt new verification methodologies to improve effectiveness and efficiency Experience working on the memory subsystem is a plus Responsibilities Build UVM test benches and own the verification of an IP from start to finish. Create coverage driven verification plans from specifications. Execute, review and refine to achieve coverage targets. Set up regressions and triage failures. Debug and drive any design and verification bugs found, to closure. Work with the team to improve DV methodology and infrastructure. Required Skills Strong knowledge of Verilog, System Verilog, and Object-Oriented Programming Experience with modern verification techniques, especially including System Verilog, UVM, constraint-random and functional coverage methodologies Complete understanding of verification life cycle and ability to create of comprehensive verification plans Knowledge of high-speed PCIe, DDR, USB, AXI, APB, AHB protocols Experience verifying networking protocols such as Ethernet is a plus Experience with scripting languages such as Python, Tcl, or Perl Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out Strong technical writing and verbal communication skills Education BTech/MTech in Electronic/Microelectronics, Electrical Engineering or Computer Science. Other Science graduates would be considered if they have relevant experience.

Senior RTL Design Engineers Experience : 3-5 years Location : Hyderabad Strong RTL(verilog/system verilog) skills with experience in IP development. • Ability to verify designs by writing simple testbenches. • Strong foundation in logic synthesis and timing closure concepts. • Good knowledge of SoC architecture, AXI bus protocols, hardware debug. • Experience of working with Xilinx FPGAs, Vivado tool flows and micro architecture development is a plus. Interested,please drop your updated resume to janagaradha.n@acldigital.com

Vicharak is on the lookout for a passionate and dynamic Computer Science Intern who will play a pivotal role in the convergence of software and hardware, contributing to the development of cutting-edge technologies. This internship offers a unique opportunity to work on Vaaman, our revolutionary single board computer, and gain hands-on experience in software development, Linux kernel understanding, and hardware acceleration over FPGA. Responsibilities: Software Development: Collaborate with the software development team to design, implement, and optimize software solutions for Vaaman's diverse applications. Write clean, efficient, and well-documented code in languages such as C/C++ and other relevant programming languages. Linux Kernel Understanding: Gain insights into the Linux kernel architecture and contribute to kernel-level software components for Vaaman, ensuring seamless integration with the operating system. Hardware Acceleration Design: Work closely with hardware engineers to design and implement hardware acceleration solutions over FPGA, leveraging your understanding of computer architecture. Develop FPGA configurations to optimize performance for specific applications, contributing to the overall efficiency of Vaaman. Programming Languages: Utilize your proficiency in C/C++ and other programming languages to implement robust and efficient software solutions for Vaaman's diverse range of functionalities. Collaboration and Communication: Engage in cross-functional collaboration with software developers, hardware engineers, and other team members. Effectively communicate technical concepts and ideas within the team. Requirements: Currently pursuing a degree in Computer Science or related field. Strong programming skills in C/C++ and familiarity with other relevant languages. Understanding of Linux kernel architecture. Interest in hardware acceleration and FPGA development. Eagerness to learn and adapt to new technologies and challenges. Effective communication and teamwork skills. Preferred Qualifications: Previous experience with FPGA development tools and languages (Verilog, VHDL). Exposure to Linux kernel-level development. Familiarity with computer architecture concepts. Enthusiasm for exploring innovative solutions at the intersection of software and hardware.

Job Title: RTL Design Engineers Exp Level: 4+ yrs Loctaion: Hyderabad Job Description: • RTL coding knowledge • Top-level (SOC) level basic industry standard Arch knowledge • SoC & IP level Integration knowledge • IPXACT knowledge • IORING and Phys & GPIOs basic functionality • Design Partitioning(Tilification) knowledge • Design RTL quality checks: Clock domain crossing(CDC) Reset domain crossing(RDC) LINT VSI UPF knowledge LEC(Logic equivalence check) Timing concepts & SDC knowledge • Tools knowledge: Vc_static or equivalent other tools(VSI) VC_spyglass LINT, CDC and RDC 0in Formality and conformal LEC tool • Design and scripting languages: Verilog and SV Perl Python TCL

Experience: 4 years Location: Hyderabad FPGA Design: Develop FPGA designs using hardware description languages (HDLs) such as VHDL or Verilog. Implement and optimize complex digital logic circuits for high-performance applications. Synthesis & Optimization: Perform synthesis, place and route, and optimization of FPGA designs to ensure optimal area, performance, and power consumption. Testbench Development & Verification: Develop and execute testbenches for simulation and verification of FPGA designs using tools such as ModelSim, Vivado, or Questa. Ensure designs meet functional, timing, and performance requirements.

Design Verification Engineer_Full-Time_Bangalore(Hybrid) Hi, Greetings from Best Infosystems Ltd.! We've spotted your impressive profile and have an exciting opportunity tailored to your skills and passions. Job Title: Design Verification Engineer Job Type: Full-Time Location: Bangalore (Hybrid) Experience: 8+ years Job Description: About the role: We are seeking a seasoned Design Verification Engineer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions. Responsibilities: • Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems • Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards • Collaborate with software teams to define and implement configurable test benches • Work with design teams test plans, failure debug, coverage, etc. Qualifications and Preferred Skills: • BS, MS in Electrical Engineering, Computer Engineering or Computer Science • 8+ years and current hands-on experience in block-level/IP-level/SoC-level verification • Proficiency in Verilog, SystemVerilog • Familiarity with industry-standard EDA tools for simulation and debug • Deep experience with UVM-based test benches • Experience with modern programming languages like Python • Knowledge of Arm AMBA protocols such as AXI, APB, and AHB • Understanding of Arm CHI protocol is a plus • Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs • Experience with formal verification techniques, emulation platforms is a plus • Excellent problem-solving skills and attention to detail • Strong communication and collaboration skills

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SOFTWARE DEVELOPMENT ENGINEER 2 The Role We are looking for a dynamic, upbeat software engineer to join our growing team. As a key contributor you will be part of a leading team to drive and enhance AMD’s abilities to deliver the highest quality, industry-leading technologies to market. The Person The ideal candidate possesses an innovative and problem-solving mindset, has a keen eye for FPGA architecture and performance modeling, and is diligent and passionate about Technology. Key Responsibilities Performance estimation of diverse workloads on FPGAs composed of heterogeneous compute elements Contribute to a high-functioning architecture and performance modeling team Collaborate closely with multiple teams to deliver key planning solutions and the technology to support them Help contribute to the design and implementation of future architecture for a highly scalable, durable, and innovative system Preferred Experience Good knowledge and hands-on experience in C, Python, Verilog Good understanding of FPGA architecture and EDA tool flow. Familiarity with Linux and modern software tools and techniques for development Good analytical and problem-solving skills Academic Credentials Master’s degree in Computer or Electronics Engineering, or related technical discipline Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Location: Bengaluru (Client Site) Job Type: Full-time Experience: 3-7 years Notice Period: 0-15 days (immediate joiners preferred) No. of Positions: 1 Lead & 4 Engineers About The Role We are seeking a skilled FPGA Engineer with 37 years of experience in RTL design using Verilog, along with expertise in Xilinx MPSoC platforms, MicroBlaze processor development, and embedded system security aspects such as authentication, encryption/decryption, and certificates. The ideal candidate will play a key role in architecting and implementing secure, high-performance digital logic systems. Requirement Experience band 3-7 years Experience in RTL coding using Verilog Experience on development on Xilinx MPSoC (preferably ZCU 106/104) Hands-on experience with Xilinx Vivado and Vitis Desirable to have experience with MISRA C coding guidelines Desirable to have experience with DO-254 Desirable to have experience with Microblaze Desirable to have experience in security aspects of authentication, certificates, encryption/decryption How to Apply If you are passionate about embedded systems and meet the above requirements, we would love to hear from you. Kindly share your resume at: hr@advantal.net For more information, connect with us at: 91 91312 95441

Location: Bengaluru (Client Site) Job Type: Full-time Experience: 3-7 years Notice Period: 0-15 days (immediate joiners preferred) Embedded Engineer Advantal Technologies is seeking for the following positions: Experience band 3-7 years (We can have one lead of experience around 7 and rest 3 years) Experience in C programming on Bare Metal Experience on development on Xilinx MPSoC (preferable ZCU 106/104) Hands-on experience on Xilinx Vitis Desirable to have experience on MISRA C coding guidelines Desirable to have experience on DO-178C Experience on device driver development Experience on protocols: I2C, SGMII, UART, SPI Desirable to have experience on security aspects of authentication, certificates, encryption/decryption FPGA Engineer: Experience band 3-7 years (We can have one lead of experience around 7 and rest 3 years) Experience in RTL coding using Verilog Experience on development on Xilinx MPSoC (preferable ZCU 106/104) Hands-on experience on Xilinx Vivado and Vitis Desirable to have experience on MISRA C coding guidelines Desirable to have experience on DO-254 Desirable to have experience on Microblaze Desirable to have experience on security aspects of authentication, certificates, encryption/decryption Technical Lead Minimum 8 years of experience. Minimum of 2 years experience in leading teams Excellent understanding of embedded system development and real-time application development. Hands-on experience in bare-metal code development using C, over an embedded platform Hands-on experience of FPGA design flow and experience digital design development using Verilog HDL. Experience in DO-178C compliance and certification Understanding of software development using API, and networking protocols Should be able to address the non-functional aspects like performance, scalability, reliability, availability etc. Should have a good understanding of the security aspects of the applications like authentication, authorization, public key infrastructure, SSL, certificates, etc. Good hands-on with design, coding, and resolving the technical issues Good experience in review process architecture, design, code. Fair understanding and working experience in Qt, C / Java/python programming languages. Technical hands-on with tools and related framework. Strong interpersonal and excellent communication skills. Testers Minimum 3 years of experience in testing of embedded systems. Experience in test case design and related execution. Experience in testing Zynq ultrascale MPSoC using Xilinx Vivado. Experience in writing test bench using Verilog/System Verilog. Experience in QuestaSim or equivalent simulation tool, simulation environment creation, good experience in code coverage, branch coverage. If interested, please contact hr@advantal.net

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . We are seeking a Senior Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. Key Responsibilities Design and implement high-performance digital solutions, including RTL development and synthesis. Collaborate with cross-functional teams on IP integration for processor IPS and peripherals Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm. Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug. Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows Basic Qualifications Bachelor's in Electronics /Electrical Engineering (Master's preferred). 5+ years of digital design experience, with 3+ years focused on processor, peripherals and full chip implementation. Proven expertise in RTL development, synthesis, and timing closure. Experience with front-end design, gate-level simulations, and design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Required Expertise Hands-on experience with processor IP (ARM/ARC) Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART Strong proficiency in System Verilog/Verilog and scripting (Python/Perl). Silicon bring-up and post-silicon debug experience. Familiarity with Synopsys/Cadence tools and UVM-based design verification. Preferred Experience Hands-on experience with complex DMA engines and FW interaction Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems Experience with block-level and full-chip design at advanced nodes (≤ 16nm). Understanding of PAD design, DFT, and floor planning. Experience with NIC, switch, or storage product development. Familiarity with working in design and verification workflows in a CI/CD environment. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Job Title: IP Design Technical Lead/ Staff ASIC RTL Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures. You’re adept at working with advanced protocols such as Ethernet, DDR, PCIe, and USB, and have hands-on experience in data path and control path design, including Reed Solomon FEC, BCH codes, and MAC SEC engines. Your expertise extends to synthesizable Verilog/SystemVerilog coding, timing closure, CDC analysis, and P&R-aware synthesis, complemented by a keen understanding of design trade-offs in area, latency, and throughput. You are comfortable leveraging version control systems like Perforce and scripting languages such as Perl or Shell to automate and streamline workflows. As a natural leader, you are ready to mentor and technically guide a team of designers, fostering a collaborative and inclusive culture. Communication comes easily to you, and you’re known for your proactive problem-solving skills, attention to detail, and unwavering commitment to design quality. You’re seeking an opportunity to take ownership of challenging projects, contribute to cutting-edge innovation, and grow alongside a team of world-class engineering professionals. What You’ll Be Doing: Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications. Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features. Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks. Collaborating with global teams and engaging directly with customers to understand and refine specification requirements. Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler. Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies. Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency. The Impact You Will Have: Enable Synopsys to deliver industry-leading, high-performance IP cores that power next-generation technologies. Contribute to the successful execution of complex, global projects that set new standards in chip design and verification. Accelerate time-to-market for customers in commercial, enterprise, and automotive sectors by delivering robust, reliable IP solutions. Elevate the technical capabilities of your team through mentorship and leadership, cultivating a culture of continuous learning and innovation. Drive improvements in design quality, efficiency, and scalability through process optimization and automation. Directly influence product architecture and feature enhancements, ensuring alignment with customer needs and emerging industry trends. What You’ll Need: Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field. 4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects. Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines. Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis. Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler. Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation. Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI). Exposure to quality processes in IP design and verification is an advantage. Prior experience as a technical lead or mentor is highly desirable. Who You Are: Innovative thinker with a solutions-oriented mindset and a passion for technology. Excellent communicator who thrives in collaborative, multicultural, and multi-site environments. Natural leader with mentoring abilities, fostering inclusion and diversity within the team. Detail-oriented professional with strong analytical and problem-solving skills. Self-motivated, adaptable, and eager to drive technical excellence and process improvements. Committed to continuous learning and staying ahead of industry trends. The Team You’ll Be A Part Of: You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals. The team thrives on collaboration, technical excellence, and shared success, working in a supportive environment that values creativity, knowledge sharing, and continuous growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74911 Responsibilities Work with a dedicated team, verifying analog and mixed-signal building blocks for SOCs, with a focus on the portable, ultra-low power audio markets. Participate in all aspects of the mixed-signal design verification, in partnership with the design engineering team, to develop and implement a mixed-signal verification infrastructure to verify all functional and performance requirements. Required Experience and Skills 5-10 yrs of relevant industry experience Insatiable curiosity to learn about new circuit architectures to advance ultra-low power audio devices A keen understanding of modern mixed-signal verification challenges and solutions. Solid foundation in network theory, amplifier design and data converters. Experience developing RNM behavioral models using System Verilog/VerilogAMS for analog blocks like analog/digital PLLs, ADCs, DACs, LDOs. Experience developing and maintaining chip level performance simulations of mixed-signal SOC designs. Ability to create and maintained mixed signal verification plans based on early system specifications or incomplete design definitions. Competent in the Cadence Virtuoso environment to setup and execute parameterized simulations of analog and SOC designs. Experienced in producing detailed technical reports and documentation. Experienced in Low-power audio amplifiers (Class D), audio converters, audio interfaces (I2S, PDM), and audio performance metrics (Dynamic Range, SNR, THD) is highly preferred. Experienced in Flow automation using command line scripts using Python, Matlab, Ocean, Perl, Csh, Make, etc. Simulation performance and accuracy trade-offs based on design requirements Experienced in Power-aware mixed-signal verification Hands-on verification of sub-45nm CMOS SOC designs Desired Experience and Skills Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. Work closely with design/verification teams within CPU to develop comprehensive test plan. Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. Verify power intent through use of methodologies like UPF. Work closely with system architects, software teams and Soc team to validate system use cases. Work closely with emulation team to enable verification on emulators and FPGA platforms. Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. BE/BTech degree in CS/EE with 3+ years’ experience. Experience in power management verification. Implementation of assembly and C language embedded firmware. Experience in C/C++, scripting languages, Verilog/system Verilog. Strong understanding of power management features in CPUs and CPU based Socs. Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements Good Understanding of CPU architectures and CPU micro-architectures. In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture Experience with advanced verification techniques such as formal and assertions is a plus Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3073352