2286 Verilog Jobs - Page 8

Were hiring a talented RTL Design Engineer to join our team in Hyderabad and contribute to advanced ASIC/SoC projects. Key Responsibilities: Perform RTL integration for ASIC/SoC designs Debug CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) violations Analyze and resolve timing and CLP (Clock Level Planning) issues Apply strong digital design fundamentals in RTL development Tackle complex design problems with excellent debugging skills Requirements: 3+ years of experience in RTL design and integration Solid foundation in digital logic design Strong problem-solving and debugging abilities

Position: Design Verification Engineer Experience: 48 Years We are looking for a skilled Design Verification Engineer with hands-on experience in MIPI protocols and Display IP. For any queries or further details, feel free to reach me at karthik.adasu@Proxilera.com Responsibilities: Experience in MIPI protocol verification (e.g., MIPI DSI, CSI). Strong hands-on experience in Display IP verification and validation. Ability to develop and execute verification plans targeting display and MIPI components. Perform RTL, gate-level, low-power simulations; ensure ISO 26262 compliance. Build SystemVerilog/UVM testbenches tailored to MIPI and Display IPs. Perform simulation and debug activities for MIPI/Display-related RTL modules. Collaborate with RTL and integration teams to resolve display and MIPI interface bugs. Integrate MIPI and Display IPs into subsystem or SoC-level test environments. Implement protocol-specific checkers, monitors, and assertions. Analyze functional coverage metrics related to display pipelines and MIPI interfaces. Work closely with post-silicon and firmware teams to validate MIPI and display functionality

About the Role We are hiring for an Executive Assistant to the founders at Leap. The primary expectation from this role is to provide real leverage to the founders and make sure that they are insanely productive at what they do. Because productive founders set the benchmark for productivity and performance for the company. The charter for this role will include Perform tasks such as managing calendars, planning travel, and other relevant administrative duties. Prompt coordination among various stakeholders for both internal and external meetings. Follow up on action items and ensure timely closure of all actionables. Leading and ensuring the success of vital cross-functional initiatives with multiple stakeholders. Tracking monthly milestones and setting up reviews for the same across all functions. Ideal Persona 2+ relevant years of experience as an EA to the founder or senior leadership team. Extremely resourceful and great at problem solving. Hands-on, adept at multitasking. Exceptional organizational skills and impeccable attention to detail. High degree of professionalism in dealing with diverse groups of people, including Board members, senior executives, internal team, community leaders, donors.

Job Overview: Experience: 3-15 years Responsibilities: Verification engineer with a knowledge of IP verification or SoC integration verification Experience in SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx integration verification in SoC RTL. Experience in architecting and implementing SV/UVM testbenches, create and maintain reusable verification components Experience in formal verification strategy for complex IP blocks defining properties, driving proofs and coverage closure Your key responsibilities will include writing test plans, defining test methodologies, SystemVerilog/Verilog testbench development, developing UVM or C based software tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills and Experience : Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies UVM/OVM, Formal(jasper), power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of IP or SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures. Porting peripheral driver software Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Experience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures. Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.) Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm

SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Developing best-in-class architecture for Analog Mixed Signal IPs and high-speed parallel PHY interface solutions for next generation NAND flash memory controllers in advanced CMOS technology nodes. Interact with cross-functional teams to define requirements/specs, conceive the optimal solution by evaluating architectures, drive implementation, closely work with layout designers in guiding and reviewing the layouts, ensure timely and high-quality deliverables, extend SOC integration support and review and provide support for post-silicon activities from IP characterization to yield improvement and RMA. Provide good technical leadership in problem solving, planning and mentoring junior and senior engineers. Propose innovative design solutions and design methodologies. Fostering innovation culture and developing efficient processes by adopting state-of-the-art technologies. Qualifications Must have Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Working experience (20+ years) in IO including 5+ years as a project leader S

Where ASIC Digital Design, Staff Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12333 Remote Eligible No Date Posted 22/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished digital design engineer with an unyielding drive for excellence. You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems. With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR, PCIe, USB, or HBM. Your expertise extends beyond individual contribution you are equally comfortable leading and mentoring small teams, fostering an environment of collaboration and shared learning. You are adept at translating functional specifications into detailed micro-architecture and design documents, always ensuring clarity and precision. Your technical toolkit includes mastery of Verilog/SystemVerilog, and you are well-versed in industry-standard flows encompassing linting, CDC analysis, synthesis, and static timing. You re not just a technical expert; you are a proactive communicator, an enthusiastic collaborator, and a natural problem solver who takes initiative and ownership of deliverables. Your ability to adapt to a global, multi-site team environment is matched only by your commitment to continuous learning and professional growth. If you re ready to take on a pivotal role in shaping next-generation silicon IP, Synopsys is where your aspirations and impact can soar. What You ll Be Doing: Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores. Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features. Contributing as an individual designer handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development. Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing. Leading or mentoring small teams of designers, providing technical guidance and fostering professional development. Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies. Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables. The Impact You Will Have: Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide. Elevating Synopsys reputation for technical excellence and innovation in the IP design space. Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies. Enabling customers to achieve faster time-to-market and superior silicon performance. Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth. Driving continuous improvement in design methodologies, enhancing efficiency and product quality. Supporting Synopsys mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions. What You ll Need: Bachelor s or Master s degree in Electrical Engineering, Electronics, VLSI, or related discipline. 5+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM. In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design. Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification. Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces). Familiarity with scripting languages such as Perl or Shell an advantage. Demonstrated ability to technically lead or mentor small teams of engineers. Who You Are: A collaborative team player who thrives in a multi-site, multicultural environment. An effective communicator, able to translate complex technical concepts for diverse audiences. A proactive problem-solver with strong analytical and troubleshooting skills. Self-motivated, showing high initiative and ownership of responsibilities. Adaptable and eager to learn, always seeking opportunities for personal and professional growth. Committed to fostering a positive, inclusive, and innovative team culture. The Team You ll Be A Part Of: You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores. As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design. The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Where Analog Circuit Design Specialist Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12346 Remote Eligible No Date Posted 22/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. Our Silicon Design & Verification business leads the industry in enabling customers to design and verify advanced silicon chips faster and with more reliability. We develop the next-generation processes and models that optimize chips for power, cost, and performance, shaving months off project schedules for our global clientele. We believe in fostering an inclusive and diverse environment where every voice is valued and innovation thrives. You Are: You are a passionate and experienced Analog/Mixed-Signal (A&MS) Circuit Design Engineer with a track record of excellence in high-speed physical interface development. With a deep foundation in CMOS circuit design, device physics, and nanometer technologies, you thrive on solving complex challenges at the intersection of analog and digital domains. You are energized by working on industry-leading projects and are adept at architecting, designing, and validating advanced circuits such as transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends. Your expertise allows you to optimize for performance, area, and power, and you are comfortable with layout considerations and parasitic optimizations. You value diversity and inclusion, recognizing the strength that comes from varied perspectives and backgrounds. You are ready to contribute to a culture of innovation, respect, and excellence helping Synopsys remain at the forefront of the smart everything revolution. What You ll Be Doing: Designing and developing high-speed analog and mixed-signal full-custom circuit macros, including transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends for PHY IPs in advanced CMOS technologies (planar and finFET). Analyzing and implementing various analog circuit techniques to optimize dynamic/static power, enhance performance, and reduce silicon area. Collaborating with global teams to define micro-architectures from specifications and create robust simulation environments for design verification. Performing transistor-level circuit design, simulation, and troubleshooting in nanometer processes, with a focus on reliability and manufacturability. Working closely with layout engineers to optimize parasitics, ensure design closure, and address layout-dependent effects. Participating in design reviews, providing technical guidance, and mentoring junior engineers within a high-performing, diverse team. Adopting and developing automation and scripting to streamline design and verification flows, leveraging languages such as Verilog-A and others as needed. The Impact You Will Have: Advance the state-of-the-art in high-speed PHY IP development, contributing directly to next-generation technology in AI, IoT, 5G, and automotive industries. Enable Synopsys customers to achieve faster time-to-market with optimized, reliable, and high-performance silicon solutions. Drive innovation in low-power and high-speed circuit design, helping customers meet stringent power and area targets. Enhance Synopsys reputation as a global leader in silicon design and verification through technical excellence and customer success. Mentor and elevate the skills of team members, fostering a collaborative and growth-oriented culture. Contribute to a diverse and inclusive workplace, ensuring a wide range of perspectives and ideas inform our solutions. What You ll Need: BE + 5 years or MTech + 4 years of relevant experience in Electrical/Electronics/VLSI Engineering or closely related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron/nanometer methodologies. Hands-on experience in analog transistor-level circuit design for high-speed applications (Multi-Gbps, PAM4 SERDES architectures). Proficiency in SPICE simulations, reliability analysis, and optimizing for layout parasitics. Ability to micro-architect circuits from specifications, set up verification environments, and debug complex analog/mixed-signal circuits. Basic proficiency with automation/scripting languages and familiarity with Verilog-A is a plus. Experience collaborating with cross-site, multicultural teams and strong documentation skills. Who You Are: Innovative thinker with a problem-solving mindset and a passion for continuous learning. Collaborative team player who values diversity, inclusion, and open communication. Detail-oriented, quality-focused, and committed to delivering results on time. Strong interpersonal and mentoring skills, able to guide and support less experienced team members. Adaptable and resilient, comfortable working in a fast-paced, dynamic environment. The Team You ll Be A Part Of: You will join a dynamic, high-performing team dedicated to the design and development of high-speed physical interfaces for advanced semiconductor products. Our team is composed of talented engineers with deep expertise in analog and mixed-signal design, working collaboratively across multiple sites worldwide. We value innovation, knowledge-sharing, and a culture of mutual respect, enabling every team member to grow and contribute to industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Candidate must have completed 03-06 months of training in VLSI. Candidate must have knowledge about: VLSI - Design Verification VLSI - Physical Design VLSI - Hardware VLSI - Analog Circuit Analog (Memory Design/Layout) VLSI - DFT RTL

In today s world of faster and more virtualized servers, storage, and network connections, CPUs cannot keep up with the growing network processing demands. Legacy or foundational network interface cards (NICs) may deliver efficient networking however when running demanding workloads, they cause overhead that burdens CPUs, chewing into available processing power. To deploy more advanced networking capabilities a new generation of intelligent NICs are required to deliver accelerations and additional processing power to offload CPUs. The industry-leading NVIDIA SmartNICs/DPUs (Data Processing Units) provide sophisticated hardware offloads and accelerated networking, storage, security, and manageability services for modern cloud, artificial intelligence, telecommunications and traditional enterprise workloads. With unmatched RDMA over Converged Ethernet (RoCE) performance, NVIDIA SmartNICs/DPUs deliver efficient, high-performance remote direct-memory access (RDMA) services to bandwidth- and latency-sensitive applications. The NBU team in India is a new team that is growing at a fast pace. We are currently seeking an Experienced Verification Engineer with strong verification fundamentals to work in NBU ASIC team. You will join a group of hardworking engineers to implement the next innovative Networking Silicon chip. In this position, youll make a real impact in a multifaceted, technology-focused company while developing the industrys best high-speed communication devices, delivering the highest throughput and lowest latency! What you ll be doing: Be responsible for verifying the smartNIC/DPU designs, architecture and micro-architecture using advanced verification methodologies. You are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems. Use advanced verification methodologies like e-specman, SV-UVM etc. What we need to see: BS / MS (or equivalent experience) with 10+ years of experience in design verification. Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc. ). C/C++ programming/scripting language experience desirable. Ways to stand out from the crowd: Prior experience of smartNIC and/or high-speed interconnects. Strong debugging, problem-solving and analytical skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a phenomenal teammate. Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www. nvidiabenefits. com/ #LI-Hybrid

Role: Functional verification Engineer Skills: UVM,Verilog or SystemVerilog, SOC, ASIC, AMBA Bus Protocols Location: Hyderabad Experience: 4-10 yrs Open Positions: 8 Client: AMD Notice Period- Immediate - 45 Days Skills: amba,systemverilog,soc,verilog,amba bus protocols,functional verification,dv,uvm,asic

Role & responsibilities Design and Development : Develop and implement FPGA architectures and digital circuits using VHDL or Verilog. Write RTL code and testbenches to meet functional and performance requirements. Perform synthesis, place-and-route, and timing analysis to ensure design closure. Simulation and Verification : Simulate designs using tools like ModelSim, Questa, or Vivado Simulator to validate functionality. Create and execute test plans on hardware test benches to verify FPGA designs. System Integration : Collaborate with hardware, software, and system engineers to integrate FPGA designs into larger systems. Debug and troubleshoot FPGA implementations using tools like logic analyzers, oscilloscopes, and JTAG. Optimization : Optimize FPGA designs for speed, resource utilization, and power efficiency. Ensure signal integrity and timing constraints are met for high-speed interfaces. Documentation : Document design processes, specifications, and test results for compliance and future reference. Participate in design reviews and provide technical input. Continuous Improvement : Stay updated with the latest FPGA technologies, tools, and methodologies. Propose and implement improvements to design workflows and processes. Qualifications and Skills : Education : Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Experience : 4-6 years of professional experience in FPGA design, development, and verification. Proven track record of delivering FPGA-based projects from concept to production. Technical Skills : Proficiency in HDL languages (VHDL and/or Verilog/SystemVerilog). Experience with FPGA development tools such as Xilinx Vivado, Intel Quartus, or Microchip Libero. Strong understanding of digital design principles, including timing analysis, signal integrity, and data path optimization. Familiarity with high-speed communication protocols (e.g., PCIe, Ethernet, USB, JESD204B). Experience with simulation tools (e.g., ModelSim, Questa, or VCS). Knowledge of scripting languages (e.g., Python, TCL, or Perl) for automation. Familiarity with embedded systems and hardware-software co-design is a plus. Soft Skills : Strong problem-solving and analytical skills. Ability to work independently and collaboratively in a team environment. Excellent communication skills for technical discussions and documentation Preferred candidate profile Experience in a regulated industry (e.g., aerospace, defence, or medical devices). Knowledge of digital signal processing (DSP) or high-speed digital design. Familiarity with SoC architectures (e.g., Xilinx Zynq, Intel Cyclone) and IP integration. Experience with version control tools (e.g., Git, SVN).

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. Our Silicon Design & Verification business leads the industry in enabling customers to design and verify advanced silicon chips—faster and with more reliability. We develop the next-generation processes and models that optimize chips for power, cost, and performance, shaving months off project schedules for our global clientele. We believe in fostering an inclusive and diverse environment where every voice is valued and innovation thrives. You Are: You are a passionate and experienced Analog/Mixed-Signal (A&MS) Circuit Design Engineer with a track record of excellence in high-speed physical interface development. With a deep foundation in CMOS circuit design, device physics, and nanometer technologies, you thrive on solving complex challenges at the intersection of analog and digital domains. You are energized by working on industry-leading projects and are adept at architecting, designing, and validating advanced circuits such as transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends. Your expertise allows you to optimize for performance, area, and power, and you are comfortable with layout considerations and parasitic optimizations. You value diversity and inclusion, recognizing the strength that comes from varied perspectives and backgrounds. You are ready to contribute to a culture of innovation, respect, and excellence—helping Synopsys remain at the forefront of the smart everything revolution. What You’ll Be Doing: Designing and developing high-speed analog and mixed-signal full-custom circuit macros, including transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends for PHY IPs in advanced CMOS technologies (planar and finFET). Analyzing and implementing various analog circuit techniques to optimize dynamic/static power, enhance performance, and reduce silicon area. Collaborating with global teams to define micro-architectures from specifications and create robust simulation environments for design verification. Performing transistor-level circuit design, simulation, and troubleshooting in nanometer processes, with a focus on reliability and manufacturability. Working closely with layout engineers to optimize parasitics, ensure design closure, and address layout-dependent effects. Participating in design reviews, providing technical guidance, and mentoring junior engineers within a high-performing, diverse team. Adopting and developing automation and scripting to streamline design and verification flows, leveraging languages such as Verilog-A and others as needed. The Impact You Will Have: Advance the state-of-the-art in high-speed PHY IP development, contributing directly to next-generation technology in AI, IoT, 5G, and automotive industries. Enable Synopsys customers to achieve faster time-to-market with optimized, reliable, and high-performance silicon solutions. Drive innovation in low-power and high-speed circuit design, helping customers meet stringent power and area targets. Enhance Synopsys’ reputation as a global leader in silicon design and verification through technical excellence and customer success. Mentor and elevate the skills of team members, fostering a collaborative and growth-oriented culture. Contribute to a diverse and inclusive workplace, ensuring a wide range of perspectives and ideas inform our solutions. What You’ll Need: BE + 5 years or MTech + 4 years of relevant experience in Electrical/Electronics/VLSI Engineering or closely related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron/nanometer methodologies. Hands-on experience in analog transistor-level circuit design for high-speed applications (Multi-Gbps, PAM4 SERDES architectures). Proficiency in SPICE simulations, reliability analysis, and optimizing for layout parasitics. Ability to micro-architect circuits from specifications, set up verification environments, and debug complex analog/mixed-signal circuits. Basic proficiency with automation/scripting languages and familiarity with Verilog-A is a plus. Experience collaborating with cross-site, multicultural teams and strong documentation skills. Who You Are: Innovative thinker with a problem-solving mindset and a passion for continuous learning. Collaborative team player who values diversity, inclusion, and open communication. Detail-oriented, quality-focused, and committed to delivering results on time. Strong interpersonal and mentoring skills, able to guide and support less experienced team members. Adaptable and resilient, comfortable working in a fast-paced, dynamic environment. The Team You’ll Be A Part Of: You will join a dynamic, high-performing team dedicated to the design and development of high-speed physical interfaces for advanced semiconductor products. Our team is composed of talented engineers with deep expertise in analog and mixed-signal design, working collaboratively across multiple sites worldwide. We value innovation, knowledge-sharing, and a culture of mutual respect, enabling every team member to grow and contribute to industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 8 - 15 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid #DVT

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical design and execution issues related to physical verificationand sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/cores. Good hands on Calibre, Virtuoso etc. Requirements : Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Expertise in physical verification of Block/Partition/ Full-chip-level DRC, Experience and understanding of all phases of the IC design process from RTL-GDS2. LVS, ERC, DFM Tape out process on cutting edge nodes, Preferably worked on 3nm/5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in debugging LVS issues at chip-level/block level with complex analog-mixed signal IPs Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.) Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc. Experience with ERC rules and ESD rules has an added advantage Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to Engineer and mentor junior engineers, fostering their professional growth and development. Preferred qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Proven track record with multiple successful final production tape-outs Proven ability to independently deliver results and be able to work hands-on as and guide/help peers to deliver their tasks Be able to work under limited supervision and take complete accountability. Excellent written and verbal communication skills Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration and Physical verification challenges.

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

Job Description: We are hiring an RTL Design Engineer with hands-on experience in FPGA-based RTL development. This role is focused on FPGA logic design and does not involve Silicon RTL or hardware testing . Key Responsibilities: RTL coding using Verilog, SystemVerilog, or VHDL Work on FPGA architecture and flow , including logic and digital design Scripting with Tcl and Python Perform synthesis and design stages using Vivado Collaborate with design teams to deliver high-quality IP blocks for FPGA

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Design. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Synthesis. Experience: 3-5 Years.

ASIC RTL DESIGN ENGINEER (4 to 10 Years) IP/SoC Design Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune/Chennai/Noida] Experience: 4 to 10 Years Openings: 6 Positions Job Description Sr RTL Design Engineer We are seeking a seasoned RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in designing state of the art solutions for automotive camera and display systems. Responsibilities Microarchitecture definition and RTL implementation ensuring optimal performance, power, area. Collaborate with software teams to define configuration requirements, verification collaterals etc. Work with verification teams on assertions, test plans, debug, coverage etc. Proficiency in Verilog/System Verilog Very google understanding of ASIC design methodologies Qualifications and Preferred Skills Graduate/Post Graduate/PhD in Electrical/Electronics 4-10 years hands-on experience in microarchitecture and RTL development Proficiency in developing micro-architecture from the design requirements, defining the H/W- S/W interface. In-depth understanding of MIPI CSI and DSI protocols Experience designing IP blocks for video and audio design Proficiency in Verilog, System Verilog Familiarity with industry-standard EDA tools and methodologies Experience with large high-speed, pipelined, and low power designs Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Experience in designs complying to automotive functional safety will be a plus

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with Physical design to close SDC related timing issues. Analysis of timing from synthesis to verify constraints. Work with architects and logic designers to generate block and full chip timing constraints. Analyse scenarios and margin strategies with Synthesis & Design team. Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints. Work with third party IP, derive timing signoff requirements. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Total 4+ years of experience in STA, timing closure related work. Hands-on experience in ASIC timing constraints generation and timing closure. Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST. Deep understanding and experience in various functional and test modes. Good fundamental on Physical design implementation. Validate timing constraints for Block and Partitions. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Ability to work cross-functionally with various teams and be productive under aggressive schedules. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Preferred Qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Has at least worked on full chip STA closure of large size silicon. Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration. Familiarity with low-power design techniques and methodologies, such as multivoltage domains and power gating using UPF

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

This job might be for you if You enjoy solving problems. You love taking on difficult challenges and finding creative solutions. You dont know the answer but will dig until you find it. You communicate clearly. You write well. You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference. You can impress our customers with your enthusiasm to solve their issues (and solve them!) Job Description Required Solid RTL coding experience including Microarchitecture of design System Verilog and Verilog coding using provided coding styles. Understanding of SDC Understanding STA reports and how to adjust RTL accordingly. Designing for error cases and debug of IP Understanding of CDC logic Knowledge of lint rules and exceptions Design and use of block level simulations to bring up IP. Knowledge of AMBA buses and when to use them. Job Description Preferred Experienceleading small design team. C coding / Firmware skills Knowledge on common processor architectures(ARM, RiscV) FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA. Lab brings up experience, scripting. Relevant tool experience such as: Socrates, Core Consultant in additionto standard simulation tools (xcellium, vcs, etc) Emulation experience(Zebu, Palladium, etc) Board knowledge, component selection, probing, debug. JTAG debugging experience (Coresight, Lauterbach, etc). Low power design techniques Qualifications E./B.Tech. degree at minimum.

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Work with the team on Verilog RTL and scripted flow implementation of the specified Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design. Work with the team on Verilog testbench implementation of the specified verification tests for DFT features and use case. Work with the team on automation scripts intended for robustness of implementation quality and improvement of efficiency. Minimum Qualifications: Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 2 to 4 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Preferred Qualifications: VLSI circuit physical behaviors in silicon (electrical migration, temperature/voltage variation effects). Basic timing concepts, including setup and hold, metastability. Some EDA tools usage experience Strong verbal communication skills and ability to thrive in a dynamic environment Scripting/coding language: Tcl, Python, Perl, or c/c++. Why Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re "old" (36 years strong) and only about hardware, but we’re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can’t put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it). Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us!

Urgent Opening for Canvendor Hiring: Design Verification -ARM (5+ Years Experience) | Bangalore and Hyderabad | Location: Bangalore& Hyderabad, India Experience: 5+ Years Notice period: Immediate to 30days Key Requirements: Strong experience in ARM based SOC and ARM based SS level Design verification . Must have worked on ARM based SOC viz Cortex A or M series based SOC Experience in Multi processor based ARM cpu is plus Coresight Debug knowledge – coresight is plus : ARM SoC based debug infrastructure including CoreSight infrastructure (implementation and/or validation). Strong debug skills with AXI/AHB/APB, memory, and NoC components. Strong work experience in AMBA – AXI/AHB protocol-based NOC , Understanding/ experience in CHI/ACE is plus Strong skills/Proficiency in System Verilog, UVM Strong work experience(Advanced skills ) in SV-UVM and/or C based verification. Working knowledge in TB/Checker/SB development is plus. Must posses strong SV/UVM debugging Proficiency in C/C++ modelling. GLS experience is a plus; Should have worked on handling regressions – RTL /GLS simulations and should possess excellent debugging skills Must be proactive, independent, and capable of strong simulation debug. Work Experience or Strong knowledge in Memory SS verification - LPDDR5/LPDDR4/DDR protocols or HBM is plus Work experience in PCIe/CXL and other similar complex protocol like Ethernet is plus Scripting knowledge – python, perl if worked is plus and should possess working knowledge in updating/fixing flow/pre or post processing scripts If interested kindly share your updated CV to irfanai@canvendor.com