Dear Candidate We have immediate job openings for Design verification openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Develop and maintain UVM-based verification environments. Define and review verification test plans with architecture and design teams. Perform design verification using directed and constraint-random tests. Maintain regression runs and debug test failures with designers. Report and analyze verification coverage metrics. Drive verification to achieve full coverage goals. Own verification of IP blocks, sub-systems, and top-level environments. Thanks Gayathri
Dear Candidate We have immediate job openings for Analog layout and design openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Analog layout exp Skills Required: Analog Layout design and IO design Good to Have: Exposure to Analog layout, EDA tools Thanks Gayathri
To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. • Leading a project for AMS requirements is a value add. • Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools • Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. • Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) • Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus • Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected • Experience working on AMS Verification on multiple SOC’s or sub-systems • Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus • Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment • Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations • Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. • Develop and execute top-level test cases, self-checking test benches and regressions suites • Developing and validating high-performance behavior models • Verifying of block-level and chip-level functionality and performance • Team player with good communication skills and previous experience in delivering solutions for a multi-national client • Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience • Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc. • Ability to extract simulation results, capture in a document and present to the team for peer review • Supporting silicon evaluation and comparing measurement results with simulations • UVM and assertion knowledge would be an advantage
1. Strong coding with Verilog and SystemVerilog 2. Good knowledge of AHB,AXI, AMBA protocol, exp in Ethernet 3. Many experiences with sequence creation, functional cover groups and assertion coding. 4. Strong C/C++ software development experiences 5. Be familiar with scripting language, such as Perl, C shell, Makefile, Ruby.
Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. • Contribute to effective project-management. • Effectively communicating with Local engineering teams to assure the success of layout project. Educational Background • BE or MTech in Electronic/VLSI Engineering • 5 + year experience in analog/custom layout design in advanced CMOS process.
You will work in the AMS Verification domain, requiring relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is considered a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools is essential. You should have knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles. Analog circuit basics understanding is necessary, and previous analog design experience would be a plus. You should be familiar with the concepts of behavioral modeling, including digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from a mixed signal perspective is advantageous. Functional knowledge of analog and mixed signal building blocks such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Previous experience working on AMS Verification on multiple SOCs or sub-systems is required. Working knowledge of Perl/Skill/Python/Tcl or other scripting relevant languages would be beneficial. You must possess the ability to lead a project team and work collaboratively in a multi-site development environment. Being delivery-oriented, passionate to learn and explore, transparent in communication, and flexible related to project situations is important. A good knowledge of analog and mixed signal electronics, test-plan development, tools, and flows is necessary. You will be responsible for developing and executing top-level test cases, self-checking test benches, and regression suites. Additionally, you will develop and validate high-performance behavior models and verify block-level and chip-level functionality and performance. Being a team player with good communication skills and having previous experience in delivering solutions for a multi-national client is valuable. You should be fluent with Cadence-based flow, creating schematics, Simulator/Netlist options, etc. Ability to extract simulation results, capture them in a document, and present them to the team for peer review is required. Supporting silicon evaluation and comparing measurement results with simulations is part of the role. Having UVM and assertion knowledge would be an advantage.,
1. Strong coding with Verilog and SystemVerilog 2. Good knowledge of AHB,AXI, AMBA protocol, exp in Ethernet 3. Many experiences with sequence creation, functional cover groups and assertion coding. 4. Strong C/C++ software development experiences 5. Be familiar with scripting language, such as Perl, C shell, Makefile, Ruby. Show more Show less
Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Excellent problem-solving skills in physical verification of custom layout. Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. Contribute to effective project-management. Effectively communicating with Local engineering teams to assure the success of layout project. Educational Background BE or MTech in Electronic/VLSI Engineering 5 + year experience in analog/custom layout design in advanced CMOS process. Show more Show less
To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected Experience working on AMS Verification on multiple SOCs or sub-systems Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. Develop and execute top-level test cases, self-checking test benches and regressions suites Developing and validating high-performance behavior models Verifying of block-level and chip-level functionality and performance Team player with good communication skills and previous experience in delivering solutions for a multi-national client Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc. Ability to extract simulation results, capture in a document and present to the team for peer review Supporting silicon evaluation and comparing measurement results with simulations UVM and assertion knowledge would be an advantage Show more Show less
Greetings from ||Thundersoft|| We are looking for Cutsom Layout engineers with an exposure of Custom layout and having experience in GF 22nm FDSOI technology node
Greetings from ||Thundersoft|| Key Responsibilities: Define and develop micro-architecture for complex digital blocks and/or SoC subsystems. Develop synthesizable RTL using Verilog/SystemVerilog for new designs and enhancements. Own end-to-end design tasks including coding, linting, CDC, SDC generation, and synthesis. Perform RTL integration of IP blocks and subsystems into the top-level SoC. Collaborate with verification, DV, and validation teams to drive high-quality designs. Work with the physical design team to address timing, area, and power goals. Contribute to design documentation, design reviews, and support silicon bring-up. Lead or mentor junior team members as needed. Interface with cross-functional teams including software, DFT, and systems architecture. Required Qualifications: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 10+ years of experience in ASIC RTL design and development. Expert in RTL coding (Verilog/SystemVerilog) and digital design principles. Strong knowledge of SoC architecture, bus protocols (AXI, AHB, APB), and memory subsystems. Experience with synthesis, timing constraints (SDC), and understanding of STA. Proficient in tools such as Synopsys Design Compiler, VCS, Spyglass, etc. Deep understanding of low-power design techniques, clock gating, power domains (UPF). Familiarity with simulation and debugging tools.
||Greetings from Thundersoft || Key Responsibilities: Perform IP-level verification for PCIe Gen6/Gen5 using SystemVerilog (SV) and UVM methodologies. Develop test plans, build testbenches, write test cases, and implement functional coverage. Verify and debug MAC and Transport layers of PCIe protocol. Collaborate with cross-functional teams (design, architecture, firmware). Ensure compliance with protocol specifications and performance goals. Required Skills : 10+ years of experience in IP-level verification . Strong hands-on expertise in SV/UVM-based verification. Solid understanding of PCIe Gen6 and/or Gen5 , particularly MAC and Transport layers . Proficient in debugging, simulation tools, and scripting (Python/Perl/TCL). Excellent communication and teamwork skills.
Exciting Hybrid Opportunity at ThunderSoft, Bengaluru, India. Join our Sales/Key Account Executive team at ThunderSoft, a global leader in semiconductor and embedded services. We are seeking fresh graduates and early-career professionals to join our dynamic team. Your Role: - Manage and support semiconductor client accounts - Develop impactful presentations and proposals - Schedule meetings and enhance client engagement - Collaborate with global teams and travel as required - Progress into a rewarding career in sales and account management Who Can Apply: Ideal for freshers with 1-5 years of experience in engineering or an MBA background. Must be skilled in MS PowerPoint and client communication, with a passion for proactive engagement and willingness to travel.
Role and Responsibilities: 1. Collaborate with design and architecture teams to understand SoC design and create validation plan to uncover Si issues 2. Develop and maintain firmware for CPU for functional bring up and validation 3. Debug Silicon issues in collaboration with HW teams to identify root cause. Skill Requirements: 1. Experience in Si bring up and pre-Si or post Si validation 2. Excellent C programming skills 3. Experience in Si debug using T32, JTAG and awareness of debug methodologies Good to have: 1. Experience in bringing up CPU on Post Si and on emulation 2. Knowledge of SoC architecture, ARM architecture and boot flows 3. Experience on firmware development for bare metal platform Experience: 5+ years of experience in Si validation and firmware development
Greetings from ThunderSoft India Pvt Ltd !! ThunderSoft is the world's Leading Intelligent Platform Technology Provider. Head Quartered in Beijing, China, we have a presence in more than 20 cities across the globe. We service more than 1000 customers and have 600+ patents to our name. ThunderSoft Bangalore is currently hiring for Wlan Develope r, please find the below details. Required Skills:: • 3-7years of experience in WLAN driver or Networking driver or Networking/WLAN protocol development • Hands on experience working in the Linux kernel & Linux kernel device drivers. • Strong C programming skills • Good WLAN 802.11a/b/g/n/ac/ax/be knowledge would be a strong plus. • Hands on experience in Wireless LAN driver development is preferred • Strong Linux internals and drivers skills would be preferred. • Knowledge of common interfaces, such as USB, MII, PCI/e would be a plus. • Hands on experience in solving complex system issues with good problem solving skills would be a plus. • Good knowledge of basic network protocols such as TCP/UDP/IPv4/IPv6/ARP/DHCP will be plus Interested candidates share your resumes to swathi.v@thundersoft.com
Testing of WLAN(802.11 a bgn ac ax) chipsets. The role involves test planning, automation, execution, triage and raising bugs. Person should in-depth WLAN , Coexistence Protocol knowledge and should able to differentiate whether it is automation, DUT or setup and raise bug accordingly. Skills/experience: Wi-Fi , WLAN 802.11( a bgn ac ax) , BT+WLAN Coexistence, Automation Responsibilities: Candidates will be responsible for testing and verifying WLAN & Coexistence technology operation in conjunction with complex digital modem ASIC products supporting UMTS and 1x/EVDO technologies. The candidate are expected to excel by doing first level of debugging and analysis of problem. Will conduct engineering tests and detailed experimental testing to collect data to expedite localization of the problem. They will be involved in profiling and performance optimizations. The candidate will also be responsible for automating these test cases using scripting languages(Perl, etc.,). Flexibility in work assignments and ability to multi-task is crucial.
Job description: Software Developer for WLAN work from HOST side which can work on DATA path , Control and middleware code. Need C-linux knowledge , known about WLAN protocol. Basic Data structure , Basic debugging via JTAG and T32
Job description: Strong knowledge and experience in Camera HAL development and Android camera frameworks. Strong C & C++ programming and debugging skills required. Strong knowledge in operating system fundamentals like virtual memory, CPU scheduling, process states, synchronization, etc. Strong knowledge in concepts like RTOS, RAM/Cache, Interrupt handling, etc applied to embedded systems. Hands on experience in real time issues like memory/stack corruption, ANR, deadlocks, race conditions, etc. Strong communication skills - Able to understand and explain highly technical information in a clear and concise manner. Willing to travel to customer sites and other Qualcomm office locations to co-develop next-generation smartphones,
Job description: Strong knowledge and experience in Camera HAL development and Android camera frameworks. Strong C & C++ programming and debugging skills required. Strong knowledge in operating system fundamentals like virtual memory, CPU scheduling, process states, synchronization, etc. Strong knowledge in concepts like RTOS, RAM/Cache, Interrupt handling, etc applied to embedded systems. Hands on experience in real time issues like memory/stack corruption, ANR, deadlocks, race conditions, etc. Strong communication skills - Able to understand and explain highly technical information in a clear and concise manner. Willing to travel to customer sites and other Qualcomm office locations to co-develop next-generation smartphones,
Job description: Understand customer requirements clearly (in BSP/Kernel/Drivers areas) and provide regular updates/follow-ups on time. Collaborate with multiple BSP/Kernel subsystems and Linux Application Frameworks (sysinit, systemd, etc.) teams globally and proactively drive tasks to closure. The job requires extensive knowledge and experience in :Core BSP,Bootloader,Core Linux,Kernel subsystems Linux Application Frameworks (sysinit, systemd) Strong kernel-level C programming skills. Good understanding of Linux OS concepts and Linux Kernel internals. Mandatory experience in Linux Kernel/driver areas and bootloader exposure such as PBL, SBL, UEFI, LK, etc. Excellent low-level system debugging skills with the ability to identify the exact root cause. Ability to quickly browse and understand complex Linux Kernel/Driver code flow. Familiarity with reviewing Device Data sheets, Schematics, Specifications, and Hardware.