Design Verification Engineer-Hyderaba/Bangalore/Chennai

Dear Candidate ,

Greeting from HCL Tech!!!!!!!

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We are hiring on below Design Verification Engineer - Engineer/Lead/Senior Lead . Please find the JD Details below - Please share us your details below in Table with your update resume.

JD - Design Verification Engineer - Engineer/Lead/Senior Lead

Qualifications:

• Bachelors degree in electrical engineering, Computer Engineering, or a related field (masters degree a plus)
• Experience in design verification for ASICs or SoCs
• Strong understanding of digital design principles (combinational logic, sequential logic)
• Proven ability to develop and debug complex verification environments
• Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM)
• Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus
• Excellent analytical and problem-solving skills
• Strong communication and collaboration skills to work effectively in a team environment
• In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines)
• Proven ability to develop, debug, and optimize complex verification environments
• Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal)
• Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl)
• Experience with formal verification tools and techniques is a plus
• Excellent analytical and problem-solving skills with a meticulous attention to detail
• Strong communication, collaboration, and leadership skills to effectively contribute and guide the team

Benefits:

• Competitive salary and benefits package
• Opportunity to work on leading-edge technologies and projects
• Collaborative and dynamic work environment
• Potential for professional development and career advancement

Please fill the details in below table

Full Name (As per Passport/10th Class )

Highest Qualification(Distance/Regular)

Total Exp

Years

Relevant Exp

Years

Design Verification Engineer(Please specify)

Years/Months

Exp ASIC

Years/Months

Exp SOCS

Years/Months

Exp simulation tools : Please specify tools exp, which you hold

Years/Months

Exp scripting languages

Years/Months

Exp digital design principles

Years/Months

Exp verification methodologies (e.g., UVM)

Years/Months

Exp Verilog or VHDL

Years/Months

Mobile Number –

Alternate Mobile Number –

Mail ID

Alternate Mail ID

CTC

ECTC (Please share expectation in number not in % or as per standards)

Notice Period(Buyout options/on Bench/Currently serving(Please specify lwd)

Current Company

Current Location

Have you attend Interview at HCL-

Have you worked for HCL if Yes(Please share EX- HCL EMPID- Duration )

Preferred Location

Reason for leaving

Holding any offers /Any Pipeline :