Posted:4 days ago|
Platform:
On-site
Full Time
Develop scalable and reusable System Verilog/UVM based environments
Define and implement test plans for functional coverage performance and corner-case analysis
Collaborate with design teams to debug and resolve challenging logic and protocol-level issues
Work with high-speed interconnects and protocols such as AXI, CHI, PCIe, Ethernet, CXL, and UCIe
Drive verification strategy including automation regression setup and coverage closure
Mentor junior engineers and guide cross-functional technical discussions.
✅ Preferred Experience
Deep hands-on expertise in SoC/NoC-level verification
Strong debug skills using waveform tools and log analysis
Exposure to power/performance optimization and metrics-driven verification
Proven experience working in complex testbench architectures
💡 Broadest Portfolio of AI Solutions
From CPUs and GPUs to adaptive computing platforms, offers the industry’s most complete suite of AI-enabling technologies-optimized for edge cloud and endpoint workloads
🌐 Open Ecosystem Philosophy
Their commitment to open standards and strategic co-innovation fosters maximum flexibility long-term scalability and compatibility across the global tech landscape
🚀 Proven Innovation Leadership
With breakthroughs like chiplet architecture 3D stacking and AI accelerators the company consistently delivers best-in-class TCO energy efficiency and performance leadership across industries
Proxelera
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