Verification Lead

Job Description — Design Verification Engineer -Senior Level

Job Title: Lead Design Verification Engineer

Location: Bangalore

Experience: 8 – 15 years

Employment Type: Full-time

Department: Digital SoC / IP Verification

Position Overview

We are seeking highly motivated and experienced Design Verification Engineers with strong hands-on experience in SoC-level, Subsystem, and IP-level verification. The ideal candidate should have deep expertise in testbench architecture, UVM-based verification, and debugging complex test environments, along with proven skills in assertions, functional coverage closure, and regression management.

Key Responsibilities

Verification Architecture & Planning

Develop and execute verification plans based on design and micro-architecture specifications.

Define and implement testbench architecture and verification strategy for IP, subsystem, and SoC-level environments.

Participate in verification reviews (test plans, coverage goals, sign-off criteria).

Testbench & Environment Development

Build UVM-based reusable verification environments from scratch.

Develop and integrate testbench components (drivers, monitors, agents, scoreboards, reference models).

Ensure scalability and configurability of the verification environment for multi-IP and SoC usage.

Test Case Development & Debug

Write directed, random, and constrained-random test cases in System Verilog/UVM.

Debug simulation failures, identify design or testbench issues, and collaborate with RTL teams for resolution.

Maintain regression infrastructure and triage failures to ensure daily stability.

Assertions, Coverage & Sign-off

DDR, DDR-PHY is a plus

Develop and integrate System Verilog Assertions (SVA) for functional and protocol checks.

Define functional coverage models and drive coverage improvement and closure.

Participate in coverage reviews and ensure verification completeness before RTL sign-off.

SoC-Level & Subsystem Verification

Drive integration-level verification, including interconnects, memory subsystem, and interface validation.

Please share your profiles to jhansi.bv@leadsoc.com for further discussion.