964 Uvm Jobs - Page 3

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Highly skilled SystemC Modeling Engineer is required to join dynamic and innovative NoC Systems team in Qualcomm Bangalore Design Center. The ideal candidate will have a strong background in digital design and a deep understanding of SystemC for hardware modeling and simulation. This role involves developing and maintaining high-quality SystemC models for complex digital systems, collaborating with cross-functional teams, and ensuring that Qualcomm products meet the highest standards of performance and reliability. Key Responsibilities: Model Development: Design and implementation of SystemC models for digital systems, including processors, memory controllers, and peripheral interfaces. Methodology Awareness of Virtual prototypes and Performance modeling using C++/SystemC/TLM 2.0. Approximately timed and Loosely Timed(LT) style of coding for software development when using Virtual Prototype Verification: Development and executution of testbenches to verify the correctness and performance of SystemC models. Optimization: Optimization of models for simulation speed and resource efficiency. Documentation: Creation and maintenance of detailed documentation for models, testbenches, and verification plans. Collaboration: Work closely with hardware and software engineers to ensure seamless integration of SystemC models into the overall system design. Troubleshooting: Identify and resolve issues in the modeling and simulation process. Research: Stay updated with the latest advancements in SystemC and digital design techniques. Technical Skills Proficient in SystemC and C++. Strong understanding of digital design principles and techniques. Experience with hardware description languages (HDLs) such as Verilog is a plus. Familiarity with simulation tools and environments is a plus. Soft Skills Excellent problem-solving and analytical skills. Strong communication and collaboration abilities. Ability to work independently and in a team environment. Attention to detail and a commitment to quality. Preferred Skills Experience with Network-on-chip, high-performance computing and parallel processing. Knowledge of ASIC design. Familiarity with scripting languages (e.g., Python, Perl). Experience with version control systems (e.g., Git). Qualifications: Education: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 5 to 10 years of experience in digital design and SystemC modeling. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Principal Design Verification Engineer Job Overview MIPS is seeking a highly experienced Senior Staff Design Verification Engineer with over 15 years of industry experience to lead verification efforts focused specifically on Coherency Manager and Cache Controller components. The successful candidate will have extensive hands-on experience utilizing advanced verification methodologies, including constrained random testing, formal verification, and coverage-driven verification. This senior role involves close collaboration with CPU architects, designers, and cross-functional global teams to ensure high-quality, high-performance processor designs. Key Responsibilities Lead and drive verification activities for Coherency Manager and Cache Controller IP to closure. Collaborate closely with design teams and architects to thoroughly understand and interpret microarchitectural and functional specifications. Develop comprehensive verification plans and execute these plans through testbench creation, test case development, and rigorous analysis. Create directed and constrained random test cases in SystemVerilog, Assembly, and C to verify complex coherency and cache management behaviors. Employ formal verification techniques to augment random verification and ensure exhaustive coverage. Analyze verification coverage metrics to identify and close coverage gaps efficiently. Automate and optimize verification flows and regression environments using scripting languages like Python, Perl, TCL, or Shell. Mentor junior verification engineers, providing technical guidance and leadership within the verification team. Qualifications Master`s degree or higher in Electronics, Electrical, Computer Engineering. 15+ years of relevant verification experience, specifically in CPU or complex SoC verification. Proven expertise in verification of Multicore and Multicluster Coherency, Cache Controllers, or similar blocks. Deep knowledge and practical experience with verification methodologies such as UVM, constrained random, and formal verification. Proficiency in SystemVerilog, Verilog, C, C++, and Assembly. Solid understanding of interconnect and coherency protocols such as AXI, ACE, OCP, CHI. Strong scripting skills in Python, Perl, TCL, or Shell. Experience with CPU architectures, particularly RISC-V, ARM, or MIPS. Preferred Experience Experience with RISC-V architecture. Familiarity with functional safety standards (e.g., ISO 26262). Prior exposure to FPGA prototyping and emulation platforms. What MIPS Offers Opportunity to be part of a dynamic team creating industry-leading RISC-V processors. Autonomy with extensive support from industry experts. Opportunities for significant career growth and technical advancement. Competitive compensation and comprehensive benefits package About MIPS MIPS is a pioneer in RISC-based computing with a legacy of innovation in high-performance microprocessor design. Today, MIPS continues this legacy by leading the adoption and advancement of the RISC-V architecture, delivering scalable processor solutions for cutting-edge computing applications.

You are a passionate and innovative engineer with a strong foundation in digital and analog design You have a knack for developing complex arithmetic and logic operations and are adept at translating algorithmic flowcharts into pseudo code Your background in Electrical Electronics Engineering, Electronics and Telecommunication Engineering, or a related field has equipped you with the skills necessary to excel in high-speed serial link design and verification You thrive in a collaborative environment and have a continuous improvement mindset, always eager to learn and grow Your knowledge of hardware description languages like Verilog and SystemVerilog, combined with your understanding of protocols such as PCIe and IEEE8023, makes you a valuable asset to any team You are ready to take on challenges and contribute to the success of cutting-edge technology What Youll Be Doing: Designing and verifying high-speed serial links for inter and intra chip communication Developing finite state machines for complex digital and analog operations Translating algorithmic flowcharts into efficient pseudo code Conducting functional verification using methodologies like UVM, OVM, and VMM Collaborating with cross-functional teams to ensure design and verification accuracy Staying updated with the latest industry protocols and standards to meet technical requirements The Impact You Will Have: Enhancing the performance and reliability of high-speed data transfer systems Contributing to the development of innovative technologies that shape the future of connectivity Ensuring the successful integration of high-speed serial links in various applications Improving product quality and efficiency through rigorous design and verification processes Setting new benchmarks in the industry for data transfer speed and reliability Driving continuous improvement and innovation within the team and organization What Youll Need: 2-3 yrs with Bachelors or Masters degree in Electrical Electronics Engineering, Electronics and Telecommunication Engineering, or a related field Strong fundamentals in digital and analog design Proficiency in hardware description languages, especially Verilog and SystemVerilog Experience with functional verification methodologies like UVM, OVM, and VMM Knowledge of high-speed serial data protocols such as PCIe and IEEE8023 Who You Are: Innovative and passionate about technology Detail-oriented with strong problem-solving skills Collaborative and team-oriented Adaptable and eager to learn new skills Effective communicator with the ability to convey complex ideas clearly The Team Youll Be A Part Of: You will be part of the Solutions Group (SG) at Synopsys India Pvt Ltd, a team of experts dedicated to pushing the boundaries of high-speed serial link design, verification, validation, and packaging This team is committed to meeting industry standards and protocol requirements, ensuring our consumer and enterprise products lead the market in performance and reliability

Must Have: SV/UVM, Test Bench Development , Any Protocols Must be able to own and drive the verification of a block / subsystem or a SOC. Must have extensive experience in verification Share resume to mansoor@hisoltech.com

THE PERSON: You will have strong analytical/problem solving skills, high attention to detail, and motivation toindependently drive tasks to completion. You will also have professional interpersonal and communication skills.If this sounds like a role you are interested in, we welcome you to apply! KEY RESPONSIBILITIES: Development and verification of embedded firmware for SOC secure boot and embedded microprocessor driven hardware acceleration services for cryptography, decompression and large scale DMA functions. Hardware/Firmware co-verification in UVM System Verilog and C-DPI structured testbench. Hardware/Firmware co-verification in FPGA hardware prototype platform. Develop and maintain subsystem verification architecture, testbench, test methodology for Embedded CPU and subcomponent IPs with AXI/AHB busses and HW accelerators such as Cryptography, Data Compression, DMA, etc Participate in subsystem specification, influence IP micro-architecture development (HW and FW co-design and verification aspect), develop and verify abstracted performance model Create abstracted FW and HW performance models Develop critical target code to collect IP performance key parameters Explore subsystem architecture performance trade-off for FW and HW optimization Develop and execute subsystem and block level test plans Develop FW/HW co-verification methodology Develop UVC and System Response models Develop and debug UVM and C-DPI test cases with integrated FW Improve verification metrics Further develop subsystem and block level testbenches using UVM randomized test methodology and C-DPI directed test methodology. Develop and maintain subsystem level integration scripts Develop and maintain subsystem testbench build and test run scripts Drive to verification metrics closure Interface with SoC integration and SoC DV teams Define and develop IP level DV API to support SoC level DV effort Develop and maintain IP build and delivery infrastructure to support SoC level integration of SMU IPs. Support SoC level IP emulation, silicon bring-up and debugging effort PREFERRED EXPERIENCE: ASIC FW and HW design and verification experience Proficient in C, C++, Assembly, Verilog, System Verilog, and several scripting languages (Make, Perl, Python, etc) Excellent knowledge about UVM methodology and C-DPI methodology Excellent knowledge about standard bus/interface protocols (ie AXI, AHB, AMBA) Excellent experience with firmware design on commercial microprocessors Excellent experience with microprocessor tool chain, compiler, assembler, debugger Excellent experience with ASIC verification tools, simulation, linting, power aware simulation, etc ACADEMIC CREDENTIALS: Major in Electrical or Computer Engineering. B.Eng or masters or PhD Degree preferred.

THE ROLE: We are looking foran adaptive, self-motivative design verification engineer to join our growing team. As a key contributor,you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. TheVerification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functionalperformance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: Good at C/C++ FamiliaritywithSystemVerilogand modern verification libraries like UVM Experience/Background on Computing/Graphics is abenefit Experience with OpenGL/OpenCL/D3D programming is abenefit ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

As a Functional Verification Engineer at AMD in Hyderabad, you will be responsible for verifying the functionality of complex System on Chip (SOC) designs using industry-standard verification methodologies. With 4-10 years of experience, you will play a key role in ensuring the quality and reliability of ASIC designs. You should be proficient in UVM (Universal Verification Methodology) and have a strong command of Verilog or SystemVerilog. Additionally, knowledge of AMBA Bus Protocols is essential for this role. Your expertise in functional verification, design verification (DV), and ASIC verification will be crucial in meeting the verification goals of the projects. Working closely with cross-functional teams, you will have the opportunity to contribute to cutting-edge technologies and innovative solutions. This position requires immediate to 45 days notice period availability. If you are passionate about verification engineering and have a solid foundation in AMBA, SystemVerilog, SOC, Verilog, and other relevant skills, we invite you to join our team at AMD and be part of our dynamic work environment. Join us in shaping the future of technology with your verification expertise.,

As a Verification Engineer, you will be responsible for developing and implementing comprehensive verification plans using industry-standard methodologies such as UVM. Your role will involve designing and writing robust verification environments (testbenches) to achieve high code coverage. Utilizing simulation tools like ModelSim, Cadence Incisive, and Synopsys VCS will be essential for verifying RTL functionality. You will play a crucial part in debugging and analyzing verification failures to identify the root cause of design issues. Collaboration with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements will be a key aspect of your responsibilities. Additionally, your involvement in code reviews and ensuring adherence to verification coding standards will be significant. Staying up-to-date with the latest verification tools and methodologies will be crucial for your continuous growth and success in this role. Qualifications required for this position include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (a Master's degree is a plus). You should have 5-7 years of experience in design verification for ASICs or SoCs. A strong understanding of digital design principles, including combinational logic and sequential logic, is essential. Your proven ability to develop and debug complex verification environments, proficiency in Verilog or VHDL, and experience with verification methodologies like UVM will be highly valued. Experience with simulation tools and scripting languages such as Python and Perl would be advantageous. Excellent analytical and problem-solving skills, along with strong communication and collaboration abilities to work effectively in a team environment, are qualities that will contribute to your success in this role.,

You will work in the AMS Verification domain, requiring relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is considered a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools is essential. You should have knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles. Analog circuit basics understanding is necessary, and previous analog design experience would be a plus. You should be familiar with the concepts of behavioral modeling, including digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from a mixed signal perspective is advantageous. Functional knowledge of analog and mixed signal building blocks such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Previous experience working on AMS Verification on multiple SOCs or sub-systems is required. Working knowledge of Perl/Skill/Python/Tcl or other scripting relevant languages would be beneficial. You must possess the ability to lead a project team and work collaboratively in a multi-site development environment. Being delivery-oriented, passionate to learn and explore, transparent in communication, and flexible related to project situations is important. A good knowledge of analog and mixed signal electronics, test-plan development, tools, and flows is necessary. You will be responsible for developing and executing top-level test cases, self-checking test benches, and regression suites. Additionally, you will develop and validate high-performance behavior models and verify block-level and chip-level functionality and performance. Being a team player with good communication skills and having previous experience in delivering solutions for a multi-national client is valuable. You should be fluent with Cadence-based flow, creating schematics, Simulator/Netlist options, etc. Ability to extract simulation results, capture them in a document, and present them to the team for peer review is required. Supporting silicon evaluation and comparing measurement results with simulations is part of the role. Having UVM and assertion knowledge would be an advantage.,

As an AMS Verification Engineer, you will be responsible for working on Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs. Your role will involve hands-on experience with AMS simulation environments using tools such as Cadence, Synopsys, or Mentor. It is essential to have a solid understanding of analog and mixed-signal circuits, including comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators. Your expertise in Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling will be crucial for block-level and chip-level AMS verification. This includes top-level testbench development, self-checking testbenches, and regression suites. Exposure to SystemVerilog (SV) and UVM from an AMS perspective will be considered a plus. Proficiency in scripting languages such as Python, Perl, TCL, or SKILL for automation is required. You should be fluent with Cadence Virtuoso-based analog design flow, encompassing schematic capture, simulator/netlist configuration, and SPICE simulation. Your ability to extract, analyze, and document simulation results and present findings in technical reviews is highly valued. Furthermore, familiarity with test plan development, AMS modeling, and verification methodologies is essential. You will also be involved in supporting post-silicon validation and correlating measurement data with simulations. As a valued team member, you should be team-oriented, proactive, and able to contribute effectively in a multi-site development environment.,

You should have a minimum of 3 years of experience in System Verilog HVL and at least 3 years of experience in OVM/UVM/VMM/Test Harness. It is important to have hands-on experience in developing assertion, checkers, coverage, and scenario creation. You must have successfully executed at least 2 SoC Verification projects and possess experience in developing test and coverage plans, Verification environment, and validation plans. Knowledge of at least one industry standard protocol such as Ethernet, PCIe, MIPI, USB, or similar is required. Participation in reviews and audits is also expected. For management responsibilities, you should have a minimum of 2 years of experience in leading a team of 5 to 10 engineers. Your role will involve defining/deriving scope, estimation, schedule, and deliverables of proposed work. It is crucial to ensure the compatibility of resources, tools, and platforms, as well as working closely with customers through the acceptance of deliverables. Effective management of team members through coaching, mentoring, guidance, and career planning is essential for this role.,

As a Sr. Verification Engineer specializing in SOC Verification at SmartSoC, you will be responsible for the technical execution of complex ARM-based SOC Verification projects. Your role will involve test planning, environment architecture, and the development of SV-UVM environments. To succeed in this role, you should have 3-10 years of experience in Design Verification, with a strong expertise in SOC Verification. Excellent communication and presentation skills are essential, along with a deep knowledge of Verification methodologies such as Coverage Driven Test Planning, Environment Architecture, and Verification Flow. Proficiency in System Verilog and familiarity with methodologies like OVM, UVM, VMM, or RVM is required. Additionally, you should possess a solid understanding of protocols, including at least one of SATA, USB, Ethernet, or PCIE. The ability and willingness to adapt to new methodologies, languages, and protocols are crucial for success in this position. This opportunity falls under the VLSI (Silicon engineering) job category and is available in multiple locations, including India (Bangalore, Chennai, Hyderabad, Noida), Sweden (Stockholm), and the USA (Texas). If you are a driven and skilled SOC Verification expert looking to tackle challenging projects in a dynamic environment, we encourage you to apply and be a part of our innovative team.,

Position: Design Verification Engineer Experience: 48 Years We are looking for a skilled Design Verification Engineer with hands-on experience in MIPI protocols and Display IP. For any queries or further details, feel free to reach me at karthik.adasu@Proxilera.com Responsibilities: Experience in MIPI protocol verification (e.g., MIPI DSI, CSI). Strong hands-on experience in Display IP verification and validation. Ability to develop and execute verification plans targeting display and MIPI components. Perform RTL, gate-level, low-power simulations; ensure ISO 26262 compliance. Build SystemVerilog/UVM testbenches tailored to MIPI and Display IPs. Perform simulation and debug activities for MIPI/Display-related RTL modules. Collaborate with RTL and integration teams to resolve display and MIPI interface bugs. Integrate MIPI and Display IPs into subsystem or SoC-level test environments. Implement protocol-specific checkers, monitors, and assertions. Analyze functional coverage metrics related to display pipelines and MIPI interfaces. Work closely with post-silicon and firmware teams to validate MIPI and display functionality

The detailed JD is given below Requirements : - B.Tech/M.Tech with 5+ Years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV) using SV RNM or Custom UDN s. Good understanding of analog design concepts and mixed signal design architectures. Exposure to products that integrate a wide variety of Analog/Mixed-Signal building blocks such as Power Management, PLL/Synthesizers, ADC, DAC, bandgap references, oscillators/clocking circuits, Phase Interpolators, SerDes etc. and related digital control and signal processing. Demonstrated experience of verification plan development, UVM verification environment development/debug and verification of complex mixed signal products at block, Subsystem & chip-top levels. Familiarity with Analog/Mixed-Signal/RF design architectures and debug experience with schematic capture tools such as Cadence Virtuoso and waveform viewers such as Cadence Simvision. Experience of imulations with analog model and digital RTL/Gate+SDFs. Experience and debug with digital simulators such as Cadence Xcelium/DMSO/Synopsys VCS. Experience in developing self-checking testcases, functional/code coverage & formal verification. Tracking of verification metrics and regression management, Metric Driven Verification (MDV) framework using tools such as Cadence vManager. Experience in closing the verification of analog designs using industry standard metrics is a must. Quick to adopt new technologies with good problem-solving skills. Collaborate and work closely with team members from various disciplines (system architects, digital design, analog design, digital DV etc.). Self-motivated and enthusiastic.

In today s world of faster and more virtualized servers, storage, and network connections, CPUs cannot keep up with the growing network processing demands. Legacy or foundational network interface cards (NICs) may deliver efficient networking however when running demanding workloads, they cause overhead that burdens CPUs, chewing into available processing power. To deploy more advanced networking capabilities a new generation of intelligent NICs are required to deliver accelerations and additional processing power to offload CPUs. The industry-leading NVIDIA SmartNICs/DPUs (Data Processing Units) provide sophisticated hardware offloads and accelerated networking, storage, security, and manageability services for modern cloud, artificial intelligence, telecommunications and traditional enterprise workloads. With unmatched RDMA over Converged Ethernet (RoCE) performance, NVIDIA SmartNICs/DPUs deliver efficient, high-performance remote direct-memory access (RDMA) services to bandwidth- and latency-sensitive applications. The NBU team in India is a new team that is growing at a fast pace. We are currently seeking an Experienced Verification Engineer with strong verification fundamentals to work in NBU ASIC team. You will join a group of hardworking engineers to implement the next innovative Networking Silicon chip. In this position, youll make a real impact in a multifaceted, technology-focused company while developing the industrys best high-speed communication devices, delivering the highest throughput and lowest latency! What you ll be doing: Be responsible for verifying the smartNIC/DPU designs, architecture and micro-architecture using advanced verification methodologies. You are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems. Use advanced verification methodologies like e-specman, SV-UVM etc. What we need to see: BS / MS (or equivalent experience) with 10+ years of experience in design verification. Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc. ). C/C++ programming/scripting language experience desirable. Ways to stand out from the crowd: Prior experience of smartNIC and/or high-speed interconnects. Strong debugging, problem-solving and analytical skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a phenomenal teammate. Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www. nvidiabenefits. com/ #LI-Hybrid

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Design. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Synthesis. Experience: 3-5 Years.

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

This job might be for you if You enjoy solving problems. You love taking on difficult challenges and finding creative solutions. You dont know the answer but will dig until you find it. You communicate clearly. You write well. You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference. You can impress our customers with your enthusiasm to solve their issues (and solve them!) Job Description Required Solid RTL coding experience including Microarchitecture of design System Verilog and Verilog coding using provided coding styles. Understanding of SDC Understanding STA reports and how to adjust RTL accordingly. Designing for error cases and debug of IP Understanding of CDC logic Knowledge of lint rules and exceptions Design and use of block level simulations to bring up IP. Knowledge of AMBA buses and when to use them. Job Description Preferred Experienceleading small design team. C coding / Firmware skills Knowledge on common processor architectures(ARM, RiscV) FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA. Lab brings up experience, scripting. Relevant tool experience such as: Socrates, Core Consultant in additionto standard simulation tools (xcellium, vcs, etc) Emulation experience(Zebu, Palladium, etc) Board knowledge, component selection, probing, debug. JTAG debugging experience (Coresight, Lauterbach, etc). Low power design techniques Qualifications E./B.Tech. degree at minimum.

As a Design Verification Engineer, you will be responsible for verifying complex designs such as accelerators, datapath IP, processor core subsystems, and complex interfaces/protocols using leading-edge methodologies like UVM and Formal DV. Your role will involve architecting the testbench, developing the verification environment, and defining test plans, tests, and verification methodology for block/sub-system level verification. You will collaborate with the design team to generate test plans, ensure code and functional coverage closure, integrate block testbenches at the sub-system level UVM environment, and verify integration. Additionally, you will interact with the analog co-simulation and firmware team to enable top-level chip verification aspects. Your responsibilities will also include packaging verification environments for Digital IP for seamless integration into the verification flow at different stages of execution. You will evaluate 3rd party IPs on key qualitative aspects and establish evaluation flows for home-grown and 3rd party IPs for consistent benchmarking of DV evaluation. To excel in this role, you should have a minimum B.E./B.Tech degree in Electrical/Electronics/Computer Science and 7-10+ years of experience in design verification with UVM and constrained random, coverage-based verification approaches. You must possess a strong understanding of DV concepts and the ability to develop scalable DV environment architecture for achieving first-pass DV success. Your adaptability to learn end application/systems and map them into smart verification test plans will be crucial. Excellent debugging and analytical skills, along with good interpersonal, teamwork, and communication skills, are essential for effectively driving discussions with geographically dispersed teams. Knowledge of assertion-based formal verification, standard on-chip interfaces, processor/SoC architecture, and/or DSP fundamentals will be advantageous. Experience with ASIC/SoC product DV and productization is highly desirable for this role.,

Role & responsibilities Strong verification expertise using Verilog and SystemVerilog, with solid understanding of UVM methodology and hands-on experience writing test-benches. Proficient in debugging testcases and verifying processor-based subsystems. Knowledge of AMBA protocols (AXI, AHB, APB) is a plus. Exposure to Arm-based SoCs and strong grasp of digital design fundamentals. Experience with scripting in Perl, TCL, Make, and Shell.

SOURCERIGHT TECHNOLOGIES (INDIA) PRIVATE LIMITED is looking for Design Verification, Pcie, SV, UVM, Ethernet (SI412FI RM 3403) to join our dynamic team and embark on a rewarding career journey Collaborate with cross-functional teams to achieve strategic outcomes Apply subject expertise to support operations, planning, and decision-making Utilize tools, analytics, or platforms relevant to the job domain Ensure compliance with policies while improving efficiency and outcomes

NVIDIA has been transforming computer graphics, PC Gaming, and accelerated computing for more than 25 years. It s a unique legacy of innovation that s motivated by great technology and amazing people. Today, we are tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what s never been done before takes vision, innovation, and the world s best talent. As an NVIDIAN, you ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. The HWPM Team at NVIDIA is seeking an excellent ASIC Senior Verification Engineer to drive high-quality, robust verification of system-level IP across unit, subsystem, and SoC levels. This role is ideal for someone passionate about ground-breaking hardware, sophisticated verification methodologies, and crafting the future of computing. Come join the team and see how you can make a lasting impact on the world. What You ll Be Doing: Play a key role in the Hardware Performance Monitor (HWPM) team, helping define and develop system-level RTL and performance measurement methodologies for NVIDIA s industry-leading SoCs and GPUs. Develop comprehensive test plans, implement tests, and apply robust verification strategies to validate microarchitecture and design functionality. Design and implement reusable, scalable testbenches and testbench components using System Verilog and UVM. Collaborate with architects, RTL designers, and software engineers to drive feature completeness, performance visibility, and verification closure. What we need to see: M. Tech. (or equivalent) in VLSI or Electronics Engineering with 2+ years of relevant industry experience OR B. Tech with 4+ years of experience in a similar domain Proven experience in unit, sub-system or SoC Level Verification Hands-on expertise in building and maintaining testbench environments for both unit and system-level verification Proficiency in Python or industry-standard scripting languages for automation and test development Strong debugging and analytical skills Familiarity with industry-standard design and verification tools like VCS, Xcelium, etc. Solid understanding of RTL Design Principles and Verilog Experience with UVM (Universal Verification Methodology) is a strong plus Excellent communication & collaboration skills, with ability to work effectively across cross-functional teams Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. Also, we have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our outstanding engineering teams are growing fast. If you are creative, curious, and motivated with a real passion for technology, we want to hear from you! #LI-Hybrid

We are looking for a seasoned Senior Design Verification Engineer with 8+ years of experience in verifying complex digital IPs and SoCs. The ideal candidate will have strong expertise in developing UVM-based verification environments and driving functional coverage closure. Key Responsibilities: Develop and maintain constrained-random and directed testbenches using System Verilog/UVM Define verification plans and test strategies based on specifications Write test cases, checkers, and functional coverage models Perform RTL simulations, debug failures, and ensure coverage closure Collaborate with RTL, DV, and firmware teams across verification lifecycle Support gate-level simulation, regression management, and post-silicon bring-up Requirements : 8+ years of hands-on experience in digital design verification Expertise in System Verilog, UVM, and verification methodology Strong debugging skills using simulators like VCS, Questa, or Incisive Good understanding of protocols like AMBA (AXI/AHB/APB), PCIe, Ethernet, etc. Experience with coverage tools, version control, and regression systems Strong communication, collaboration, and documentation skills

NVIDIA has been redefining computer graphics, PC Gaming, and accelerated computing for more than 25 years. It s a unique legacy of innovation that s motivated by phenomenal technology and outstanding people. Today, we are tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what s never been done before takes vision, innovation, and the world s best talent. As an NVIDIAN, you ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. The HWPM Team at NVIDIA is seeking an excellent ASIC Verification Engineer to drive high-quality, robust verification of system-level IP across unit, subsystem, and SoC levels. This role is ideal for someone passionate about ground-breaking hardware, sophisticated verification methodologies, and crafting the future of computing. Come join the team and see how you can make a lasting impact on the world. What You ll Be Doing: Play a key role in the Hardware Performance Monitor (HWPM) team, helping define and develop system-level RTL and performance measurement methodologies for NVIDIA s industry-leading SoCs and GPUs. Develop comprehensive test plans, implement tests, and apply robust verification strategies to validate microarchitecture and design functionality. Design and implement reusable, scalable testbenches and testbench components using System Verilog and UVM. Collaborate with architects, RTL designers, and software engineers to drive feature completeness, performance visibility, and verification closure. What we need to see: M. Tech. (or equivalent) in VLSI or Electronics Engineering OR B. Tech with 2+ years of experience in a similar domain Hands-on experience in unit and/or system level verification Ability to contribute to testbench development and maintenance, preferably using System Verilog and standard methodologies Proficiency in Python or industry-standard scripting languages for automation and test development Proven debugging fundamentals ability to read waveforms, analyze logs, and isolate issues effectively Familiarity with industry-standard tools such as VCS, Xcelium, Verdi, or similar simulation/debug environments Good understanding of RTL design concepts and experience working with Verilog or SystemVerilog Experience with UVM (Universal Verification Methodology) is a strong plus Clear communication skills and collaborative attitude, with ability to work alongside design, DV, and automation teams Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. Also, e have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our outstanding engineering teams are growing fast. If you are creative, curious, and motivated with a real passion for technology, we want to hear from you! #LI-Hybrid