685 Uvm Jobs - Page 5

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Principal Product Engineer Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary: Drives development of products and technologies and has material responsibility for the success of that product/technology. VIP PE is expected to be an expert in Memory domain of Verification IP family- protocol and product-wise. PE main role is to help accelerate VIP portfolio adoption at Cadence s top tier customers by supporting pre-sales technical activities. To ensure that, one must have strong verification expertise and understand customer design and verification flows. As a Memory model VIP and protocol expert, PE drives product knowledge transfer across our field engineers and customer, providing training and developing collaterals. The PE will also need to translate high-level requirements from customers into a technical spec and drive the product definition that fits the customer needs. PE is expected to work independently and collaborate with other team members (RD, Marketing, support) to ensure all dimensions of the product are aligned. This role requires approximately 20% travel on average. Job responsibilities: (edit as per the requirement) Leads projects with high resource, risk and/or complexity Develops and leads large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity Continually evaluates technology effectiveness/data interoperability of complex systems Manages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products Communicates highly-complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view. Experience and Technical Skills required (edit as per the requirement): At least 7+ to 12 years of experience with Verification and Design Working knowledge with Memory Models like DDR, HBM, LPDDR protocols is a must Experience with Developing Verification environments using System Verilog Working knowledge and experience with the UVM methodology Good experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors. Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results. Excellent problem-solving and debugging skills Qualifications BE/BTech/ME/MS/MTech in Electrical, Electronics Comm or Computer Science Engineering Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We re doing work that matters. Help us solve what others can t.

Role: AMS Verification Engineer / Sr. Engineer Experience required: 5-15 years Work location: Pune, Bangalore, Hyderabad, Chennai, and Noida Minimum 5 Years of overall experience in ASIC Verification Should have worked on AMS Verification for a minimum of 2 years Develop and execute verification plans for AMS designs. Create test benches and run simulations using tools such as Cadence Virtuoso, Spectre, or AMS Designer. Verify mixed-signal blocks (e.g., ADCs, DACs, PLLs) and ensure proper analog-digital interaction. Debug and resolve design issues in collaboration with design teams. Document verification results and ensure compliance with design specifications. Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com References are welcome! For other open roles, please visit - www.logicalhiring.com

Role: ASIC Verification Engineer Experience Required: 5-15 Years Work location: Bangalore, Hyderabad, Chennai, Ahmedabad, and Pune Minimum 5 years of experience in System Verilog HVL. Minimum 5 years of experience in OVM/UVM/VMM/Test Harness. Hands-on experience in developing assertions, checkers, coverage, and scenario creation. Must have executed at least 2 to 3 SoC Verification projects Experience in developing test and coverage plan, verification environment and validation plan. Knowledge of at least one industry standard protocol like Ethernet, PCIe, MIPI, USB, or similar is required. Review and Audit participation. At least 1 year of experience in handling a team for the senior roles Define/derive the Scope, Estimation, Schedule, and Deliverables of the proposed work. Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com References are welcome! For other open roles, please visit - www.logicalhiring.com

Mirafra is hiring!!! Hardware (HW) Verification Engineer Location: Hyderabad Experience: 5 to 10 Years Job Description: Mirafra Technologies is hiring experienced Hardware Verification Engineers to work on top-tier SoC verification projects. The ideal candidate will have strong UVM/SystemVerilog expertise and hands-on experience with FPGA and protocol-level testing. Responsibilities: Develop SV/UVM testbenches at Top/Sub-system/Block-levels Drive creation and execution of test plans and test specs Document verification phases: user guides, test reports, and execution logs Contribute to verification architecture and methodology development Required Skills: Strong programming skills in SystemVerilog and UVM Protocol verification experience: Ethernet, PCIe, SPI, I2C, USB Hands-on hardware testing experience using logic analyzers, traffic generators Exposure to FPGA verification and Xilinx tools Solid debugging skills at both device and board level Proficiency in scripting languages: Perl, Python, TCL Strong interpersonal, communication, and analytical skills Apply Now or send your resume to swarnamanjari@mirafra.com Note: This is a client-based selection process .

Design Verification Engineer (4-7 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement

Lead /Senior Design Verification Engineer-GLS/UVM |Hyderabad, India | Experience:7-12 Years Role Overview: We are looking for an experienced and detail-oriented Design Verification Engineer with strong expertise in Gate-Level Simulation (GLS) and SystemVerilog/UVM methodology . The role involves validating complex SoC/IP designs in post-synthesis environments, working closely with design, DFT, and physical implementation teams. Experience with HBM (High Bandwidth Memory) is a strong advantage. Key Responsibilities: Develop and maintain UVM-based verification environments for complex digital IP and SoCs. Plan and execute GLS (Gate-Level Simulation) flows including SDF annotation, X-checking, and timing-aware validation. Perform debug of timing-related and X-propagation issues at netlist level. Drive regression automation, simulation coverage analysis, and documentation of results. Work closely with cross-functional teams (DFT, synthesis, STA, PD) to resolve post-synthesis and post-layout issues. (Optional) Support validation of HBM interfaces , including protocol-level behavior and error scenarios. Required Skills: 7-12 years of design verification experience in ASIC or SoC environments. Solid expertise in SystemVerilog, UVM , and assertion-based verification. Strong hands-on experience in GLS including: SDF annotation Debugging setup/hold, X issues Power-aware simulations (optional) Familiarity with simulation tools : VCS, Xcelium, Questa, Debussy/Verdi. Experience with scripting (Perl, Python, Shell) for automation. Good understanding of chip lifecycle from RTL to GDSII. Nice to Have: Experience working with HBM protocols or memory controller verification. Exposure to low-power verification , UPF flows. Familiarity with post-silicon bring-up and debug is a plus. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

Position #1: Lead/Senior Design Verification Engineer - CPU / RISC-V Location : Bangalore Experience : 612 Years Domain : Semiconductors | SoC | RISC-V | CPU Subsystems Role Overview: We are seeking an experienced Design Verification (DV) Engineer to join our core CPU verification team focused on RISC-V based processors and subsystems . This is a hands-on role requiring strong technical knowledge in processor architecture , microarchitecture verification , and end-to-end validation of complex SoCs. Key Responsibilities: Develop and execute test plans and environments for CPU and RISC-V based subsystems. Build UVM-based verification environments for simulation and regression. Create testbenches, assertions, checkers, and functional coverage models. Debug failures using waveform viewers, logs, and deep architectural understanding. Collaborate with architects, designers, and firmware teams across all verification phases. Required Skills: 612 years of hands-on DV experience, primarily on CPU cores or RISC-V . Strong understanding of RISC-V or ARM microarchitectures . Proficient in SystemVerilog, UVM , and scripting (Python/Perl/Tcl). Experience with cache coherency, MMUs, branch prediction, or pipeline logic is a plus. Exposure to verification tools like VCS, Questa, or Xcelium . Position #2: Lead/Senior Design Verification Engineer - High-Speed PCIe Location : Bangalore Experience : 612 Years Domain : Semiconductors | SoC | High-Speed Interfaces | PCIe Gen4/Gen5 Role Overview: We are looking for a skilled Design Verification Engineer with expertise in high-speed interface protocols , particularly PCI Express (PCIe) . The role will focus on validating complex SerDes-based subsystems and ensuring full compliance and performance coverage. Key Responsibilities: Define and implement UVM-based testbenches for PCIe-based subsystems. Verify protocol-level compliance (PCIe Gen4/Gen5/Gen6). Generate, run, and debug simulations across various protocol scenarios and stress conditions. Ensure full coverage functional, code, and assertion-based . Collaborate with silicon validation and firmware teams for end-to-end test alignment. Required Skills: 612 years of DV experience with PCIe (mandatory) and high-speed interface protocols. Strong command of UVM, SystemVerilog , and assertion-based verification. Deep understanding of PCIe layers , packet formats, credit flow, and link training. Experience with VIPs (Synopsys/Cadence/Mentor) and waveform debugging tools. Knowledge of AXI/AMBA , DDR, or USB is a strong plus. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

Job Title: Design Verification Engineer Location: Hyderabad Experience: 3 to 8 Years Job Description: Mirafra Technologies is looking for experienced Design Verification Engineers to join our team in Hyderabad . This role involves a mix of IP-level ownership, feature enhancement, and debug responsibilities. Key Responsibilities: Own design verification at the IP level Plan and execute feature additions and mode re-enablement for specific design variants Perform bug fixes and analyze regression signatures Minimum Qualifications: Proficient in SystemVerilog, UVM, UVM_REG , and advanced debugging techniques Experience reading specifications and developing comprehensive test plans Expertise in building monitors, scoreboards, sequencers, and sequences Skilled in using scripts and verification methodologies to enhance bug detection Strong understanding of functional verification , including test planning, testbench development, stimulus generation, checking, and functional coverage Comfortable with build checks , working with large testbenches , coverage analysis , and adding/enabling debug mechanisms Proactive approach to analyzing failures and identifying root causes Apply Now or send your resume to swarnamanjari@mirafra.com

Key Responsibilities Lead and manage all engineering functions across front-end and back-end VLSI design and verification. Define and execute engineering strategy aligned with company objectives and customer requirements. Drive excellence in RTL design, functional verification, DFT, physical design, STA, and sign-off processes. Build and mentor high-performing teams; attract, retain, and develop top VLSI engineering talent. Ensure timely delivery of high-quality project outcomes across multiple client engagements. Establish and enforce best practices, methodologies, and quality standards. Collaborate with business development and sales teams to support proposals and client interactions. Evaluate and introduce tools, technologies, and methodologies to enhance engineering productivity. Manage engineering budgets, resource planning, and project allocation. Foster a culture of innovation, ownership, and continuous improvement. Qualifications B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related field. 15+ years of hands-on experience in VLSI design and verification, including at least 5 years in senior leadership roles. Proven track record of managing large engineering teams and delivering complex SoC or ASIC projects. Deep expertise in design (RTL, synthesis) and verification (UVM, SystemVerilog, functional coverage). Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor, etc.). Strong leadership, communication, and organizational skills. Experience working with global clients or in multinational environments is a plus.

Job Details: : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Hot Vacancy Design Verification Engineer (5–10 Years) Location: Bangalore Experience: 5 to 10 Years Industry: Semiconductors / VLSI / ASIC Employment Type: Full Time Joining: Immediate to 30 days preferred Job Description: We are actively hiring skilled and passionate Design Verification Engineers with 5–10 years of experience for multiple cutting-edge SoC/ASIC. Roles and Responsibilities: Develop test plans , testbenches , and testcases using System Verilog and UVM . Own block-level and/or SoC-level verification and drive coverage closure . Verify protocols and interfaces such as AXI, AHB, PCIe, LPDDR5, UCIe, I3C, CXL , etc. Perform assertion-based verification (SVA) and support gate-level simulations (GLS) . Collaborate with cross-functional teams including RTL. Desired Candidate Profile: 5–10 years of hands-on experience in ASIC/SoC functional verification . Strong in System Verilog, UVM . B.E./B.Tech or M.E./M.Tech in ECE/EEE/CSE or related fields. Why Join Us? Work on next-gen chip designs with global teams. Opportunity to work on latest protocols and IPs . Interested Candidates share your resumes to priya@maxvytech.com and hr@maxvytech.com

Minimum 4 years of experience in System Verilog HVL. Minimum 4 year of experience in OVM/UVM/VMM/Test Harness.

verification experience in SV, UVM, DDR, serdes high speed protocol, PCIE

In your new role you will: Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices. Responsible for: Designing self-checking test benches using modern verification techniques o Implementing functional coverage and assertions using System Verilog and UVM. Developing TB environment using SV and UVM. Developing test and functional coverage plans based on device specifications. Analyzing and debugging simulation failures, as well as analyzing functional coverage results to guarantee zero defect outcomes. Your Profile You are best equipped for this task if you have: Engineering in Electrical/electronic streams , or equivalent experience. 7+ years experience in constrained-random, coverage driven verification environments. Experience in developing the test bench from scratch using System Verilog (SV) HDVL and UVM (Universal Verification Methodology). Expertise in Gate Level simulations (GLS) a nd have debugged, root caused real netlist issues. A solid understanding of verification concepts and experience designing class-based test benches. C coding, Formal verification methods and Power aware simulation will be an advantage Excellent written and oral communication skills Strong debugging skills, functional simulations and GLS simulations.

nikita.chaudhary@enlink.com Job Title: Design Verification Engineer SoC/IP Verification Location: Bangalore Job Type: [Full-Time] Experience : 5 to 9 Years Job Description: We are looking for experienced Design Verification Engineers with a strong background in SoC and IP-level verification. The ideal candidate will be responsible for developing and implementing advanced verification environments and ensuring the functional correctness of complex digital designs. Key Responsibilities: Develop and maintain verification environments for SoC and IP designs Implement test bench components and verification infrastructure Create and execute test cases to ensure thorough validation of designs Develop and track functional coverage metrics Write and integrate assertions for design verification Perform failure analysis and debug issues efficiently Work with high-speed interface protocols such as PCIe Gen6, CXL,Ethernet, and UCIe Required Skills: Strong experience in SystemVerilog/UVM-based verification methodologies Solid understanding of digital design and verification flows Proven skills in debugging and failure analysis Experience with functional coverage and assertions Hands-on experience with at least one of the following protocols:PCIe Gen6, CXL, Ethernet, or UCIe Excellent communication and teamwork skills Preferred Qualifications: Bachelors or Masters degree in Electronics, Electrical, or relate engineering disciplines Exposure to scripting languages (Python, Perl, etc.) for automation Contact HR Nikita Chaudhary 8879637539 nikita.chaudhary@enlink.com

DESIRED PROFILE : Expertise in working with large teams working on ASIC verification or digital verification Expertise in Digital Verification / Formal Verification flow Expertise in working on system Verilog assertions & test benches Expertise in working on UVM based verification flow Expertise in working on ARM processor Expertise in working on AMBA bus protocols (AXI, AHB, APB) Expertise in CXL or PCIe Protocol Verification Expertise in simulation tools (VCS, ModelSim, Questa) Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. Expertise in analysing Code Coverage, Functional Coverage and Assertions. Expertise in verification of complex SoCs. Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. Expertise in Verification of complex datapath, DSP based ASICs Good knowledge in gate-level simulation, and Scripting languages like Python, TCL JOB SPECS : Responsible to perform Digital Verification / Formal Verification flow Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management Hire, build technical teams from scratch and manage high caliber technical teams across GCC, ODC and onsite. Must be willing to work at customer sites as per customer needs Must be willing to travel worldwide at short notice as per customer needs Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action Uphold the organization's culture and long term missions Liaise and negotiate with various partners around the world to bring in new partnership. Synergize all company's resources and talents for the growth of company's business Oversee all sectors and fields of the business to ensure the company's competitiveness Provide leadership, direction, major decision making and resolution support to operations, projects and staff. Build strategic business partnerships and execute these opportunities through collaboration with external partners.

NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the world s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: You will be responsible for verifying the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies. Understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. Coming up come up with test plans, tests and verification infrastructure for complex IPs/sub-systems. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Work on advanced verification methodologies like SV/UVM. Perform functional coverage driven verification closure. Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks. What we need to see: B. Tech. / M. Tech. , or equivalent experience. 5+ years of relevant experience. Experience in verification of complex IPs/units and sub-systems. Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies. Expertise in Verilog. Knowledge in SystemVerilog or similar HVL / UVM or VMM. Ways to stand out from the crowd: Experience in memory subsystem or network interconnect IP verification. Good debugging and analytical skills with sound scripting knowledge. Good communication and excellent team player. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. #LI-Hybrid

Senior/ Lead - Design Verification Engineer SV / UVM Test bench development and test cases coding Code and Functional coverage analysis and closure Work with team for verification closure Experience with python or any other scripting language is a plus Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage. BSEE/BS Computer Science, Computer Engineering, Electrical Engineering (or equivalent). Good Experience on Semiconductor/VLSI Design verification IP's. Experience with ISO 26262 is plus Leads must have Faultsim experience Z01X tool experience and any equivalent tool Can consider GLS experience for rest of the engineers. Location: Bangalore / Hyderabad Notice Period: Immediate to 60 days. Experience: 4 to 12 Years

Greetings from Synopsys!!! I hope this message finds you all well! At Synopsys Inc, we are looking for Senior Design Verification Engineer and expertise in System Verilog and UVM methodology skills for an exciting project. If you're open to exploring this opportunity, I would love to discuss it further. Please feel free to reply to this email or we can chat over the phone at your convenience. I believe this could be a great match for both of us. Experience: 5+yrs to 15years Location: Bengaluru & Noida Expertise in UVM/OVM/SOC and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for verification projects using VMM/OVM/UVM methodologies . Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Taufiq Hussain Talent Acquisition, Sr Staff | People | mobile: +91 9148401555 | email: taufiq@synopsys.com

Design Verification Engineer (5 to 12 Years) SoC/IP Verification Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune] Experience: 5 t o 12 Years Openings: 8 Positions Preferred - Immediate to 45 Days (Notice Period) Job Location: ACL Digital is hiring experienced Design Verification Engineers to work on leading-edge processor-based SoCs and IPs. Notice Period-Prefer less Notice period or serving. Strong understanding of design verification methodologies (UVM, SV, etc.) Experience with industry-standard protocols (AXI, DDR, PCIe, etc.) Familiarity with ASIC and SoC design flows. Proficiency in scripting languages (Python, Perl) Experience with simulation tools and debuggers. Strong problem-solving and analytical skills Communication and collaboration skills to work effectively with cross-functional teams Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: AMBA, AXI, PCIE, USB, MIPI

In fast changing markets, customers worldwide rely on Thales. Thales is a business where brilliant people from all over the world come together to share ideas and inspire each other. In aerospace, transportation, defence, security and space, our architects design innovative solutions that make our tomorrows possible. Senior Technical Lead - Design Optimization for FPGAs Essential Specifications: Masters / PhD in Electrical Engineering, Computer Science, or a related field with at least 10 years of experience on FPGA based designs, design optimizations and problem solving. Strong understanding of digital logic fundamentals and computer architecture. Proficiency in FPGA programming techniques. Experience with timing analysis and optimization for FPGA designs. Excellent skills in Verilog programming language. Experience using Vivado or Questa Sim EDA tools. Desirable Specifications: Knowledge of RISC-V architecture. Effective presentation skills to communicate complex ideas. Familiarity with verification techniques using UVM. Responsibilities: Work on a variety of design optimization problems for FPGA-based systems. Collaborate with the team to develop innovative solutions for performance improvement, power optimization, and area reduction. Implement designs using FPGA programming languages like Verilog. Conduct timing analysis and optimize designs to meet performance requirements. Utilize Vivado or Questa Sim EDA tools for design and validation. Stay informed about the latest advancements in FPGA design optimization. Document research findings and project progress accurately. Participate in team meetings, providing valuable insights and suggestions.

NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. Were united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks. What we need to see: B. Tech. / M. Tech or equivalent experience 5+ years of relevant experience Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog Expertise in comprehensive verification of IP or interconnect protocols (e. g. PCI Express, USB, SATA) Experience in developing and working in functional coverage based constrained random verification environments Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug Ways to stand out from the crowd: Excellent knowledge of PCIE protocol - Gen3 and above Good understanding of the system level architecture of PCIE/CXL-based designs Perl, Python or similar scripting and SW programming language experience Good debugging and analytical skills Good interpersonal skills & dream to work as a great teammate #LI-Hybrid

Job Summary: We HCL TECH are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 4-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement

VERIFICATION LEAD – IP VERIFICATION SmartSoC is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution. This role will include- Lead an internal IP Verification team, executing projects for an offshore client Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects Guide team members in verifying IP’s and delivering zero bug IP’s Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 8 – 12 years experience in Design Verification Expert Knowledge in IP Verification Very strong knowledge in multiple protocols is highly desired, AMBA protocols and at least one high speed interface Must have expert knowledge in coverage driven test planning Must have expert knowledge in architecting configurable environments Must have very strong System Verilog and UVM background Must be able to lead the team technically in all aspects, must be able to drive multiple projects Past experience leading and managing teams highly desired Excellent Communication and Presentation Skills Ability and desire to learn new methodologies, languages, protocols etc. is required Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

SENIOR VERIFICATION ENGINEER – SV UVM SmartSoC is looking for smart and enterprisingDesign Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. SmartSoCs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM. Job Responsibilities- Build SV, SV UVM, OVM based environments. Work with many different networking and other protocols Desired Skills and Experience- 3 to 10 years of experience in IP verification Good experience in SV/ UVM based verification project. Good debug skills is a must. Experience in building components like Scoreboard, functional coverage & writing sequences using SV/UVM based Verification environment One of the following experiences is important: Experience in Video/Display domain in particular DP, oLDI, MIPI CSI/ DSI Experience in any one high speed protocol like USB3, PCIe, MIPI, Unipro etc Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USADelaware Location - Bengaluru,Chennai,Hyderabad,Noida