964 Uvm Jobs - Page 4

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. . Required education Master's Degree Preferred education High School Diploma/GED Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design,

Your Role and Responsibilities Lead the unit level pre-silicon functional & performance verification the Instruction Sequencing Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for ISU which covers the Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Technical and Professional Expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of Instruction Dispatch verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Nice to haves - Knowledge of instruction dispatch and Arithmetic units. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Knowledge of verification principles and coverage. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.

Your Role and Responsibilities Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Technical and Professional Expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Nice to haves - Knowledge of instruction dispatch and Arithmetic unit. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Knowledge of verification principles and coverage. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.

As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Develop skills in IBM Formal verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 – 10 years of relevant industry experience Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. Knowledge of formal methodology, Knowledge of HDLs (Verilog, VHDL, SV), Good programming skills in python, processor core u-arch skills Exposure in developing testbench environment, debugging and triaging fails. Good communication skills and be able to work effectively in a global team environment. Drive verification coverage closure, lead verification team. Drive complex scenarios, participate in High level design discussions. Track record in leading teams. Preferred technical and professional experience Writing test plans, building random / exhaustive formal verification environment, functional and coverage analysis and debug. Good understanding of the Server System

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor core/cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Role & responsibilities Core Requirements Basic understanding of CMOS and gate level circuit designs Familiarity with SPICE Familiarity with Verilog simulations Good communication skills and ability to work well in a team Preferred Qualities Analytical capability for complex gate level circuit designs Experience in SystemVerilog, PLI coding Experience in UVM Test Bench Experience in DRAM, SRAM or other memory related fields Experience Level 5+ years Preferred candidate profile

Roles and Responsibilities 8yrs yrs of Experience in developing TB & TB components for block level and full chip level verification. Experience in creating Test plan, writing Test cases Proficient in System Verilog Verilog Proficient in writing Assertions UVM based Methodology with strong understanding of OOPS concepts Good knowledge of Digital Fundamentals Good knowledge of Scripting (Perl, Shell), C language Familiar with different aspects of IP development: micro-architecture, RTL & TB implementation, Test plan, Functional coverage, Code coverage and regression Strong Simulation & Debugging skills Strong analytical skills with attention to detail Excellent written & verbal communications skills. Knowledge of protocols such as PCI-Express, Rapid IO, NVM Express, NAND,CXL and DDR/ LPDDR Experience implementing directed and random test cases. Very good leadership skills. You will be a key player in IP development forMemory/Wired-Interconnect/Networking/Mobile/ Video Develop BFMs, Drivers, Monitors and Scoreboard for the test bench in System Verilog. Mandatory skills (Leads ): oExperience in leading team atleast 5 member team. 0 Strong hands-on Verification experience in AMBA protocols oStrong hands-on UVM, Assertions, RAL. Testbench flow. oExperience intestbenche development using UVM. oStrong hands-on experience in testbench run automation using make, c-shell or perl scripts Good to have PMIC experience. Skills Required UVM, System Verilog, Verification Location Bengaluru, India

As a Sr. Verification Engineer specializing in SOC Verification, you will be a valuable member of the SmartSoC team, contributing your expertise to intricate SOC Verification projects. Your responsibilities will entail the technical execution of SOC Verification projects for complex ARM-based SOCs. This involves tasks such as Test Planning, Environment Architecture, and creating SV-UVM environments to ensure the successful verification of SOC designs. To excel in this role, you should possess 3 to 10 years of experience in Design Verification, coupled with excellent Communication and Presentation Skills. Your proficiency in SOC Verification is crucial, along with your expertise in Verification methodologies such as Coverage Driven Test Planning, Environment Architecting, and Verification Flow. A strong command of System Verilog is essential, as well as familiarity with methodologies like OVM, UVM, VMM, or RVM. Furthermore, your knowledge of protocols, specifically one of SATA, USB, Ethernet, or PCIE, will be highly beneficial. Your willingness and ability to adapt to new methodologies, languages, and protocols are key attributes for success in this role. This position falls under the Job Category of VLSI (Silicon Engineering) and offers opportunities in various locations including Bangalore, Chennai, Hyderabad, Noida in India, Stockholm in Sweden, and Texas in the USA. Join us at SmartSoC and be part of a dynamic team working on cutting-edge SOC Verification projects.,

As a Design Verification Engineer at our Hyderabad location, you will be responsible for verifying the design of industry-leading products, such as Graphics DDR7. With 5-7 years of experience in SV, UVM, Test Bench Development, Soc, Full-chip verification, and memory experience, you will play a crucial role in ensuring the quality and reliability of our products. Your primary responsibilities will include Verilog simulation, UVM methodology implementation, and full-chip verification. Familiarity with memory interfaces is highly preferred. Additionally, you will have the opportunity to work on projects involving GLS, STA, Python knowledge, and circuit characterization. We are looking for someone with a quick learning ability, a positive attitude, and strong technical skills in system Verilog and UVM. Your educational background should include a bachelor's degree, and any experience in static timing analysis, GLS, and Python automation for test bench development will be advantageous. Strong communication skills are essential for this role, as you will be required to effectively convey complex technical concepts to your peers. A proactive learner with strong analytical and problem-solving skills will thrive in this dynamic environment. If you are a local candidate and an immediate joiner with a passion for design verification and a desire to work on cutting-edge products, we would love to hear from you. Join us in our mission to deliver high-quality products to our customers and make a significant impact in the industry.,

The ideal candidate for the position should be a self-motivated and multi-tasker, with a demonstrated ability to work well in a team setting. As part of the team at Centum T&S, you will be responsible for delivering assigned tasks with a focus on quality. Your role will involve interacting with cross-functional teams to resolve any issues that arise. Strong communication skills and leadership qualities are essential as you collaborate with global stakeholders and report to the Project Manager. Your responsibilities will include working on cutting-edge FPGA-based verification environments that encompass System Verilog (SV) and Universal Verification Methodology (UVM). You will need expertise in IP verification, testbench design, and debugging skills. Experience in working on complex test benches and models in UVM-System Verilog is crucial. Additionally, you will be involved in reviewing design changes from a verification complexity perspective, architecting verification IPs and environments, and optimizing verification flows. Analyzing simulation data to identify and resolve issues efficiently, developing and deploying methodologies within the team, and mentoring other team members will be part of your role. Collaboration with other FPGA engineering teams to ensure high-quality verification environments and RTL deliverables will be essential for success in this position. Key values for the role include a results-oriented approach, customer focus, timely delivery of high-quality work, and a positive attitude. Desirable characteristics include trust-building, adaptability to change, continuous learning, proactive behavior, and a joyful disposition. The ideal candidate should have experience in constrained-random verification, architecting functional verification environments, and developing scalable code using UVM. Strong scripting skills, software engineering expertise, knowledge of object-oriented programming, and proficiency in test bench development processes are required. Effective communication, teamwork, problem-solving skills, planning, and estimation abilities are also essential. Leadership and mentoring experience, familiarity with multiprocessing microarchitecture, bus protocols, and formal verification test benches are advantageous for this role. In summary, the successful candidate will be a proactive team player with a strong technical background, exceptional problem-solving skills, and a dedication to delivering high-quality results within the specified timelines.,

As a VLSI Mentor / Guest Faculty specializing in Advanced Digital Systems & Low Power Design at Spandsons Horizon Engineering, you play a crucial role in guiding 5th, 6th, and 7th-semester B.E./B.Tech students in advanced VLSI concepts and practical applications. This contract role, based in Salem, offers a unique opportunity to directly influence the academic and career growth of 60 aspiring engineers. Your key responsibilities include delivering engaging sessions covering topics such as Advanced Digital System Design with Verilog HDL and Low Power VLSI Design. You will also provide hands-on guidance for lab assignments and projects using various tools like Xilinx Vivado, ModelSim, LTspice, and more. Facilitating interactive learning and ensuring alignment with the semester curriculum are essential aspects of this role. To qualify for this position, you need a minimum of 4-5 years of industry experience in VLSI design, proficiency in relevant EDA tools and hardware platforms, excellent communication skills, and a passion for teaching and mentoring. The program details include a total of approximately 60 students, with sessions scheduled on Thursdays and Fridays for 12 hours per week starting on July 24th & 25th. The program will run for Semesters 5, 6, and 7. In addition to a comprehensive program, benefits such as accommodation, food, and the opportunity to impact the next generation of VLSI engineers are provided. Join us at Spandsons Horizon Engineering and be part of a forward-thinking academic institution.,

If you are passionate about pushing the boundaries of Design technology and thrive in a collaborative, dynamic environment, we invite you to join our team as a Design Engineer. Join us to be part of our journey in shaping the future of SoC design and innovation. Responsibilities As a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team integrating IP and developing logic for SoCs. You will work with the project team to understand and review the architecture and develop the design specifications. Your key responsibilities will include writing micro-architecture specifications, developing the RTL, fixing bugs and running various design checks. You will work with the verification team to review test plans and help debug design issues. You will work with the performance analysis team to evaluate and improve subsystem performance. You will also contribute to developing and enhancing the design methodologies used by the team. You will guide and support other members of the team as needed to enable the successful completion of project activities. You will balance other opportunities such as working with Project Management on activities, plans, and schedules Required Skills and Experience: In addition to bringing your accomplishment of either Bachelors or masters degree or equivalent experience in Computer Science or Electrical/Computer Engineering. Experience of 8+ years working in design of complex compute subsystems or SoCs, you will need: Strong knowledge of digital hardware design and Verilog HDL! A thorough understanding and experience of the current design techniques for complex SoC development. Experience creating design specifications Experience developing RTL for SoC projects Experience with Perl, Python or other scripting language Desired Skills and Experience: Experience with ARM-based designs and /or ARM System Architectures Experience integrating subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet Experience with SystemVerilog and verification methodologies UVM/OVM/e Experience leading small teams or projects Experience or knowledge in the following areas Synthesis and timing analysis Static design checks, including CDC, RDC, X-Propagation, Linting Power management techniques DFT and physical implementation

We are hiring 8+ years of hands-on DV experience in System Verilog/UVM.

Job Description Key Responsibilities: Define and implement verification strategies and test plans for DDR memory interface designs. Develop UVM/System Verilog-based testbenches and reusable verification components. Perform protocol-level verification for DDR memory interfaces and validate compliance. Collaborate with architecture, RTL, and system teams to understand design intent and corner cases. Own functional coverage, regression setup, and closure. Integrate DDR models, controllers, PHYs , and validate their interactions. Required Skills: 6-10 years of hands-on experience in ASIC/IP/SoC verification . Strong expertise in SystemVerilog, UVM, and functional coverage methodology . In-depth working experience with DDR3/DDR4/DDR5/LPDDR protocols . Experience with DDR controllers, PHY integration, and JEDEC standards . Proficient in simulation and debug tools such as Synopsys VCS, Cadence Xcelium, QuestaSim, etc. Good scripting skills in Python, Perl, or Shell for automation and regression management. Excellent debugging and problem-solving skills. Familiarity with AXI/AHB protocols and interconnects is a plus. Experience working with memory models and timing analysis.

Job Requirements Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills. Work Experience Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills.

We are looking for experienced FPGA Verification Engineer. As a FPGA Verification Engineer, you will work for a high complexity DWDM equipment for LH/ULH applications. You will work in close collaboration with multi location cross-functional R & D teams. Our work includes everything from product concept to finished product - a process that spans over the entire development cycle. The team takes full responsibility for delivery on time with the right quality. As an FPGA Verification engineer, you will be responsible for designing verification plan, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and strong will to drive for solutions. Education Necessary: Candidates must have a bachelors degree or higher in EE with very good academics. Roles & Responsibilities: Must have 10 years of experience in developing System Verilog UVM based test environments, developing and implementing test plans at block, sub-chip and chip levels. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools. Exposure to UVM (or similar) verification methodologies is required. Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred. Should be conversant with technologies like, Ethernet, PCIe etc. Knowledge of telecom protocol is preferred. Structured and thorough with analytical and troubleshooting skills. Good written and oral communication skills are required. Flexible, innovative, self-driven and willing to take own initiatives. Highly motivated team player. We offer: A high pace in development of new products. Tight cooperation with other disciplines. Short product development cycles, Real results of your work, you will see how it affects our products and sales. International possibilities of development and internal advancement. Social and wellness activities and clubs. A friendly and helpful atmosphere. Highly competent and motivated colleagues.

CPU Verification Engineer THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: Good at Assembly language and C/C++/SV/Uvm Familiarity with SystemVerilog and modern verification libraries like UVM Experience/Background on Computing/Graphics is a benefit Experience with OpenGL/OpenCL/D3D programming is a benefit ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RG2 #LI-Hybrid

Hiring Now: Design Verification Engineers (Multiple Openings) Locations: Bangalore & Pune Experience: 4+ to 18 Years Notice Period: Immediate to 30 Days Email: prabhu.p@acldigital.com WhatsApp: 8754387484 Current Openings 1 Senior Design Verification Engineer 10+ Years (Bangalore) – 1 Position Strong expertise in SystemVerilog (SV) and UVM-based verification Mandatory : Experience with ARM Coresight Debug subsystem Strong debugging and problem-solving skills 2 Design Verification Engineer – 5+ Years (Bangalore) – 2 Positions Proficient in SystemVerilog (SV) and UVM Preferred : ARM Coresight Debug subsystem knowledge Strong debugging expertise required 3 Design Verification Engineer – 8+ Years (Bangalore) – 2 Positions Solid experience with SV and UVM Mandatory : CSI/DSI Protocol knowledge Excellent debugging capabilities 4 Design Verification Engineer – 8+ Years (Pune Preferred / Bangalore) – 2 Positions Expertise in SystemVerilog (SV) and UVM Mandatory : Experience with Memory Controller or Cache Strong debug experience is essential Why Join ACL Digital? Work on cutting-edge SoC & IP designs with global semiconductor leaders Opportunity to contribute across leading technology nodes Fast-paced, innovation-driven culture with career growth opportunities Interested candidates can apply now by sharing their CV to prabhu.p@acldigital.com or WhatsApp 8754387484 .

Hi, Greetings from Thales India Pvt Ltd.....! We are hiring for Technical Lead - Design Verification (SV UVM) for our Engineering competency center for Bangalore location. Thales India Engineering Competency Center in Bangalore is seeking Technical Lead /Senior Technical Lead role to be part of AVS/FLX FPGA design and development team. In this role, you will be responsible for FPGA Validation & Verification for Avionics products and solutions. Responsibilities includes development of Test strategy, Virtual Verification Procedures, Test bench, BFMs, Monitors, Checkers & Virtual Verification Report as per DO254 guidelines. Qualifications: B.Tech/B.E or Masters in Electronics & Communication or equivalent with 8 to 12 years of relevant experience. Working experience in Defence\military\Aerospace products development is desirable Location: Thales India Private Limited, Richmond Town, Bengaluru, Karnataka 560025. Required Skills: Mandatory: Hands on in FPGA device Validation and Verification methodologies and processes. Experience in developing verification strategies and creating test plan based on requirements. Hands on Virtual Verification Environment development using VHDL and System Verilog/UVM Should be experienced in BFM development, monitors, checkers and Test case development using VHDL and SV/UVM Hands on with physical verification methodologies for various FPGA devices Good experience in Requirements Capture, developing Design Specification, Detailed design, Test procedure, Test report & other technical artefacts. Hands on experience in performing simulations using the Questasim tool. Should be hands on with configuration management tools such as GIT, BIT Bucket, DOORS, GIT/BIT Bucket/ REQTIFY/DOORS Good experience in RTL Design using VHDL, FPGA Implementation, Testing, Integration and delivery of FPGA based hardware systems for Defense\military\Aerospace Applications. Experience in any scripting language for automation, such as Python, Perl or TCL Experienced with Jenkins for continuous integration and automation of test and build processes. Capable of independently managing project planning, estimation, scheduling, technical risk identification and mitigation. Experience in Intel, Microchip or Xilinx based FPGA/PLD will have added advantage Experience in Bus Interfaces - A818, A429, SPI/UART/I2C, PCIe, AXI4, A664, LVDS, DDRx Should be experienced with environment to work in a cross-functional and multi-national global team. Expected to be Familiar: Experience in FPGA validation and verification in line with DO-254 process Experience in FPGA Implementation Tools (XILINX Vivado/ALTERA Libero SoC/ ALTERA Quartus). Experience in JIRA (Project / Issue management) Experience in handling Lab equipment (Logic Analyzer, Oscilloscope, Function Generators, JTAG, and In-circuit de-buggers).

Roles & Responsibilities: Be part of a team to verify or emulate/prototype complex system on a chip designs. Interact with design engineers to identify important verification scenarios. RTL Design / porting of ASIC RTL targeting FPGA prototyping and emulation platforms, such as Synopsys ZEBU, Cadence Palladium or Siemens Veloce Synthesis, PNR and timing analysis of RTL on industry standard prototyping and emulation platforms Qualification, Experience & Skills desired: Bachelor's degree in Electrical/Electronics Engineering with 5+ years of relevant experience, or masters degree in Electrical Engineering Skilled in FPGA design techniques, RTL Design, tools and processes. Minimum 5 years and above experience in digital design/verification, emulation/ FPGA prototyping and system validation. Verilog/SystemVerilog based verification experience at Subsystem and Full chip level. Experienced in transactor-based verification. Verification methodology like UVM/OVM knowhow is a plus. Knowledge of RTL language (e.g., VHDL, Verilog), in-circuit emulation, simulation acceleration and FPGA prototyping. Familiar with emulation/prototyping tools and methodologies. Real experience of mapping complex SOC design into multi-FPGA platforms/emulators and hands on experience with Synopsys ZEBU, Cadence Palladium, Siemens Veloce or HAPS A proven track record with emulation-based verification methodologies including ownership of a suitably complex emulation workflow environment. Well versed in model building for prototyping or emulation. Experience with STA/timing closure, wrapper creation, HDL simulation, synthesis, and memory modelling for prototyping/emulation. Working knowledge of Perl, Python & Shell scripts is a plus Experience with digital systems based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols. Experience with SOC boot flow, writing basic test cases, clocking and platform bring up in Emulators or Silicon desired Interested in and passionate about staying updated with tech trends. Excellent verbal and written communication skills to communicate issues, impact and corrective action.

Rambus, a premier chip, and silicon IP provider, is seeking to hire an exceptional mid-level Design and Verification Engineer to join our PHY integration team The successful candidate will participate in pre-silicon RTL Design and Verification activities related to PCIe and CXL Controller Soft IP development and PHYs integrations, on leading-edge PCI-Express and CXL controller technologies This is a Full Time position Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles Responsibilities Verilog RTL design in order to integrate different IPs together such as PCIe IP with vendor PHY module Verifying the IP integration with dedicated simulation environment Development and support test cases of different verification environments Support worldwide customers on the IP integration Get familiar to existing verification process, propose improvements Maintain the traceability from the customer specification or the product specification to the architecture and verification results Track and maintain verification productivity metrics Reporting periodically on progress and difficulties Qualifications Positive and self-driven achiever with: "Can Do" Attitude Bachelor or Master's degree in Electronics Engineering, Computer Science, or related disciplines Strong analytical and problem-solving skills Excellent interpersonal skills Open for traveling abroad Work in international organization and specially with teams in France, USA, Taiwan and India Because Rambus operates internationally, very good English is important for the position Your technical experience: 6+ years experience verification with Verilog, SystemVerilog, FPGA prototyping 6+ years experience with complex ASIC/VLSI verification 6+ years experience with Avery or UVM Any 3rd party VIP experience is a plus 6+ years experience in multinational company Experience with creating documentation, python, shell & etc About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrows systems Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures If you require assistance or an accommodation due to a disability, please feel free to inform us in your application Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services For more information about Rambus, visit rambus, For additional information on life at Rambus and our current openings, check out rambus,/careers/

Responsibilities Be the primary point of contact for IP and SoC functional verification for cross-functional teams. Participate with architecture, design teams, silicon validation, and software teams in defining the overall verification strategy of our SoCs. Develop high-performance and low power hardware to enable Google's continuous innovations in consumer hardware. Minimum qualifications: Bachelor's degree in Computer Science or Electrical Engineering or equivalent practical experience. 5 years of experience in driving/leading functional verification for Intellectual Properties (IPs) and System-on-a-Chip (SoCs). Experience working with System Verilog and Universal Verification Methodology (UVM). Preferred qualifications: Master's degree in Computer Science or Electrical Engineering or equivalent practical experience. Experience leading design verification of an SoC or large ASICs. Experience in different verification techniques and methodologies, including formal, Gate Level Simulation, Unified Power Format based Power simulations, UVM, etc. to achieve bug-free Silicon in complex SoC. Experience in scripting languages (e.g., Python, Perl) for automation and analysis. Experience in driving cross-functional teams for high quality tape-outs.

Role Responsibilities: Plan and develop formal verification strategies for complex digital design blocks. Create properties and constraints using formal verification tools for property verification. Resolve verification challenges and improve methodologies for better results. Architect and implement reusable components to enhance formal verification processes. Job Requirements: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience with verification methodologies and languages such as UVM and System Verilog. Experience with designing and maintaining verification test benches and environments.

Role Responsibilities: Verify complex digital design blocks (e.g., GPU, CPU, Image processors) by analyzing design specifications and working with design engineers. Create and enhance constrained-random verification environments using SystemVerilog, UVM, or formal verification techniques with SystemVerilog Assertions (SVA). Write coverage measures for stimulus and corner cases, ensuring thorough testing of the design. Debug tests in collaboration with design engineers to ensure functional correctness and close coverage gaps before tape-out. Job Requirements: Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, or equivalent practical experience. 3 years of experience with standard GPU workloads like Manhattan/3DMark and knowledge of GPU architecture. Experience with AMBA Bus protocols like AHB/AXI/ACE. Experience in creating verification environments and debugging designs.

You will be responsible for leading the verification efforts for complex System on Chips (SoCs) and multi-chiplet System on Packages at Krutrim. This includes developing verification plans, testbench environments, and reusable verification IP. You will work on module, sub-systems, chiplets, and complex multi-chiplet testbench environments. Additionally, you will be involved in developing UVM and C/Python based testbench environments for functional, netlist, and power simulations. You will also contribute to developing reference models using System Verilog/SystemC/Python and improving verification flow and methodology. Debugging design units using simulation and formal tools and methodologies will be part of your responsibilities. Collaboration with Architects, Systems, and Software engineering teams on post-silicon debug in the lab is also expected. To qualify for this role, you should have a Bachelor's/Masters degree in Electronics Engineering and a minimum of 10 years of experience in verification of complex SoC designs. Proficiency in System Verilog, SVA, and UVM for code development is essential. Deep knowledge and experience of metric-driven verification methodology and flow are required. You should have extensive experience with various state-of-the-art simulation and formal tools, as well as expertise in verification of CPU/DPU/GPU based sub-systems. Experience with industry standard protocols such as CXL, PCIe, UCIe, and Ethernet protocols will be beneficial. Join Krutrim to be part of the team that is shaping the future of AI computing through cutting-edge silicon design.,