Sub System Verification Engineer

At MediaTek, we are driven by a relentless pursuit of excellence, leading the way in performance and innovation across diverse industry sectors. From groundbreaking advancements in mobile, automotive, consumer, and industrial devices to transformative breakthroughs in datacenter computing, MediaTek is on a journey to redefine what is possible. At MediaTek, we are not only re-imagining the future; we are creating it. Come be a part of it.

Join our team of exceptionally talented professionals at our Bangalore design center, where we are pioneering cutting-edge technologies that will power the next generation of smartphone chips, IoT and automotive devices, and edge computing solutions. Be a part of MediaTek and help us shape the future of technology.

Mediatek is building Sub System DV teams in Bangalore to cater to the verification challenges in our next gen Smartphone, Compute and Automotive chips. We are seeking experienced Design Verification Engineers with 3-15 years of experience, specifically in subsystem verification or SoC verification, to join our highly talented verification team at Bangalore.

The candidate needs to have a strong background in Sub System verification methodology and flows. Should have exposure to different verification methodologies at Sub System or SoC Level. Experience in test planning & testbench design/improvements and coverage closure is needed. Low power verification exposure is a plus.

Must have strong System Verilog programming skills and experience with UVM methodology. Should possess excellent problem-solving skills and ability to work collaboratively in a fast-paced environment spanning across geographies.

Senior candidates with experience in leading teams will be considered for higher/lead roles.

Key Responsibilities:

• Develop and implement comprehensive verification test plans for subsystems components and IP’s in those sub-system.
• Build testbenches from scratch for new Sub systems, develop verification flows and test cases using System Verilog and UVM methodology.
• Drive functional verification of RTL designs at Sub System level or SoC Level including simulation, debugging and coverage closure, ensuring high-quality and robust designs.
• Collaborate with design engineers to understand detailed design specifications and target corner cases and various configurations of subsystem levels.
• Generate and analyze verification metrics to regularly track progress and ensure timely coverage closure.
• Participate in design and verification reviews, test plan reviews, methodology reviews, providing technical expertise and insights.
• Incorporate newer verification techniques and methodologies to improve verification efficiency and effectiveness.
• Guide and mentor junior verification engineers and provide technical guidance .

Qualifications & Experience:

• Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related fields from an institute of repute.
• Proficiency in verification languages and methodologies, such as SystemVerilog, UVM, and other industry-standard tools.
• Experience with scripting languages (e.g., Python, Perl, Tcl) for automation and tool integration.
• Excellent problem-solving skills and attention to detail.
• Need to have strong oral and written communication skills, with an ability to work as a team player in a fast-paced collaborative environment.
• Track record of successfully participating in or leading verification of complex IP blocks, Subsystems or SoC Modules.
• 3-15 years of experience in design verification, with a focus on Subsystem/SoC verification. Candidates with higher experience will be considered for senior or lead roles. Prior experience of leading teams is needed for Lead role.