Static Timing Analysis (STA) Place and Route (PNR)

Job Summary

Static Timing Analysis (STA) & Place and Route (PNR)

Key Responsibilities

 Lead STA and PNR activities for complex subsystems, ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization.

 Develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.

 Drive automation and validation of timing and physical design data across subsystem boundaries.

 Mentor and guide junior engineers, fostering technical growth and knowledge sharing within subsystem teams.

 Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.

 Exhibit excellent communication skills to present technical solutions and lead discussions with internal teams and customers, especially regarding subsystem-level trade-offs and integration

Qualifications and Skills

10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).

 Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.

 Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.

 Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.

 Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.

 Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level preferred.

 Background high-speed interfaces, or mixed-signal SoC subsystems