Staff Software Engineer - EDA Formal Verification

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned engineering professional with a passion for solving complex challenges and driving technological advancement. With a BS/BE in Electrical or Computer Engineering and at least Five years of relevant industry experience, you pride yourself on your deep understanding of software development, data structures, and algorithms. Your expertise spans across C/C++, legacy code bases, and emerging technologies, giving you the flexibility to adapt and grow in fast-paced environments.
You thrive both independently and as part of a collaborative team, leveraging your strong communication skills to bridge technical concepts with actionable solutions. You have a keen interest in formal verification, synthesis techniques, and the latest advances in distributed processing, machine learning, and big data. Your hands-on experience with Verilog, VHDL, and System Verilog allows you to contribute meaningfully to the design and development of cutting-edge EDA solutions for digital SOC chip designs. As a lifelong learner, you eagerly embrace new methodologies and enjoy mentoring others, sharing your knowledge to elevate the team’s capabilities. You are motivated by the opportunity to make a significant impact—driving innovation, shaping product direction, and delivering sign-off quality solutions that empower customers worldwide. Whether architecting new algorithms or engaging with global clients, you bring enthusiasm, creativity, and technical leadership to every challenge you encounter.

What You’ll Be Doing:

• Designing and developing advanced algorithms for formal equivalence checking in complex digital SOC designs.
• Architecting innovative solutions to enhance runtime, memory efficiency, and supporting state-of-the-art synthesis optimizations.
• Collaborating with a dynamic R&D team to develop, prototype, and deliver high-quality EDA tools for Formality.
• Engaging in technical mentoring, sharing expertise, and guiding junior engineers to elevate overall team performance.
• Interacting with global customers across computing, AI, automotive, and mobile industries to understand their needs and deliver tailored solutions.
• Applying formal verification strategies, distributed computing, and machine learning techniques to solve industry-leading challenges.
• Contributing to the enhancement of existing engines, creation of new algorithms, and deployment of innovative AI/ML technologies.
• Ensuring timely delivery of high-quality software, aligned with customer requirements and product roadmaps.

The Impact You Will Have:

• Shape the future of digital SOC chip design by delivering industry-leading formal verification solutions.
• Drive performance improvements in Formality tools, enabling customers to achieve faster and more reliable design sign-off.
• Mentor and empower fellow engineers, building a culture of knowledge sharing and technical excellence.
• Enhance Synopsys’ reputation as a leader in EDA innovation, contributing to successful chip launches in high-growth markets.
• Bridge the gap between customer needs and product capabilities, ensuring solutions are practical, scalable, and impactful.
• Accelerate the adoption of advanced technologies, including AI/ML and distributed processing, within the formal verification domain.
• Help customers deliver their next big innovation—whether in AI, automotive, computing, or mobile—by providing robust, sign-off-ready solutions.

What You’ll Need:

• BS/BE degree in Electrical or Computer Engineering (or related field) with at least 8 years of relevant experience.
• Proficiency in software development using C or C++.
• Strong grasp of data structures, algorithms, heuristics, and their practical applications.
• Experience in formal verification, synthesis techniques, and equivalence concepts.
• Knowledge of solver algorithms such as SAT or BDD, and familiarity with regression testing and software design processes.
• Hands-on experience with Verilog, VHDL, and System Verilog.
• Understanding of distributed processing, big data, and machine learning techniques is a plus.
• Demonstrated ability to work with complex legacy code bases and learn new technologies quickly.

Who You Are:

• An innovative problem solver with a keen analytical mindset.
• A collaborative team player who values open communication and shared success.
• A technical leader willing to mentor and guide others.
• Adaptable and resilient when faced with evolving technical challenges.
• Proactive in seeking out new knowledge and sharing insights.
• Detail-oriented with a commitment to delivering high-quality solutions.
• Effective communicator, able to translate complex ideas into practical outcomes.

The Team You’ll Be A Part Of:

You’ll join the Formality R&D team—an enthusiastic, creative, and highly skilled group of engineers focused on developing world-class formal verification tools. The team collaborates closely, values technical mentorship, and is driven by a shared mission to advance the capabilities of digital SOC chip design. You’ll work alongside experts in design methodology, EDA solutions, and algorithm development, with opportunities to interact with customers and learn from diverse fields.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.