Sr. ASIC Engineer (UVM | System Verilog | Scripting)

Cisco

7 - 12 years

12 - 17 Lacs

bengaluru

Posted:1 day ago| Platform:

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Skills Required

scripting switching python design verification ai public sector networking uvm verilog asic design ve formal verification design wireless perl networking hardware cisco architecture

Work Mode

Work from Office

Job Type

Full Time

Job Description

Your Impact-

You will contribute to developing Ciscos progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security
Specific responsibilities include:- Architect block, cluster and top-level DV environment infrastructure
- Develop DV infrastructure from scratch
- Maintain and improve existing DV environments
- Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus
- Ensure complete verification coverage through implementation and review of code and functional coverage
- Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist
- Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance
- Support testing of design in emulation
- Lead all aspects of and manage the ASIC bring-up process

Minimum Qualification:

- Bachelors Degree or equivalent experience in EE, CE, or other related field
- 7+ years of related ASIC design verification experience
- Proficient in ASIC verification using UVM/System Verilog
- Proficient in verifying sophisticated blocks, clusters and top level for ASIC
- Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes

Preferred Qualifications

- Scripting experience with Perl and/or Python
- Experience with data path verification, performance tests- Experience with Veloce/Palladium/Zebu/HAPS
- Formal verification (iev/vc formal) knowledge
- Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, TCP)

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