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SoC Static Timing Analysis Engineer, Silicon

SoC Static Timing Analysis Engineer, Silicon

Google

3 - 6 years

6 - 10 Lacs

bengaluru

Posted:21 hours ago| Platform:

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Skills Required

physical design static timing analysis soc floorplan computer science drc fpga perl tcl system verilog architecture synthesis asic sta python c primetime lvs timing analysis verilog floor planning silicon timing closure pnr synopsys placement vlsi

Work Mode

Work from Office

Job Type

Full Time

Job Description

Google is looking for SoC Static Timing Analysis Engineer, Silicon to join our team
Roles and Responsibility

Design and develop static timing analysis tools and methodologies for complex digital circuits.
Collaborate with cross-functional teams to identify and resolve timing-related issues in SoC designs.
Develop and maintain detailed documentation of static timing analysis results and reports.
Participate in design reviews and provide feedback on timing constraints and requirements.
Work closely with the verification team to ensure successful integration of static timing analysis into the overall verification strategy.
Identify and implement process improvements to increase efficiency and effectiveness of static timing analysis.

Job Requirements

Strong understanding of digital circuit design principles and methodologies.
Experience with static timing analysis tools and technologies, such as STA or ICC2.
Excellent problem-solving skills and attention to detail.
Strong communication and collaboration skills.
Ability to work in a fast-paced environment and meet deadlines.
Bachelor's degree in Electronics Engineering or related field.

Disclaimer: This job description has been sourced from a public domain and may have been modified by Naukri.com to improve clarity for our users. We encourage job seekers to verify all details directly with the employer via their official channels before applying.

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SoC Static Timing Analysis Engineer, Silicon