SoC Static Timing Analysis Engineer, Silicon

Job Description: You will be part of a team that develops custom silicon solutions for Google's direct-to-consumer products. Your contribution will be crucial in shaping the next generation of hardware experiences, ensuring unparalleled performance, efficiency, and integration. As a member of Google's Silicon team, you will work on hardware and software for Application Specific Integrated Circuits (ASIC), driving the complete design constraints development and validation process. Your role will involve designing and building computing infrastructure systems, from circuit design to large system design, and overseeing the manufacturing process. Responsibilities: - Create design constraints based on architecture/microarchitecture documents, considering various external Input Output (IO) protocols. - Validate design constraints across multiple corners/modes using Fishtail/Timevision tools. - Utilize Primetime for running and validating constraints post-synthesis runs, setting up timing constraints, and defining the overall static timing analysis (STA) methodology. - Collaborate with the design team and block owners for sign-off timing convergence throughout the project. - Lead constraints promotion and demotion flow using Fishtail and Timevision tools. - Evaluate different timing methodologies/tools on diverse designs and technology nodes, working on automation scripts within STA or tools for methodology development. Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 8 years of experience with Static Timing Analysis, Constraints development, sign-off corner definitions, process margining, and setup of frequency goals with technology growth and platform development kit (PDK) changes. - Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science. - Experience with a scripting language like Perl or Python. - Experience in developing constraints and validating using Timing Constraints Manager (e.g., Synopsys) or TimeVision (e.g., Ausdia).,