10 Constraints Development Jobs

L&T Technology is looking to hire for Physical Design Engineers Experience : 5-8 Years JD is mentioned below :: Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. Can work closely with FE team for constraints development and constraints cleanup. Work with partitions/block owner to give timing ECO for timing closure. Knowledge of advanced timing closure techniques and methodology Knowledge of industry stanrd tools from Synops or Cadence. Worked on DSM technologies, tsmc 5nm and below experience preferred. Minimum 5+ of relevant experience Good scripting and communication skills

Job Description: You will be part of a team that develops custom silicon solutions for Google's direct-to-consumer products. Your contribution will be crucial in shaping the next generation of hardware experiences, ensuring unparalleled performance, efficiency, and integration. As a member of Google's Silicon team, you will work on hardware and software for Application Specific Integrated Circuits (ASIC), driving the complete design constraints development and validation process. Your role will involve designing and building computing infrastructure systems, from circuit design to large system design, and overseeing the manufacturing process. Responsibilities: - Create design constraints bas...

Hi All, Eximietas Hiring Senior Physical Design Leads/Managers. Experience: 10+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. About the job Qualification Required: Typically requires a minimum of 10+ years of experience in Physical Design with mainstream P&R tools Bachelors OR Masters Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering. Roles And Responsibilities Working on 10nm/7nm/5nm or lower nodes designs with various customers for deployment. Expertise in solving customers problems for critical designs to achieve desired performance, area, and power targets. Responsible for developin...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly experienced and motivated professional with a solid background in SoC RTL Design. With over 12 years of experience, you have honed your skills in RTL Design, Lint, CDC, RDC, Synthesis, and Constraints Development. You possess a deep understanding of design concept...

LTTS is looking for STA engineers with 5+ Years of experience, Detailed JD is mentioned below :: Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. Can work closely with FE team for constraints development and constraints cleanup. Work with partitions/block owner to give timing ECO for timing closure. Knowledge of advanced timing closure techniques and methodology Knowledge of industry stanrd tools from Synops or Cadence. Worked on DSM technologies, tsmc 5nm and below experience preferred. Minimum 5+ of relevant experience Good scripting and communication skills

L&T Technology is hiring for STA Engineers / Physical Design Engineers with 4-8 years of experience. Job Location : Bangalore Detailed JD is below :: Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. Can work closely with FE team for constraints development and constraints cleanup. Work with partitions/block owner to give timing ECO for timing closure. Knowledge of advanced timing closure techniques and methodology Knowledge of industry stanrd tools from Synops or Cadence. Worked on DSM technologies, tsmc 5nm and below experience preferred. Minimum 4+ of relevant experience Good scripting and communication skills

L&T Technology is looking to hire for STA Engineers. Job Location : Bangalore Detailed JD is below :: JD For STA Engineer-6+ experience Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. Can work closely with FE team for constraints development and constraints cleanup. Work with partitions/block owner to give timing ECO for timing closure. Knowledge of advanced timing closure techniques and methodology Knowledge of industry stanrd tools from Synops or Cadence. Worked on DSM technologies, tsmc 5nm and below experience preferred. Minimum 5+ of relevant experience Good scripting and communication skills

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with Static Timing Analysis, Constraints development and its validation, sign-off corner definitions, process margining, and setup of frequency goals with technology growth and platform development kit (PDK) changes. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science. Experience with a scripting language like Perl or Python. Experience in developing constraints and validating using Timing Constraints Manager (e.g., Synopsys) or TimeVision (e.g...

As a member of the team at Google, you will play a crucial role in developing custom silicon solutions for Google's direct-to-consumer products, contributing to the innovation that impacts millions globally. Your expertise in electrical engineering or computer science will be instrumental in shaping the future of hardware experiences, focusing on performance, efficiency, and integration. **Key Responsibilities:** - Create design constraints based on architecture/microarchitecture documents, understanding various external IO protocols. - Validate design constraints across multiple corners/modes using Fishtail/Timevision. - Utilize Primetime for running and validating constraints post synthesi...

We are seeking an experienced RTL Design Engineer to be a part of our advanced ASIC/SoC development team in Bengaluru. As an RTL Design Engineer, you will be responsible for developing high-quality, synthesizable RTL code using Verilog/SystemVerilog and integrating complex IPs and subsystems into high-performance SoCs. Collaboration with system architects, contribution to micro-architecture, and ensuring design quality through checks like Lint, CDC, and Synthesis will be key aspects of this role. Your responsibilities will include leading SoC-level integration activities, providing technical guidance in design reviews, and interfacing with cross-functional teams for smooth bring-up and signo...