636 Silicon Jobs - Page 2

In today s world of faster and more virtualized servers, storage, and network connections, CPUs cannot keep up with the growing network processing demands. Legacy or foundational network interface cards (NICs) may deliver efficient networking however when running demanding workloads, they cause overhead that burdens CPUs, chewing into available processing power. To deploy more advanced networking capabilities a new generation of intelligent NICs are required to deliver accelerations and additional processing power to offload CPUs. The industry-leading NVIDIA SmartNICs/DPUs (Data Processing Units) provide sophisticated hardware offloads and accelerated networking, storage, security, and manageability services for modern cloud, artificial intelligence, telecommunications and traditional enterprise workloads. With unmatched RDMA over Converged Ethernet (RoCE) performance, NVIDIA SmartNICs/DPUs deliver efficient, high-performance remote direct-memory access (RDMA) services to bandwidth- and latency-sensitive applications. The NBU team in India is a new team that is growing at a fast pace. We are currently seeking an Experienced Verification Engineer with strong verification fundamentals to work in NBU ASIC team. You will join a group of hardworking engineers to implement the next innovative Networking Silicon chip. In this position, youll make a real impact in a multifaceted, technology-focused company while developing the industrys best high-speed communication devices, delivering the highest throughput and lowest latency! What you ll be doing: Be responsible for verifying the smartNIC/DPU designs, architecture and micro-architecture using advanced verification methodologies. You are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems. Use advanced verification methodologies like e-specman, SV-UVM etc. What we need to see: BS / MS (or equivalent experience) with 10+ years of experience in design verification. Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc. ). C/C++ programming/scripting language experience desirable. Ways to stand out from the crowd: Prior experience of smartNIC and/or high-speed interconnects. Strong debugging, problem-solving and analytical skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a phenomenal teammate. Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www. nvidiabenefits. com/ #LI-Hybrid

Sodexo Food Solutions India Pvt. Ltd. is looking for Carpenter to join our dynamic team and embark on a rewarding career journey Measurement and Planning: Measure and plan the layout and design of structures or components to ensure precision and accuracy in construction Cutting and Shaping: Cut and shape wood, metal, or other materials using hand and power tools like saws, chisels, and routers Assembly: Assemble and join pieces of wood or materials using screws, nails, adhesives, and other fastening methods to create structures, such as furniture, cabinets, or buildings Installation: Install doors, windows, moldings, cabinets, and other fixtures in homes, offices, and construction projects Framing: Build structural frameworks and frames for buildings, including wall framing, roof trusses, and floor systems

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

Are you passionate about ensuring silicon design accuracy and power integrity at advanced nodes? We re looking for a skilled PDV & Power Analysis Engineer to join our growing team! Key Responsibilities: -Physical design verification and power analysis using Calibre, Innovus, and Voltus -Hands-on layout edits in Innovus and deep analysis of IR/EM reports from Voltus -Expertise in understanding and resolving DRC violations using Calibre and Innovus -Strong knowledge of IR drop and electromigration issues and their resolution -Scripting proficiency in TCL, AWK, and Python -Exposure to ADI flows and power domain-based designs is a strong advantage Who Should Apply: Engineers with a strong background in PDV and power integrity, comfortable working with industry-standard EDA tools and scripts, and who thrive in a collaborative environment.

Are you passionate about driving performance at the silicon levelWe are looking for an experienced STA Engineer with 5+ years of expertise in Static Timing Analysis (STA) to join our team! Key Responsibilities: Perform timing analysis, validation, and debug across multiple PVT corners using Tempus Hands-on experience with Tempus DMMMC flow for STA Handle STA setup, convergence, reviews, and signoff for both scan and functional modes Review unconstrained endpoints and analyze detailed timing reports Deep understanding of noise, crosstalk, and OCV effects Experience with block-level and full-chip timing closure at advanced nodes like 22nm, 16nm, 5nm Collaborate with cross-functional teams (design, synthesis, PnR) for smooth closure Scripting knowledge in TCL and Python Prior experience with ADI/Cadence flows and power domain-based designs is a plus

Staff Software Engineer The Software (CE-SW) group is responsible for developing and improving the software ecosystem around Arms next generation of applications processors and IP. This means working with processors and other hardware technology not yet available to the public. You will join a team of Software Engineers who share a passion for leaving their mark on the future of computing. If you are similarly passionate about innovative technologies, then we want to hear from you! Responsibilities: We are looking for highly capable engineers to work in the areas of Client/Server/Automotive/IoT, ready to use their knowledge and experience to ensure we continue to deliver software with the level of quality demanded by our customers. Day-to-day activities will include: Participating in the design, implementation of new features, integration and debugging of firmware for reference application processor. Development, debugging and testing of features and its integration on different platforms including software models, development boards and shipping products. We want you to be able to analyze industry specs, roadmap requirements, breakdown tasks and help implement the project plans. Your activities will involve upstreaming and maintenance. Required Skills and Experience : 8+ Years of relevant work experience in firmware development for Linux/Zephyr based system software. Expertise in application and low-level systems, with a strong understanding of system architecture (preferably ARM), OS fundamentals, bootloaders, and device drivers. Proficiency in Linux/Zephyr operating systems and driver development is preferred. Good understanding of industry standards: I2C, I3C, SCMI, UART, MCTP, PLDM. Familiarity with either of the technologies such as remote manageability, telemetry, power or security. Excellent C/C++ programming with some knowledge of assembly and debugging skills. Strong interpersonal skills; excellent written and spoken English; capable of writing documentation and mentoring of junior engineers. Nice To Have Skills and Experience : Familiarity with open-source project development cycles and contribution processes. Experience of software profiling, instrumentation, and optimization. Verification and validation of firmware on both pre-silicon and post-silicon platforms. A knowledge of how to test software using various techniques alongside an awareness of the value of CI and automated test systems. Mentoring and line management experience. Accommodations at Arm At Arm, we want to build extraordinary teams. . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm

SMTS SILICON DESIGN ENGINEER (AECG ASIC PD FCL Lead) T HE ROLE : We are looking for an adaptive, self-motivative design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. K EY RESPONSIBLITIES : Handling SOC floorplanning/Partitioning, Die size estimation Experience on abutted and non-abutted designs Handling of Hierarchical designs (Subfcs), Block partitioning, block pin placement, Feedthrough punching, HFN implementation Planning clock Mesh/Tree at SOC/Sub System level Full SOC bump planning including GPIO Bump Placement, Pad ring generation/GPIO placement, Hard IP bump placement, GPIO and PG RDL routing Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams P REFERRED EXPERIENCE : 12+ years of professional experience in physical design, preferably ASIC designs. Knowledge on bump placement/critical IP placement. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4

Chryselys Overview Chryselys is a Pharma Analytics & Business consulting company that delivers data-driven insights leveraging AI-powered, cloud-native platforms to achieve high-impact transformations. Chryselys was founded in the heart of Silicon Valley in November 2019 with the vision of delivering high-value business consulting, solutions, and services to clients in the healthcare and life sciences space. We are trusted partners for organizations that seek to achieve high-impact transformations and reach their higher-purpose mission. Chryselys India supports our global clients to achieve high-impact transformations and reach their higher-purpose mission. Our India team focuses on development of Commercial Insights platform and supports client projects. Role Summary As a Consultant, you will work closely with internal and external stakeholders and deliver high quality analytics solutions to real-world Pharma commercial organization s business problems. You will bring deep Pharma / Healthcare domain expertise and use cloud data tools to help solve complex problems Key Responsibilities: Collaborate with internal teams and client stakeholders to deliver Business Intelligence solutions that support key decision-making for the Commercial function of Pharma organizations. Leverage deep domain knowledge of pharmaceutical sales, claims, and secondary data to structure and optimize BI reporting frameworks. Develop, maintain, and optimize interactive dashboards and visualizations using Tableau (primary), along with other BI tools like Power BI or Qlik, to enable data-driven insights. Translate business requirements into effective data visualizations and actionable reporting solutions tailored to end-user needs. Write complex SQL queries and work with large datasets housed in Data Lakes or Data Warehouses to extract, transform, and present data efficiently. Conduct data validation, QA checks, and troubleshoot stakeholder-reported issues by performing root cause analysis and implementing solutions. Collaborate with data engineering teams to define data models, KPIs, and automate data pipelines feeding BI tools. Manage ad-hoc and recurring reporting needs, ensuring accuracy, timeliness, and consistency of data outputs. Drive process improvements in dashboard development, data governance, and reporting workflows. Document dashboard specifications, data definitions, and maintain data dictionaries. Stay up to date with industry trends in BI tools, visualization of best practices and emerging data sources in the healthcare and pharma space. Prioritize and manage multiple BI project requests in a fast-paced, dynamic environment. Qualifications: 2 4 years of experience in BI development, reporting, or data visualization, preferably in the pharmaceutical or life sciences domain. Strong hands-on experience building dashboards using Tableau (preferred), Power BI, and Qlik. Advanced SQL skills for querying and transforming data across complex data models. Familiarity with pharma data such as Sales, Claims, and secondary market data is a strong plus. Experience in data profiling, cleansing, and standardization techniques. Ability to translate business questions into effective visual analytics. Strong communication skills to interact with stakeholders and present data insights clearly. Self-driven, detail-oriented, and comfortable working with minimal supervision in a team-oriented environment. Exposure to data warehousing concepts and cloud data platforms (e.g., Snowflake, Redshift, or BigQuery) is an advantage. Education Bachelor s or Master s Degree (computer science, engineering or other technical disciplines)

Job Title: Senior or Principal Software Systems Engineer We are looking for an experienced full-time engineer to provide software development support for high energy density battery power applications. An ideal candidate is an experienced systems engineer with a software interest and focus capable of developing user interface and control system software. The candidate should be comfortable developing graphical user interface software that translates technically complex system information into a human relatable interface. The candidate should also be comfortable creating, modeling, and analyzing management and control algorithms as they apply to battery and power applications. Job Description: Design software to interface users with complex battery management and control systems, Model and develop management and control algorithms for power system applications, Provide design and test support for manufacturing systems development. Desired Skills/Abilities: Software development in C++ and common workflow for PC application development. Python-based development. Knowledge of programmable logic controllers (PLC). Knowledge of real-time design techniques for embedded systems. Knowledge of digital signal processing techniques Embedded programming for digital signal controllers and small microcontrollers. Embedded C programming. Knowledge of power converter topologies, control, and design. Qualifications: Bachelor s degree 5+ years experience in electrical engineering or Computer Science Self-motivated and high energy Strong organization, communication and interpersonal skills About Enovix: Industries of the future Artificial Intelligence, Edge computing, 5G, Electric Vehicles, Augmented Reality and Virtual Reality all require greater battery energy capacity. Building and scaling a 100% active silicon anode has long been a goal of the battery industry because it dramatically increases capacity and performance. Enovix, based in Fremont, California, is the first company in the world to be capable of volume production of advanced Lithium-ion batteries with a 100% active silicon anode using its 3D cell architecture. The company has designed, developed and sampled advanced Lithium-ion batteries with energy densities five years ahead of current industry production. Enovix s initial goal is to provide designers of category-leading mobile devices with a high-energy battery so they can create more innovative and effective portable products. Enovix is also developing its 3D cell technology and production process for the EV and energy storage markets to help widespread use of renewable energy. Enovix in an equal opportunity employer.

Need to work in collaboration with global analog teams across sites. Will be responsible for driving innovation in Analog IP designs. Responsible for design of IPs like Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools. Should provide technical leadership and mentor junior engineers. Responsible for developing processes and robust design methodology. Help build overall competency in Analog domain. Qualifications Bachelor or Master Degree in Electrical/Electronic Engineering with 12+ years of experience in Analog design across different technologies. Should have experience in developing analog IPs like Switch capacitor circuits, LDO, DC-DC converter, oscillator, ADCs, Should have experience in integrating Analog IPs in a complex system. Knowledge of PCB and system design will be preferred. Should experience in silicon characterization and probing. Should have experience in a multi-site environment, interacting with teams in other sites. Should possess good mentorship skills. Ability to coordinate priorities and initiatives

Develop and maintain prototyping environments, verification frameworks, and reusable infrastructure to support seamless transition from pre-silicon to post-silicon validation. Collaborate with cross-functional teams including Architecture, Design, Verification, and Partner teams to drive project execution and influence future silicon designs. Participate in silicon bring-up activities and develop verification firmware to support silicon bring up, validation and debug efforts. Create detailed test plans, develop C-based tests, and develop validation infrastructure to validate complex microprocessor designs. Execute tests, debug failures, and develop stress and performance scenarios to meet validation goals. Continuously innovate and enhance validation methodologies and tools to improve efficiency and coverage. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Bachelor’s degree (BE/B.Tech) in Electrical Engineering, Computer Engineering, or a related field. 5+ years of experience in microprocessor verification or validation (pre- or post-silicon), with a strong track record in building test infrastructure and automation. Proficiency in Python and C/C++. Solid understanding of microarchitecture (x86 or other architectures), technical debug and validation strategy

Your Role and Responsibilities Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. . Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Technical and Professional Expertise 4 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications,processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Nice to haves -Knowledge of verification principles and coverage. -Knowledge of test generation tools and working with ISA reference model. -Experience with translating ISA specifications to testplan. -Understanding of Agile development processes. -Experience with DevOps design methodologies and tools. Preferred technical and professional experience Work with Hiring Manager to ID up to 3 bullets max (encouraging then to focus on required skills) Advanced Verification Techniques: Familiarity with advanced verification techniques such as RAS verification is a plus Experience with Hardware Description Languages (HDLs): Proficiency in hardware description languages like Verilog and VHDL, enabling seamless collaboration with design teams and enhancing verification effectiveness. Experience in System-Level Verification: Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design abstraction.

Your Role and Responsibilities Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Technical and Professional Expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Nice to haves - Knowledge of instruction dispatch and Arithmetic unit. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Knowledge of verification principles and coverage. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.

THE ROLE: As the one of the design leads of the Programmable Clock & Methodologies team in India for AMD's Adaptive-Embedded Computing products, you will be responsible for driving the development of clocking solutions that meet the high standards of AMD's AECG products. This will involve leading a team of highly skilled engineers in India, as well as collaborating with the global Clock team of experts at the San Jose office, inventing and implementing original solutions, addressing challenging clock problems in some of the industry's largest and most complex SOCs. Every new Adaptive SOC brings a new set of programable Clock challenges with their latest system and functional architectures and their adoption of new semiconductor and packaging technologies. The Global Clock team works closely with functional Architecture, Programable fabric, Integration and SW teams to craft and implement new clock solutions, including new architectures, Clock IPs and development of new tools, flows & Methodology. THE PERSON: You will lead by bringing people together and drive towards consensus, decisions, and results. Working independently, you will convert high level concepts down to tangible specifications that can be implemented efficiently. You should enjoy collaborating with engineers with their diverse skillsets and bring their expertise to bear on solving challenging Programable Clock problems. KEY RESPONSIBILITIES: Lead floor-planning, placement, routing, custom clock tree design, and optimization. Expert knowledge and hands-on experience of the entire backend and adjacent flows, including synthesis, Floor-planning P&R, clocking, timing closure, power and IO planning Perform all aspects of design flow from feasibility analysis, logic synthesis, FP, place and route, FEV, power, timing, quality checks, and design closure. Collaborate with design, Physical design, IT/infrastructure teams to ensure successful CAD flow all the way from IP design to SoC/3DIC design. Developing Programable global Clock distribution methodologies, optimizing Clock - Skew, Signal integrity and power integrity issues for AMD's next generation of programmable product families. Large Scale Block to Block Clock timing analysis, within the Die & Die to Die Clock interposer crossing. Deep analysis of timing paths to identify and debug key issues. Collaborate with functional IP teams (RTL, Ckt, physical design, Full Chip Timing, Integration) during the implementation and qualification of a growing number of programable Clock IPs. PREFERRED EXPERIENCE: You should have a deep understanding of clocking methodologies and experience in leading teams to deliver complex projects. Workingknowledge of Programable clocking is a plus. Strong working knowledge in all aspects of Physical Design and Advanced Packaging (Professional Experience: 10+ years of hands-on experience in physical design and verification, with a proven track record in chip-level PNR and successful tapeouts of complex SoC designs). You should be an expert in the development of clocking solutions and have the ability to work effectively with global teams (USA & India) to ensure that on time product delivery with high quality is met. Strong Clock fundamentals (Clock switching and gating, synchronization, Clock skew balancing, Jitter, Fmax, DCD and CDC analysis). Familiarity with test, debug, yield, post-Silicon Validation & Characterization is a plus. Working experience of Package level Clock SIPI is a plus. Proficient in STA and methodologies for timing closure and have a good understanding of noise, cross-talk, Aging and OCV effects, among others.Defined timing/SDC and placement constraints for IPs. Familiar with circuit modeling, including SPICE models, and worst-case corner selection. Familiarity with Verilog and system Verilog for design. Additionally, you should be a skilled communicator, able to provide technical guidance and mentorship to junior team members to help them develop their skills and advance their careers. ACADEMIC CREDENTIALS: Bachelor or master degree in computer engineering/Electronics or Electrical Engineering with 8-12+ years of exp.

THE ROLE: This role demands strong technical expertise in PDN design, electromigration (EM), IR drop analysis, and power integrity, along with effective leadership skills to guide and mentor a team of engineers focused on power distribution and integrity solutions. THE PERSON: As the PDN Lead, you will be responsible for designing, analyzing, and optimizing the Power Delivery Network (PDN) for complex System-on-Chip (SoC) designs. You will work closely with cross-functional teams to ensure that the PDN meets power integrity, signal integrity, and reliability requirements across advanced technology nodes. KEY RESPONSIBLITIES: Perform and lead in-depth electromigration (EM) and IR drop analysis for Soc designs, identifying areas of concern and implementing mitigation strategies to meet power integrity and reliability requirements. Work closely with physical design, package, and RTL teams to define PDN architecture, ensure robust power grid structures, and optimize on-chip decoupling. Develop, implement, and maintain EM/IR analysis flows and methodologies using tools like Synopsys RedHawk. Create and refine scripts to automate analysis and reporting tasks. Perform comprehensive signal integrity (SI) and power integrity (PI) analysis across various operating modes and temperatures, collaborating with packaging and PCB design teams to ensure robust end-to-end PDN performance. Identify root causes of EM/IR issues, work with design teams to implement fixes, and ensure solutions are verified through simulations. Mentor junior engineers in EM/IR best practices, provide training on analysis tools, and share expertise on reliability issues PREFERRED EXPERIENCE Proficiency in PDN analysis and EDA tools such as Synopsys Redhawk, or equivalent tools for power and EM/IR analysis. Strong understanding of electromigration, IR drop, and power integrity challenges in modern SoC designs. Experience in power grid design, power/ground plane distribution, and decoupling strategies. Advanced scripting skills (Python, Tcl, Perl) for automation of PDN design flows and custom analysis tasks. Strong analytical and problem-solving skills, excellent communication skills, and the ability to collaborate across multiple teams and disciplines. ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

THE ROLE: The AMD Cores system validation team is looking for a dynamic, energetic Cores Validation engineer to join our growing team focused on the Zen CPU. Cores Systems Validation Engineer will perform hands-on system level debug to isolate system level failures to a specific IP or domain. Exposure begins at the architecture level, working with pre-silicon teams to maximize pre-silicon coverage, post-silicon bring-up and enablement, and engagement through production and working with customer facing teams for best adoption. You will work in a dynamic environment, directly with the product, tools, motherboards, and BIOS/OS. THE PERSON: As a key contributor to the success of AMD's server roadmap, you will be part of a high performing team driving the delivery of high quality, industry leading processors to market. The validation team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. KEY RESPONSIBILITIES: Isolate generic system level failures into a more focused area of the platform or CPU Drive debug and resolution of Zen CPU validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed Develop x86 content to exercise new features and reproduce complex bugs in silicon Devise validation strategy from pre-silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams Proactively participating in project planning, developing, and maintaining schedules, managing dependencies, and ensuring quality of deliverables at committed milestones. Generates/Maintains regular status representing the Server Validation team in program meetings providing status to program management PREFERRED EXPERIENCE: Programming/scripting skills (e.g. C/C++, Perl, Ruby, Python) x86 assembly programming Debug techniques and methodologies Extensive experience with board/platform-level debugging, including delivery, sequencing, analysis, and optimization Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion ACADEMIC CREDENTIALS: Bachelors or Masters degree in CS/EE with 2-8 years of experience.

THE ROLE: AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as highly configurable high-speed memory I/Os/PHYs and Chiplet Interconnect IP (e.g. UCIE) to various Business Units/SoCs within AMD. The ideal candidate will get to work with circuit and FE architects to accurately model the analog digital interface boundary of high speed mixed signal IPs to accomplish timing integrity goals. KEY RESPONSIBILITIES: Analyze timing constraints for complicated static timing analysis (STA) paths including multistage generated clocks, ZCPs in a variety of mixed signal circuits. Use the appropriate margining methodology for data, clock and async timing paths to improve timing robustness and reliability. Identify noise sources in timing models and feedback to CKT and LAY for appropriate design fixes. Adopt leading industry STA and Timing Char tools to drive timing convergence in mixed signal IP development. Use scripting skills to meet efficiency and quality goals across all timing workflows. Derive best design guidelines for optimal signaling performance that result in minimal skews and insertion delays for various types of data interfaces and clock propagation. Prepare, analyze and report on data integrity and consistency within the macro timing model using spice correlation and data analytics. PREFERRED EXPERIENCE: 6+yrs experience in high-speed 10+Gbps serial and/or parallel analog PHY/IO designs. Experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals. Timing closure and Timing char using PrimeTime and NanoTime STA tools is a must. Proficiency in using spice based extraction and simulation tools. Very good understanding of SOC and Custom flows including physical design and IR drop. Strong communication skills with ability to comprehend and present technical ideas & reports across different teams and geographies. Strong analytical and problem-solving skills including the ability to root cause and debug in a fast-paced environment. Possess sound fundamentals and knowledge of analog mixed signal circuits timing collaterals and constraints. ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD SOCs THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge. Experience in Power Management and Power aware UPF based verification Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and System Verilog language Good working knowledge of System C and TLM with some related experience. Scripting language experience: Perl, Ruby, Make file, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electronics/Electrical Engineering

THE ROLE: The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors in a fast-paced environment with cutting-edgetechnology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs-CPU/GPU/DPU/memory controller, etc. Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

You are a highly skilled and knowledgeable professional with a passion for semiconductor physics and technology. With a PhD or MS degree in Electrical Engineering, Physics, or Materials Sciences, you bring profound expertise in semiconductor devices and process technologies. You have a deep understanding of semiconductor manufacturing processes and process modeling. You demonstrate the ability to analyze and to interpret experimental test/characterization data. Your excellent presentation and communication skills enable you to interact effectively across teams and at various levels within the organizations. You thrive in collaborative environments, always ready to help others succeed. You will be conducting TCAD calibration projects for advanced logic and memory technologies. Providing consulting services to customers and enhancing the value of TCAD for leading-edge technologies. Collaborating with R&D, sales, marketing, and customers to drive product development and acceptance. Managing customer projects, including definition, execution, and follow-up. Improving the overall quality and functionality of our TCAD tools through modeling and calibration. Driving the successful adoption of our TCAD products in various customer projects. Contributing to product development through valuable feedback and collaborative efforts with R&D teams. Elevating Synopsys" market position as a leader in semiconductor technology and simulation tools. Fostering strong relationships with customers, leading to increased trust and long-term partnerships. You should have a PhD degree in Electrical Engineering, Physics, Materials Sciences, or a related field and 5+ years of industry or research experience. Advanced knowledge and experience in semiconductor process technology and device design based on Silicon. Sound understanding of the process models describing implantation, diffusion, and activation of dopants in Silicon. Hands-on experience with TCAD simulation or emulation tools. Strong understanding of semiconductor devices physics. Python scripting proficiency is a plus. You are a collaborative team player with a "help others succeed" mentality. Detail-oriented with strong problem-solving abilities. Adaptable and able to work effectively in a fast-paced, dynamic environment. Proactive and self-motivated, with a passion for continuous learning and improvement. Able to interact at both engineering and management levels within customer organizations. The Product Application Engineering team is part of TCAD R&D providing market-leading solutions and services for TCAD and EDA. Our team drives the successful adoption of our best-in-class technologies and platforms at our broad and growing set of customers and partners across diverse market segments.,

You are a highly skilled and motivated Analog Design Engineer who thrives at the intersection of innovation and precision. Your background in analog design fundamentals and deep knowledge of device physics allow you to tackle complex circuit design challenges with confidence. You possess a track record of successful high-speed IO designs and have hands-on experience working with advanced technologies such as CMOS, FinFET, and GAA. Your expertise extends to ESD and reliability concepts, and you are we'll-versed in JEDEC requirements for memory interfaces enabling you to design robust, standards-compliant solutions. Collaboration is central to your approach. You excel in diverse, global teams, sharing your insights while listening and learning from others. Analytical thinking and creative problem-solving are your hallmarks, and you approach each task with a meticulous attention to detail. You are adaptable, continuously seeking to stay ahead of industry trends and technological advancements. Your communication skills allow you to clearly articulate complex technical concepts to both technical and non-technical stakeholders, making you an invaluable bridge within cross-functional teams. Above all, you are driven by a passion for innovation, eager to contribute to projects that push the boundaries of what s possible in semiconductor technology. What you'll Be Doing: Developing next-generation high-speed memory interface PHY IPs, including DDR, HBM, and UCIe standards. Executing projects in advanced semiconductor technologies, leveraging strong analytical and problem-solving skills. Designing high-speed IOs for memory interface PHY IP in CMOS, FinFET, and GAA process nodes. Collaborating with cross-functional and global teams to achieve ambitious project goals and timelines. Ensuring exceptional product quality and efficiency in all analog design tasks from concept to implementation. Staying informed and responsive to the latest industry standards, best practices, and technological advancements. Participating in design reviews, mentoring junior engineers, and contributing to a culture of technical excellence. The Impact You Will Have: Drive the development and delivery of innovative, industry-leading high-speed memory interface PHY IPs. Enable integration of advanced capabilities into complex SoCs, helping customers achieve unique performance goals. Enhance performance, power efficiency, and area optimization in mission-critical applications. Accelerate time-to-market for differentiated products by reducing design risk and streamlining development cycles. Foster effective collaboration with global teams, ensuring high-quality and reliable products. Set new industry benchmarks through cutting-edge analog design technologies and methodologies. What you'll Need: BTech/MTech degree in Electrical Engineering, Electronics, or a related field. At least 3 years of experience in analog design fundamentals and device physics. Proven proficiency in high-speed IO designs using advanced semiconductor technologies. Hands-on experience with ESD protection and reliability concepts in circuit design. Strong knowledge of JEDEC requirements and memory interface standards (DDR/HBM/UCIe). Familiarity with signal integrity and/or power integrity concepts is a plus. Who You Are: An analytical thinker with exceptional problem-solving skills and technical curiosity. A collaborative team player who communicates effectively and values diverse perspectives. Detail-oriented and capable of executing tasks with high precision and efficiency. Adaptable and eager to learn and master new technologies and industry standards. Passionate about driving innovation and making an impact through technology Health & we'llness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries

"> Search Jobs Find Jobs For Where Search Jobs Analog Layout Engineer - Senior Hyderabad, Telangana, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12304 Remote Eligible No Date Posted 21/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a deep understanding of Analog and Mixed Signal Circuit Layout. With a minimum of 3 years of experience, you bring a strong background in transistor-level analog and mixed-signal layout design. You possess extensive knowledge in CMOS and FINFET technologies, and your expertise in semiconductor device physics sets you apart. Your problem-solving skills are top-notch, and you are detail-oriented, self-directed, and passionate about learning new techniques. You are adept at communicating effectively with cross-functional teams to ensure successful project execution. You thrive in a dynamic environment and are excited about the opportunity to contribute to cutting-edge technology that drives the future. What You ll Be Doing: Design and development of transistor-level analog and mixed-signal layout. Device level floorplan, placement, routing, and physical verification. Troubleshoot physical verification issues to achieve clean and desired results. Create and review layout documents to ensure they meet quality standards and are delivered on time. Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment. Collaborate with cross-functional teams to ensure successful project execution. The Impact You Will Have: You will drive the design and development of high-quality analog and mixed-signal layouts. Your expertise will ensure the successful implementation of CMOS and FINFET technologies. Through effective troubleshooting, you will contribute to achieving clean physical verification results. Your attention to detail will ensure that layout documents meet quality standards and deadlines. By managing project schedules and milestones, you will help deliver projects on time. Your collaboration with cross-functional teams will enhance project success and innovation. What You ll Need: Bachelors or Masters degree in Electrical Engineering or a related field. Minimum 3 years of experience in Analog and Mixed Signal Circuit Layout. Proficiency in Analog Layout Flow from device placement to GDS release. Strong knowledge of CMOS and FINFET technologies and semiconductor device physics. Experience with EDA tools for custom mixed-signal layout flows. Understanding of CMOS fabrication technology and deep sub-micron effects on layout. Knowledge of electro-migration, reliability concepts, and ESD/LUP concepts as applied to layout. Passion for learning and exploring new techniques. Who You Are: Detail-oriented and self-directed with excellent problem-solving skills. Strong communication skills for effective collaboration with cross-functional teams. Ability to manage multiple projects and meet deadlines effectively. Innovative thinker with a passion for technological advancement. Team player who thrives in a dynamic and fast-paced environment. The Team You ll Be A Part Of: You will be part of a highly skilled and dedicated team focused on pushing the boundaries of analog and mixed-signal design. Our team collaborates closely with cross-functional departments to drive innovation and deliver high-performance solutions. We value creativity, teamwork, and a commitment to excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Hyderabad View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Participate in DDR/HBM Memory Interface I/O circuit and layout design, including GPIO and special IO s. Collaborate closely with the DDR/HBM PHY team, package engineers, and system engineers to ensure all design specifications are met. Support the execution of assigned circuit design tasks to achieve optimal product quality and efficiency. Engage in technical discussions and share creative solutions with cross-functional internal development teams. What You ll Need: Currently pursuing a bachelor s or master s degree in electronic engineering, Electrical Engineering, Computer Engineering, or a related field (preferably in the penultimate or final year of study). Knowledge of CMOS processes and deep submicron process technology challenges. Experience with CMOS circuit design and layout methodology & flow; a basic understanding of analog/mixed signal circuitry, with familiarity in basic ESD concepts considered an advantage. Familiarity with the ASIC design flow. Understanding of JEDEC requirements for DDR interfaces & standards, DDR timing, ODT, and SDRAM functionality is a plus. Strong written and verbal communication skills for effective collaboration within development teams.

Tessolve Semiconductor Pvt Ltd is looking for Post Silicon Validation Engineer to join our dynamic team and embark on a rewarding career journey Collaborate with cross-functional teams to achieve strategic outcomes Apply subject expertise to support operations, planning, and decision-making Utilize tools, analytics, or platforms relevant to the job domain Ensure compliance with policies while improving efficiency and outcomes

You are a passionate engineer eager to make a tangible impact in the world of analog and mixed-signal design. With a strong foundation in electronics or electrical engineering, you thrive in environments that challenge your technical and creative abilities. You are meticulous in your approach, ensuring the highest quality in every design you touch. Your curiosity drives you to stay at the forefront of CMOS technologies and deep submicron process innovations. You possess a collaborative spirit, enjoying teamwork with cross-functional groups to deliver best-in-class solutions. Communication is one of your strengths, enabling you to articulate complex technical concepts clearly and effectively. You are adaptable, excited by emerging technologies like DDR and HBM memory interfaces, and always seeking opportunities to grow your expertise. Above all, you are driven by a desire to contribute to groundbreaking products that set industry standards and improve the way people live and connect. What You ll Be Doing: Design and layout of DDR/HBM Memory Interface I/O circuits, including GPIO and special IOs, ensuring high performance and reliability. Collaborate closely with DDR/HBM PHY, package, and system engineering teams to align on design specifications and project goals. Develop and optimize analog and mixed-signal circuits in deep submicron CMOS processes. Contribute to the definition and implementation of circuit design flows and methodologies for advanced memory interfaces. Analyze and verify circuit performance against JEDEC and industry standards for DDR interfaces. Document your design work and effectively communicate progress and technical challenges with internal teams. Participate in design reviews, provide constructive feedback, and continuously improve design quality and efficiency. The Impact You Will Have: Drive innovation in the design of high-speed memory interfaces, directly influencing the performance of next-generation electronic devices. Enhance Synopsys reputation as a leader in analog and mixed-signal IP for advanced semiconductor applications. Help deliver robust, high-quality silicon solutions that power cutting-edge technologies worldwide. Facilitate seamless integration of memory interfaces into complex SoC designs, improving time-to-market for customers. Contribute to customer success by ensuring compliance with industry standards and exceeding reliability expectations. Support the continuous improvement of design methodologies and best practices within the team and organization. What You ll Need: BTech or MTech in Electronics or Electrical Engineering. 2 4 years of experience in analog/mixed-signal CMOS circuit design, preferably with exposure to deep submicron process technologies. Strong understanding of CMOS processes, circuit design, and layout methodologies. Familiarity with ASIC design flow and ESD concepts; hands-on experience is a plus. Knowledge of JEDEC requirements for DDR interfaces, DDR timing, ODT, and SDRAM functionality is highly desirable. Proficiency in executing circuit design tasks efficiently while maintaining high product quality. Effective written and verbal communication skills for collaboration with internal teams. Who You Are: Detail-oriented and quality-driven, consistently striving for technical excellence. Collaborative team player eager to contribute and learn in a dynamic, cross-functional environment. Adaptable and resourceful, able to manage multiple priorities and shifting project requirements. Proactive problem-solver with a growth mindset, always seeking opportunities for innovation and improvement. Clear communicator, able to convey complex technical ideas to both peers and non-technical stakeholders. The Team You ll Be A Part Of: You ll join a diverse and talented group of engineers focused on developing industry-leading analog and mixed-signal IP for memory interfaces. Our team collaborates across disciplines to tackle complex technical challenges and deliver innovative solutions. We value open communication, knowledge sharing, and mutual support as we push the boundaries of what s possible in semiconductor technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!