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ASIC Design Verification Engineer - ( SystemVerilog, UVM test

ASIC Design Verification Engineer - ( SystemVerilog, UVM test

Cisco

6 - 11 years

9 - 14 Lacs

bengaluru

Posted:5 days ago| Platform:

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Skills Required

asic asic design debugging troubleshooting perl soc verification python c++ simulation verdi design verification networking uvm verilog emulators data center formal verification silicon axi shell scripting tcl system verilog chip design

Work Mode

Work from Office

Job Type

Full Time

Job Description

ASIC Design Verification Engineer - ( SystemVerilog, UVM test bench, C/C++ , Perl/Python scripting, (VCS, DVE, Verdi), TCL/Shell scripting) | 10+ years

Meet the Team

Join our dynamic front-end design team at Cisco Silicon One, where innovation meets

innovative technology! As part of the heart of silicon development at Cisco, you'll

engage in every facet of chip design, from architecture to validation, using the latest

silicon technologies to create groundbreaking devices.

Cisco Silicon One is the only unified silicon architecture that empowers customers to deploy top-tier silicon across diverse applications, from top-of-rack switches to expansive data centres. Be a part of shaping Cisco's progressive solutions by designing and testing advanced ASICs that integrate networking, compute, and storage into a single system. With tightly integrated hardware and software solutions, you'll gain exposure to all aspects of our systems, using the latest technology.

We're seeking a dedicated ASIC engineer with a proven track record in high-performance products, ready to make a significant impact in the industry. Join us and push the boundaries of what's possible!

Your Impact

Develop test plans, cover points, and qualification tests
Perform end-to-end verification of design blocks and top-level
Build and maintain block, cluster, and top-level DV environment infrastructure
Construct testbenches components like scoreboard, agents, sequencers, and
monitors
Write tests, debug regressions, and drive to module verification closure
Collaborate with designers and verification engineers for cross-block verification
Upgrade configuration/reset sequences (APIs)
Develop environment and tests for emulation
Ensure complete verification coverage through code, functional coverage, and gate level simulations
Support post-silicon bring-up and optimize integration and performance

Minimum Qualifications

Bachelors Degree in EE, CE, or other related fields with 6+ years or Masters Degree
with 4+ years of ASIC design or verification experience
Experience in developing verification environment for complex blocks from design specifications document
Proficient in verifying complex blocks and/or clusters for ASIC using UVM/System Verilog.
Scripting experience with Perl, Python, TCL, shell scripts.

Preferred Qualifications

Experience in Data center/ Hyper scaler /AI Networking technologies
Proven experience meeting and delivering project milestones and deadlines.
Ability to communicate technical concepts to audiences spanning executives to junior
engineers to customers.
Demonstrated ability in troubleshooting and debugging.

Experience with Emulation and Formal Verification tools is a plus.

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ASIC Design Verification Engineer - ( SystemVerilog, UVM test