636 Silicon Jobs - Page 7

Join a team of passionate engineers shaping the future of silicon innovation. Where cutting-edge technology meets unlimited possibilities. Why Choose LeadSOC? At LeadSOC, youre not just joining a company youre becoming part of a mission to revolutionize the semiconductor industry. Every day brings new challenges, breakthrough innovations, and the opportunity to work alongside the brightest minds in VLSI design. Innovation First Work on cutting-edge VLSI projects that push the boundaries of technology Global Team Collaborate with talented engineers across Bangalore, California, and Berlin Continuous Learning Access to latest technologies, training programs, and industry conferences Work-Life Balance Flexible work arrangements and comprehensive health benefits Life at LeadSOC Unmatched Work Perks At LeadSOC, we believe in rewarding excellence and fostering growth. Discover the exceptional benefits that make our workplace truly special. Travel Benefits Explore the world with our global project opportunities. Work across our offices in Bangalore, California, and Berlin with full travel support and accommodation. Expand your horizons while building cutting-edge semiconductor solutions. Recognition & Rewards Your exceptional work deserves exceptional recognition. Enjoy performance bonuses, annual awards, and public acknowledgment for outstanding contributions. We celebrate achievements with meaningful rewards and career advancement opportunities. Growth Opportunities Accelerate your career with personalized development plans, mentorship programs, and access to cutting-edge training in emerging technologies. From junior engineer to technical leader - we invest in your professional journey. Ready to Shape the Future? Join our team of innovators and be part of the next generation of semiconductor breakthroughs. Your journey with LeadSOC starts here. Multiple Open Positions Available Were actively hiring talented professionals across various departments. Join our growing team and contribute to cutting-edge projects that shape the future. Full-Stack Development Apply with us below! Dont see your specific role? Apply anyway! Were always looking for exceptional talent and may have upcoming opportunities that match your skills. Years of Experience GitHub Profile (Optional) LinkedIn Profile (Optional) Upload your resume (PDF or Word document, max 25MB)

Very good knowledge of DFT RTL insertion including MBIST and SRAM repair Job Description In your new role you will: Drive and manage as technical member of a self contained DFT team which is responsible of: The DFT implementation of latest Infineon microcontroller products Scan insertion , ATPG, LBIST and MBIST Verification of the DFT implementation and Test pattern delivery for production testing Support the Silicon bringup activities to guarantee highest stability of the test pattern Contribute to the overall microcontroller DFT methodology Coordination of DFT workpackage s and hands-on work, status reporting Interfacing with project management, layout team and test engineering Your Profile You are best equipped for this task if you have: At least 6+ years of experience in DFT of highly complex SoCs A university degree in Electrical Engineering, Microelectronics, Physics or a similar field. Profound knowledge about semiconductor products. Expert Knowledge of DFT methods for state-of-the-art MPU/MCU products. Working knowledge of test concept or DFT concept definition. Strong track record of scan insertion and ATPG Very good knowledge of DFT RTL insertion including MBIST and SRAM repair Experience of debugging test pattern issues Programming or scripting experience Very good soft skills and experience in leading Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Build Your Future With LeadSOC Join a team of passionate engineers shaping the future of silicon innovation. Where cutting-edge technology meets unlimited possibilities. Why Choose LeadSOC? At LeadSOC, youre not just joining a company youre becoming part of a mission to revolutionize the semiconductor industry. Every day brings new challenges, breakthrough innovations, and the opportunity to work alongside the brightest minds in VLSI design. Innovation First Work on cutting-edge VLSI projects that push the boundaries of technology Global Team Collaborate with talented engineers across Bangalore, California, and Berlin Continuous Learning Access to latest technologies, training programs, and industry conferences Work-Life Balance Flexible work arrangements and comprehensive health benefits Life at LeadSOC Unmatched Work Perks At LeadSOC, we believe in rewarding excellence and fostering growth. Discover the exceptional benefits that make our workplace truly special. Travel Benefits Explore the world with our global project opportunities. Work across our offices in Bangalore, California, and Berlin with full travel support and accommodation. Expand your horizons while building cutting-edge semiconductor solutions. Recognition & Rewards Your exceptional work deserves exceptional recognition. Enjoy performance bonuses, annual awards, and public acknowledgment for outstanding contributions. We celebrate achievements with meaningful rewards and career advancement opportunities. Growth Opportunities Accelerate your career with personalized development plans, mentorship programs, and access to cutting-edge training in emerging technologies. From junior engineer to technical leader - we invest in your professional journey. Ready to Shape the Future? Join our team of innovators and be part of the next generation of semiconductor breakthroughs. Your journey with LeadSOC starts here. Multiple Open Positions Available Were actively hiring talented professionals across various departments. Join our growing team and contribute to cutting-edge projects that shape the future. Silicon Engineering Full-Stack Development DevOps Machine Learning Marketing Apply with us below! Dont see your specific role? Apply anyway! Were always looking for exceptional talent and may have upcoming opportunities that match your skills. Apply Now Ready to take the next step in your career? Submit your application and join our team of innovators. Full Name * Email Address * Phone Number * Position Applied For * Years of Experience GitHub Profile (Optional)

Very good knowledge of DFT RTL insertion including MBIST and SRAM repair Job Description In your new role you will: The DFT implementation of latest Infineon microcontroller products Scan insertion, ATPG, LBIST and MBIST Verification of the DFT implementation and Test pattern delivery for production testing Support the Silicon bring up activities to guarantee highest stability of the test pattern Contribute to the overall microcontroller DFT methodology Coordination of DFT work packages and hands-on work, status reporting Interfacing with project management, layout team and test engineering Your Profile You are best equipped for this task if you have: At least 3+ years of experience in DFT of highly complex SoCs A university degree in Electrical Engineering, Microelectronics, Physics or a similar field. Profound knowledge about semiconductor products. Expert Knowledge of DFT method s for state-of-the-art MPU/MCU products. Working knowledge of test concept or DFT concept definition. Strong track record of scan insertion and ATPG Very good knowledge of DFT RTL insertion including MBIST and SRAM repair Experience of debugging test pattern issues Programming or scripting experience Very good soft skills and experience in leading Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Join a team of passionate engineers shaping the future of silicon innovation. Where cutting-edge technology meets unlimited possibilities. Why Choose LeadSOC? At LeadSOC, youre not just joining a company youre becoming part of a mission to revolutionize the semiconductor industry. Every day brings new challenges, breakthrough innovations, and the opportunity to work alongside the brightest minds in VLSI design. Innovation First Work on cutting-edge VLSI projects that push the boundaries of technology Global Team Collaborate with talented engineers across Bangalore, California, and Berlin Continuous Learning Access to latest technologies, training programs, and industry conferences Work-Life Balance Flexible work arrangements and comprehensive health benefits Life at LeadSOC Unmatched Work Perks At LeadSOC, we believe in rewarding excellence and fostering growth. Discover the exceptional benefits that make our workplace truly special. Travel Benefits Explore the world with our global project opportunities. Work across our offices in Bangalore, California, and Berlin with full travel support and accommodation. Expand your horizons while building cutting-edge semiconductor solutions. Recognition & Rewards Your exceptional work deserves exceptional recognition. Enjoy performance bonuses, annual awards, and public acknowledgment for outstanding contributions. We celebrate achievements with meaningful rewards and career advancement opportunities. Growth Opportunities Accelerate your career with personalized development plans, mentorship programs, and access to cutting-edge training in emerging technologies. From junior engineer to technical leader - we invest in your professional journey. Ready to Shape the Future? Join our team of innovators and be part of the next generation of semiconductor breakthroughs. Your journey with LeadSOC starts here. Multiple Open Positions Available Were actively hiring talented professionals across various departments. Join our growing team and contribute to cutting-edge projects that shape the future. Full-Stack Development Apply with us below! Dont see your specific role? Apply anyway! Were always looking for exceptional talent and may have upcoming opportunities that match your skills. Years of Experience GitHub Profile (Optional) LinkedIn Profile (Optional) Upload your resume (PDF or Word document, max 25MB)

Join a team of passionate engineers shaping the future of silicon innovation. Where cutting-edge technology meets unlimited possibilities. Why Choose LeadSOC? At LeadSOC, youre not just joining a company youre becoming part of a mission to revolutionize the semiconductor industry. Every day brings new challenges, breakthrough innovations, and the opportunity to work alongside the brightest minds in VLSI design. Innovation First Work on cutting-edge VLSI projects that push the boundaries of technology Global Team Collaborate with talented engineers across Bangalore, California, and Berlin Continuous Learning Access to latest technologies, training programs, and industry conferences Work-Life Balance Flexible work arrangements and comprehensive health benefits Life at LeadSOC Unmatched Work Perks At LeadSOC, we believe in rewarding excellence and fostering growth. Discover the exceptional benefits that make our workplace truly special. Travel Benefits Explore the world with our global project opportunities. Work across our offices in Bangalore, California, and Berlin with full travel support and accommodation. Expand your horizons while building cutting-edge semiconductor solutions. Recognition & Rewards Your exceptional work deserves exceptional recognition. Enjoy performance bonuses, annual awards, and public acknowledgment for outstanding contributions. We celebrate achievements with meaningful rewards and career advancement opportunities. Growth Opportunities Accelerate your career with personalized development plans, mentorship programs, and access to cutting-edge training in emerging technologies. From junior engineer to technical leader - we invest in your professional journey. Ready to Shape the Future? Join our team of innovators and be part of the next generation of semiconductor breakthroughs. Your journey with LeadSOC starts here. Multiple Open Positions Available Were actively hiring talented professionals across various departments. Join our growing team and contribute to cutting-edge projects that shape the future. Full-Stack Development Apply with us below! Dont see your specific role? Apply anyway! Were always looking for exceptional talent and may have upcoming opportunities that match your skills. Years of Experience GitHub Profile (Optional) LinkedIn Profile (Optional) Upload your resume (PDF or Word document, max 25MB)

Join a team of passionate engineers shaping the future of silicon innovation. Where cutting-edge technology meets unlimited possibilities. Why Choose LeadSOC? At LeadSOC, youre not just joining a company youre becoming part of a mission to revolutionize the semiconductor industry. Every day brings new challenges, breakthrough innovations, and the opportunity to work alongside the brightest minds in VLSI design. Innovation First Work on cutting-edge VLSI projects that push the boundaries of technology Global Team Collaborate with talented engineers across Bangalore, California, and Berlin Continuous Learning Access to latest technologies, training programs, and industry conferences Work-Life Balance Flexible work arrangements and comprehensive health benefits Life at LeadSOC Unmatched Work Perks At LeadSOC, we believe in rewarding excellence and fostering growth. Discover the exceptional benefits that make our workplace truly special. Travel Benefits Explore the world with our global project opportunities. Work across our offices in Bangalore, California, and Berlin with full travel support and accommodation. Expand your horizons while building cutting-edge semiconductor solutions. Recognition & Rewards Your exceptional work deserves exceptional recognition. Enjoy performance bonuses, annual awards, and public acknowledgment for outstanding contributions. We celebrate achievements with meaningful rewards and career advancement opportunities. Growth Opportunities Accelerate your career with personalized development plans, mentorship programs, and access to cutting-edge training in emerging technologies. From junior engineer to technical leader - we invest in your professional journey. Ready to Shape the Future? Join our team of innovators and be part of the next generation of semiconductor breakthroughs. Your journey with LeadSOC starts here. Multiple Open Positions Available Were actively hiring talented professionals across various departments. Join our growing team and contribute to cutting-edge projects that shape the future. Full-Stack Development Apply with us below! Dont see your specific role? Apply anyway! Were always looking for exceptional talent and may have upcoming opportunities that match your skills. Years of Experience GitHub Profile (Optional) LinkedIn Profile (Optional) Upload your resume (PDF or Word document, max 25MB)

Join a team of passionate engineers shaping the future of silicon innovation. Where cutting-edge technology meets unlimited possibilities. Why Choose LeadSOC? At LeadSOC, youre not just joining a company youre becoming part of a mission to revolutionize the semiconductor industry. Every day brings new challenges, breakthrough innovations, and the opportunity to work alongside the brightest minds in VLSI design. Innovation First Work on cutting-edge VLSI projects that push the boundaries of technology Global Team Collaborate with talented engineers across Bangalore, California, and Berlin Continuous Learning Access to latest technologies, training programs, and industry conferences Work-Life Balance Flexible work arrangements and comprehensive health benefits Life at LeadSOC Unmatched Work Perks At LeadSOC, we believe in rewarding excellence and fostering growth. Discover the exceptional benefits that make our workplace truly special. Travel Benefits Explore the world with our global project opportunities. Work across our offices in Bangalore, California, and Berlin with full travel support and accommodation. Expand your horizons while building cutting-edge semiconductor solutions. Recognition & Rewards Your exceptional work deserves exceptional recognition. Enjoy performance bonuses, annual awards, and public acknowledgment for outstanding contributions. We celebrate achievements with meaningful rewards and career advancement opportunities. Growth Opportunities Accelerate your career with personalized development plans, mentorship programs, and access to cutting-edge training in emerging technologies. From junior engineer to technical leader - we invest in your professional journey. Ready to Shape the Future? Join our team of innovators and be part of the next generation of semiconductor breakthroughs. Your journey with LeadSOC starts here. Multiple Open Positions Available Were actively hiring talented professionals across various departments. Join our growing team and contribute to cutting-edge projects that shape the future. Full-Stack Development Apply with us below! Dont see your specific role? Apply anyway! Were always looking for exceptional talent and may have upcoming opportunities that match your skills. Years of Experience GitHub Profile (Optional) LinkedIn Profile (Optional) Upload your resume (PDF or Word document, max 25MB)

: As part of the methodology team, you will be responsible for developing and leading sophisticated power estimation and optimization methodologies at the netlist (gate-level) stage across SoC and IP designs. You will drive correlation strategies, automation flows, and accuracy improvements to ensure power estimates are tightly aligned with final silicon behavior. This role requires deep technical expertise in power analysis tools, a strong understanding of low-power design techniques, and collaboration with multi-functional teams across the design and verification cycle. Responsibilities: Define and drive netlist-level power estimation methodologies using industry-leading tools (e.g., Synopsys PrimeTime PX, Cadence Voltus). Establish and maintain correlation frameworks between RTL and gate-level power, and between estimated and silicon power. Develop automated flows for toggling activity generation, vector-based and vectorless power estimation, and regression reporting. Analyze power consumption trends and identify hotspots; provide recommendations for low-power design optimization. Collaborate with RTL design, physical design, DFT, and architecture teams to ensure early and accurate power signoff. Lead methodology development for corner analysis, dynamic/static power separation, and voltage scaling assessments. Support signoff reviews, audits, and compliance to power specifications and constraints. Provide mentorship and technical leadership within the team and across global sites. Required Skills and Experience : Proven experience of 5+ years in power estimation, optimization, and methodology development at the gate-level/netlist stage. Hands-on expertise with tools such as Synopsys PrimeTime PX, Cadence Voltus, and related signoff flows. Strong understanding of digital design principles, low-power architecture techniques, clock gating, and multi-voltage domains. Proficient in scripting (Python, Perl, TCL) to develop scalable and automated power analysis flows. Demonstrated experience in analyzing switching activity data (SAIF/VCD/FSDB) and correlating to real application workloads. Confirmed ability to handle large SoC designs and deliver accurate power metrics under tight schedules. Excellent problem-solving skills, attention to detail, and ability to drive technical discussions and decisions. Nice To Have Skills and Experience : Experience with UPF/CPF power intent validation and integration. Exposure to thermal and IR-drop analysis in relation to power consumption. Familiarity with AI/ML-based power modeling or anomaly detection. Previous contributions to methodology deployment in domains such as mobile, automotive, or server-grade SoCs. Participation in EDA tool evaluations, benchmarking, and vendor teamwork. Publications or presentations in technical forums (e.g., SNUG, DVCon, DAC) related to power estimation or optimization. In Return: We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding! Partner and dedication towards or customers Collaborate and communication Originality and resourcefulness Team and personal development Impact and influence Deliver on your promises Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Hybrid Working at Arm #LI-BB1 Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm

Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master's Degreein Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System Verilog programming skills Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime) Experience with debugging and verification methodologies Preferred Qualifications: Understanding of Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Experience with formal verification tools Experience with emulation

Project description Join our team in developing cutting-edge security firmware for Embedded Systems on Chips (SoCs). You will be working on innovative projects that focus on the security subsystem of silicon, including policy implementation, root of trust, TPM/fTPM, and Widevine. This role demands a high level of expertise in trusted applications and handshakes, contributing to the robustness and security of our products. Responsibilities Develop and maintain security firmware for Embedded SoCs Implement and enhance silicon security subsystems, policies, and root-of-trust mechanisms Work with TPM/fTPM and Widevine to ensure secure communication and data protection Debug and review C code to maintain high-quality firmware standards Collaborate with the team using Git/Gerrit for version control and code review processes Contribute to boot loader and Linux kernel development as needed Skills Must have 5-12 years of experience with MANDATORY Very strong in C language programming and debugging Security Firmware called PSP FW JD, Key skillsets 1 positions Good knowledge about silicon security subsystem / policy, root of trust, TPM/fTPM, Widevine Good knowledge of trusted applications and handshake Good knowledge on security concepts like chain of trust , Crypto Algorithms. Nice to have Familiarity with boot loader and Linux kernel development Experience with JIRA for project management and issue tracking Knowledge of UEFI/BIOS development and functionality

Project description Join our team in developing cutting-edge security firmware for Embedded Systems on Chips (SoCs). You will be working on innovative projects that focus on the security subsystem of silicon, including policy implementation, root of trust, TPM/fTPM, and Widevine. This role demands a high level of expertise in trusted applications and handshakes, contributing to the robustness and security of our products. Responsibilities Develop and maintain security firmware for Embedded SoCs Implement and enhance silicon security subsystems, policies, and root-of-trust mechanisms Work with TPM/fTPM and Widevine to ensure secure communication and data protection Debug and review C code to maintain high-quality firmware standards Collaborate with the team using Git/Gerrit for version control and code review processes Contribute to boot loader and Linux kernel development as needed Skills Must have 5-12 years of experience with MANDATORY Very strong in C language programming and debugging Working knowledge of git/Gerrit Side-band/Out-of-band server management. Experience in OpenBMC based BMC FW development mandatory. Experience on redfish Nice to have Familiarity with boot loader and Linux kernel development Experience with JIRA for project management and issue tracking

Sodexo Food Solutions India Pvt. Ltd. is looking for FTM - Carpenter to join our dynamic team and embark on a rewarding career journey Measurement and Planning: Measure and plan the layout and design of structures or components to ensure precision and accuracy in construction Cutting and Shaping: Cut and shape wood, metal, or other materials using hand and power tools like saws, chisels, and routers Assembly: Assemble and join pieces of wood or materials using screws, nails, adhesives, and other fastening methods to create structures, such as furniture, cabinets, or buildings Installation: Install doors, windows, moldings, cabinets, and other fixtures in homes, offices, and construction projects Framing: Build structural frameworks and frames for buildings, including wall framing, roof trusses, and floor systems

Sodexo Food Solutions India Pvt. Ltd. is looking for Carpenter to join our dynamic team and embark on a rewarding career journey Measurement and Planning: Measure and plan the layout and design of structures or components to ensure precision and accuracy in construction Cutting and Shaping: Cut and shape wood, metal, or other materials using hand and power tools like saws, chisels, and routers Assembly: Assemble and join pieces of wood or materials using screws, nails, adhesives, and other fastening methods to create structures, such as furniture, cabinets, or buildings Installation: Install doors, windows, moldings, cabinets, and other fixtures in homes, offices, and construction projects Framing: Build structural frameworks and frames for buildings, including wall framing, roof trusses, and floor systems

Title: Principal Engineer - IO Layout Design About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Introduction: This position is for IO Layout Engineer who will work on multiple IO IPs. The successful candidate needs to have a solid background in CMOS design, End-to-end Analog/IO IP development experience, and needs to be a team player with a solution-oriented approach. Your Job : Take full ownership of End-to-End IP development and support for IO IPs - Define specifications, define topologies, design/verify, guide layout team, post silicon validation, customer support on IP bugs Mentor junior engineers in block level designs Create required testbenches and perform DC, AC, Transient, STB, EMIR simulations Create design documents and drive Design reviews Be a creative problem solver, and look for innovation in design Work with cross-geo, cross-vertical teams to understand requirements and communicate resolution Other Responsibilities: Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs Required Qualifications : BS + 10 years/ MS + 8 years/ PhD + 6 or more years of experience working on IO Design - GPIO, LVDS, SSTL, HSTL, MIPI Deep understanding of Standard CMOS, FinFet and SOI technologies Multiple successful tapeouts in IO IPs Experience with silicon debug is a big plus Expert knowledge of Cadence tools - Virtuoso schematic editor, ADE-XL, Spectre Supervise layout engineers in delivering high quality layouts Must have good technical verbal and written communication skills and ability to work with cross functional teams is necessary Be able to collaborate with program and technical design leads on multiple concurrent projects. Should have excellent problem-solving skills, written & oral communication, teaming & interpersonal skills Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs Language Fluency - Fluent in English Language - written & verbal Preferred Qualifications: Knowledge of scripting languages like Python/Perl Familiarity with standard engineering practices like Version Control systems, Configuration Management and Regression process GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https: / / gf.com / about-us / careers / opportunities-asia

MANAGER SOFTWARE DEVELOPMENT THE ROLE: This role will include development, debug, and optimization of software on AMD silicon/ platforms during pre-si, bring-up and post-si phases. Coach and mentor staff. Influence others as a technical leader. THE PERSON: The candidate must demonstrate flexibility, strong motivation and a proven record of meeting aggressive deadlines as well as the ability to work as part of a team. The individual must have proven abilities to solve critical software problems and will be working with innovative engineers and managers to engineer the cutting-edge AMD silicon debug software. KEY RESPONSIBILITIES: Collaborate with the design team and architects to understand and define the software requirements. Translate these requirements into executable task plans. Responsible for design and management of software development activities for the audio diagnostics team at AMD. Code quality, robustness, extendibility and performance are critical. Responsible for code reviews, creating unit tests, authoring detailed documentation, and working with local & global teams to deliver the software solution on schedule. MUST HAVE SKILLS: Proficient in C++ programming. Audio protocol experience: I2S, Azalia, Soundwire. Strong understanding of Linux OS and its internals, memory and kernel. I/O execution/development experience on platforms/boards/SoCs. Scripting knowledge to automate test executions using bash scripts. Expert using GDB debugger and oscilloscope for analyzing waveforms and debugging. Proactiveness & positive attitude. Effective communication skills to be able to frame a problem statement and explain the issues or resolutions for debug. An effective team player to make sure we work together with laser focus on issues, execution, and positive attitude to learn in the process. ACADEMIC CREDENTIALS: Bachelor s degree + >10 yrs of experience (or) Master s degree with >7 yrs of experience in Computer Science, Computer Engineering, Electronics Engineering, or equivalent. LOCATION: Bangalore, India #LI-NR1

SE NIOR SILICON DESIGN ENGINEER Role: The ideal candidate is a person with extenstive experience in applying formal verification methods to complex IPs for cpu, gpu and high speed protocols. Responsibilities: Complete ownership and execution of formal verification of cache controllers, computational IPs, floating point units, etc In this role, he/she would be responsible for formal verification of GPU Design by meeting the demands of the constantly evolving project schedule. The successful candidate will be a member of the GFX team. He/she will demonstrate passion towards design, design verification, be a teammate, a problem solver with independence, creativity, and interpersonal skills. Complete ownership and execution of formal verification of cache controllers, computational IPs, floating point units, etc. PREFERRED EXPERIENCE: Vast and deep experience of formal verification methods Domain knowledge in cpu, gpu, serial protocols Must be able to do compexity reduction, bug hunting or similar methods ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1

SE NIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the Adaptive and Embedded Computing Group, you will help bring to life cutting-edge designs. As a member of the front-end design team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be designed and integrated Own the design and implementation of blocks to meet functional, timing, area and power requirements Guide and review verification for these blocks Design and implement logic functions that enable efficient test and debug Implement automation to increase design team efficiency PREFERRED EXPERIENCE: Strong front-end RTL engineering background Strong communication skills, able to summarize complex problems for executives as well as drill down to details with architects and engineers Strong analytic and problem solving skills including the ability to analyze current behavior, identify potential areas for improvement, and design of experiments Experience with Arm architecture and APB, AXI, CHI protocols Experience with design reuse, including RTL, constraints, and waivers Experience with SoC level design integration Experience with automation using scripting techniques such as PERL, Python, or Tcl Experience with timing constraints and timing exceptions Experience running standard quality checks such as LINT and CDC Experience designing with multiple power domains including writing UPF Must be a self-starter and self-motivated ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PS1

PMTS - GFX Verification Technical Lead Role: We are currently seeking a highly skilled Principal Member of technical staff (PMTS) Verification engineer for GFX top level end-to-end verification. Responsibilities: In this role, he/she would be the technical lead responsible for driving content, quality and debug throughput of top-level debugs coming from simulation, emulation, and post-silicon debugs. Working with architects and design leads and driving quality test plans Developing verification infrastructure and needed improvements Developing content strategy for quality. Driving DV closure to meet schedule with quality Working with each domain (sub-system) lead and guide them to get better quality and debug throughput. Helping management with risk assessment on features, quality, and schedules Working with sub-system DV leads to identify potential areas of formal verification Requirements: BS +14 years or MS +12 years work experience preferred. Should have end to end GFX/Compute verification experience and system knowledge. Experience with advanced verification methodologies and languages like UVM, system Verilog. Familiarity with all Design areas and tools and confirmed understanding of design/technology interactions Good understanding of memory hierarchy, caches, address translations schemes. Good understanding of general dram technologies and address translation schemes Familiarity with GFX pipeline and GPU design is plus Familiarity with Computer organization/architecture. Strong analytical/problem solving skills and pronounced attention to details. Formal property-based verification knowledge is an added plus. Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required Academic credentials: B.E/B.Tech or M.E/M.Tech degree in ECE / Electrical Engineering / Computer Engineering #LI-NS1

Where Staff Applications Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 6051 Remote Eligible No Date Posted 20/03/2025 Job Description and Requirements Our Silicon Design & Verification business is all about building high-performance silicon chips faster. We re the world s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance eliminating months off their project schedules. Were looking for an Applications Engineer to join our team. Does this sound like a good role for you This is an exciting opportunity to be part of applications engineering team that supports the industry leading Static Timing Analysis tool, Primetime. The primary focus of the Application Engineer (AE) is to drive increased usage of the product in both pre-sale and post-sale capacity. Pre-sales tasks include competitive benchmarks and evaluation, articulating the superiority to our customer s design team and management. Post-sales tasks include customer training, tape-out support and advance collaboration initiatives for product enhancements. The job involves working closely with users/customers and multiple organizations like R&D, marketing, sales among others. Key Qualifications Synopsys STA tool, PrimeTime experience and knowledge are required Knowledge of timing corners/modes, process variations and signal integrity related issues are required Familiarity with synthesis, Physical design, extraction and ECO methodology is desired Strong TCL knowledge is preferred Excellent verbal and written communication skills are mandatory. Prior customer facing role is a plus BSEE or equivalent, required with 6-7 years of experience, or MSEE, or equivalent with 4-5 years of experience At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Minimum qualifications: Bachelor s degree or equivalent practical experience. 2 years of experience with software development in one or more programming languages, or 1 year of experience with an advanced degree. 2 years of experience building developer tools (e.g., compilers, automated releases, code design and testing, test automation frameworks). Preferred qualifications: Master's degree or PhD in Computer Science or related technical fields. 2 years of experience with data structures or algorithms. Experience developing accessible technologies. About the job Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google s needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Develop code for products or systems. Lead design reviews with peers and stakeholders to evaluate technology options. Conduct code reviews developed by peers to ensure adherence to best practices including style guidelines, accuracy, testability and efficiency. Update documentation and educational materials based on product changes and user feedback. Debug and resolve systems issues by analyzing root causes and operational impact.

Minimum qualifications: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 5 years of experience with physical design. Experience with Python or C++. Experience with machine learning. Preferred qualifications: 10 years of experience in synthesis and physical design. Experience in various machine learning algorithms from logistic regression to neural networks and reinforcement learning. Understanding of algorithms and data structures. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Machine Learning Engineer for the Google silicon organization, you will contribute to improving SoC Performance, Power, and Area (PPA) using machine learning techniques. You will apply your experience to solve technical issues and drive improvements in Power, Performance, Area, and Schedule. You will directly impact logic design and optimization, floorplanning, place and route, clock and power planning, timing analysis, Power Delivery Network (PDN) analysis, and more. You will collaborate across Alphabet, working with design, CAD, and machine learning teams. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Deploy Google s AI solutions into chip design, collaborating with internal teams, Google DeepMind, and other teams within Google to explore and apply solutions that improve chip design PPA or reduce cycle time.

Minimum qualifications: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 4 years of experience with physical design flow such as floor planning, place and route, or physical verification. Experience with low-power design techniques, such as power gating, clock gating, or voltage scaling. Preferred qualifications: Experience in using Machine Learning (ML) in physical design. Knowledge of machine learning algorithms from logistic regression to deep neural networks and reinforcement learning. Knowledge of data structures and algorithms. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will contribute to improving Power Performance Area (PPA) using machine learning techniques. You will use the experience of physical design and machine learning to solve technical problems and improve on Power, Performance, Area and Schedule. You will work on design and optimizations, floorplan, place and route, clock and power planning, timing analysis, and Power Delivery Network (PDN) analysis. You will collaborate across Alphabet working with design, CAD and machine learning teams. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Deploy Artificial Intelligence (AI) solutions into chip design, work with internal teams, Google DeepMind and other teams to explore solutions and apply to improve chip design PPA or cycle time.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 10 years of experience with software design and development for software layers found in ASIC such as boot, drivers, embedded firmware, libraries, and API for applications. 5 year of experience in people management and developing employees. 5 years of experience driving ASIC architecture decisions from a software point of view. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Knowledge of interaction types between hardware and software for different types of standard hardware blocks, CPU and accelerators. Experience with Android OS and similar, with a focus on power management, debug, quality of service or drivers. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Software Manager, you will understand software product requirements, use cases and applications, and how they relate to specific hardware blocks or sub-systems. You will represent the goal of the software team and their constraints, working at system architecture definition of hardware blocks with the hardware architects, and the implementation definition working with the Hardware Implementation team. You will define or influence their work with the goal of ensuring fulfillment of software requirements, striving for optimal software programming model and interfaces, discuss and come to an agreement on hardware/software trade-off solutions, ensure scalability to future software and applications, and backwards compatibility as much as possible. You will make decisions using a data driven approach adopting or developing a modeling platform that will help you side your requests. You will also be required to estimate the complexity of specific implementations with the intent of supporting educated estimation of staffing and schedule required by managers or planners. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Collaborate with company-wide stakeholders like product management, architecture, silicon architecture, silicon implementation, silicon software, and product software engineering team, to identify user experiences characteristics and how they can be mapped onto hardware in existence or in development. Understand interactions between hardware components and drive towards the definition of architecture and block s interactions design, providing options or trade-offs, identifying issues and driving them to resolution. Design architecture and software interfaces that enable a software programming model that can ultimately delight our application developers, and that can let them make use of hardware accelerators seamlessly and timely. Design and improve hardware from generation to generation based on the results of productization efforts, and to reduce technical debt.

Minimum qualifications: Bachelor s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. 15 years of experience in ASIC RTL design. Experience with RTL design using Verilog/System Verilog and microarchitecture. Experience with ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: Master s degree in Electrical Engineering or Computer Engineering. Experience driving multi-generational roadmap for IP development. Experience leading interconnect IP design team for low power SoCs. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Lead a team of people to deliver fabric interconnect design. Develop and refine RTL design to aim power, performance, area, and timing goals. Define details such as interface protocol, block diagram, data flow, pipelines, etc. Oversee RTL development, debug functional/performance simulations. Communicate and work with multi-disciplined and multi-site teams.