Be responsible for supply chain planning through all business cycles,with focus on revenue contribution, ensuring forecast accuracy, managing inventory, and accurate demand planning. Job Description Be responsible for supply chain planning through all business cycles,with focus on revenue contribution, ensuring forecast accuracy, managing inventory, and accurate demand planning. Support allocation planning (supply stabilization, product planning &execution) and generate supply/ recovery plans to close demand gaps in consideration of contract fulfilments Consolidate capacity requiremen t for dedicated front end and silicon foundries in a structured manner for the entire business line on a regular basis: planning process, alignment with peers and communication to central functions Support and execute ramp up and product change projects , coordinate customer escalations and involve higher management levels where necessary. Interface with production logistics and planning; businessmanagement, business line marketing, ramp-up managers, corporate supplychain and quality management. Central role to manage and update planning models and supply/demandrules of our planning systems and act as support to the team whenrequired. You are best equipped for this task if you have: A university degree in industrial management, supply chain management or equivalent. 3-5 years of working experience in the semiconductor industries. Working knowledge of supply chain and material management concepts preferable. Affinity to Data and Advanced excel skills as we'll as experience in SAP. Knowledge in data analytics tools (eg Tableau, Power BI) andplanning models (eg Blue Yonder/JDA tool) is a plus. Fluency in English due to working in multi-cultural team

As a member of the NBIO IP Physical aware group, you will help bring to life cutting-edge designs. As a member of the Physical aware person, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve best quality and PPA for complex IPs THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: STA, timing analysis. Interface timing analysis, generate ECO. Primetime expert. Synthesis of Complex IPs, constraint developement. Develop feedback to RTL team for physically driven microarchirtecture changes, Manage data for shared design across multiple projects. corrdintation with multiple SOC for complex IPs PREFERRED EXPERIENCE: Understanding of STA and synthesis design cycle. 5+ experience in physical design and syntheis domain ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Power Management Engineer in Pune, MH, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: Ampere Computing is looking for a qualified design engineer on power analysis, optimization, and validation, to contribute in designing our high-performance power-efficient microprocessor chipset. This person will be a part of the Silicon Engineering team and work across multiple groups to drive the power requirements, and power optimization from micro-architecture to final silicon. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Power analysis engineer is expected have strong CMOS design fundamentals and deep knowledge of power reduction techniques at various levels of abstraction. Expertise in analyzing the results given by various power estimation tools and create actionable items for power reduction. Experience in developing flows and post processing scripts to help in analysis and rollup. Setup power analysis environment for at the RTL-level, and gate-level for power analysis of all design blocks at the pre-silicon stage. Determine tests and benchmarks to run on all blocks for pre-silicon power analysis Develop tests in DV test environment to certain use cases interesting for power analysis and reduction Run and review power analysis reports at the RTL-level and gate-level on all design blocks. Identify areas of improvements at the architecture-level, RTL-level, and synthesis. Analyze power from activities from workloads run on emulation environment Determine power optimization budgets for all blocks, and setup runs to validate them as the design progresses. Understand the different CPU use cases, Memory and Pcie workloads. Work with industry standard power analysis tools like Spyglass/Power Artist/Joules/PrimePower etc. Maintain and improve existing power modeling and analysis flows. Experience with power analysis using gate-level and RTL-power analysis tools Good understanding of power analysis and optimization on CMOS designs Good understanding of clock-gating, power-gating, DVFS, etc. used for power optimization Good understanding of processor designs, processor work-loads. Solid programming and scripting skills using Perl/Python/Tcl Experience running power analysis on activity from emulation environment Owned CPU or SOC design blocks and familiar with design flows (synthesis, place & route, power, timing, EM/IR) Owned power analysis methodology and/or automation in previous role Hands-on working experience with Power analysis tools and flows (one or more of the following industry-standard tools: Primepower, PTPX, Power Artist, Joules, Voltus) Advanced knowledge of Python, TCL and shell scripting M.Tech in Electronics Engineering or Computer Engineering with 1+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

The role will be a key player in organization responsible for Characterizing and validating Analog and Digital IP based Silicon Solutions at Cadence. Candidate should possess strong leadership skills with ability to manage multiple priorities and guide team members on day-to-day lab tests and silicon characterization activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication skills, are must have attributes in this role. Coordination with R&D, Marketing teams in defining the scope and delivering the results in time are critical. Minimum Qualifications & Professional Experience: 10-15 years (with BTech) or 10 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing. 2-3 years of management experience leading/mentoring a small team of engineers Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/ Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers. Proficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience to interpret the standard s specification to develop Electrical and Protocol, Interoperability and Compliance test suites to validate the silicon. Ability to isolate the PHY and controller (MAC/PCS) features to test, develop calibration / compliance lab suites and characterize. Architect and design Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes needed to meet the performance requirements. Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus. Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures. Expertise in developing ESD/Latchup/ HTOL tests to meet industry standards reliability qualification & specification Expert level knowledge in Verilog RTL coding for FPGA, python,C/C++

We are seeking a Senior Manager to lead our Bengaluru IC Verification team. This role offers a unique opportunity to shape the future of AI Networking. If youre a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI networking. Responsibilities Manage and lead Bengaluru team of ASIC verification engineers, fostering an inclusive and collaborative work environment. Ensure effective communication and coordination across different geographical locations. Technical Leadership in ASIC Verification: Provide technical expertise in the verification of complex ASIC designs, ensuring compliance with industry standards and project specifications. Gate Timing Simulations: Manage comprehensive gate-level simulations, including timing and power analysis, to validate the ASIC design before tape-out. RTL Coverage Analysis: Oversee the delivery of detailed coverage metrics to assess the thoroughness of the test suite. Offer actionable feedback to test writers and design engineers, focusing on identifying gaps and suggesting enhancements to broaden coverage scope. Firmware Collaboration: Work closely with Firmware teams to conduct co-simulations, ensuring seamless integration and functionality between hardware and firmware components. Team Development: Mentor and develop team members, identifying training needs and opportunities for growth. Manage third-party team augmentation in varied geographical locations. Qualification s ME/BE in Electrical Engineering, Computer Engineering, or a related field. A minimum of 12 years in ASIC verification, particularly in networking ASIC design. Technical Skills: Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, UVM) with a strong understanding of ASIC design and verification flow. Experience with coverage, gate/timing/power simulations, and test-plan documentation is required. Protocol Experience: Prior experience with Ethernet, UCIe, and PCIe protocols and both serial and parallel VIP verification modes, with strong expertise in high-speed SerDes. Leadership and Management Skills: Proven track record in managing and leading global teams with excellent people management skills, including experience in cross-cultural team dynamics. Communication Skills: Exceptional communication abilities, capable of effectively coordinating and leading a global team, and articulating complex technical issues clearly.

{"company":" About Eridu AI Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is looking to hire highly motivated and talented professionals for its R&D center in Bengaluru to join our world-class team. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI s solution and value proposition have been widely validated with several hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World s leading micro-LED display company and developer of the first augmented reality contact lens) . Visit our website to learn more about our impressive list of investors, advisors and leadership team. ","role":" Position Overview We are seeking a Verification Engineer to join our Verification team. This role offers a unique opportunity to shape the future of AI Networking. If youre a highly motivated self-starter eager to solve real-world problems, we d love to hear from you. Responsibilities Specialized Verification Strategy: Develop verification infrastructure and test cases for ASICs in the area of network fabrics, leveraging your extensive experience in networking. Technical Expertise in ASIC Verification: Provide technical leadership in the verification of complex ASIC designs, ensuring compliance with industry standards and project specifications Gate & Timing simulations: collaborate with the team to execute comprehensive gate-level simulations, including timing and power analysis, to validate the ASIC design before tape-out. RTL Coverage Analysis: deliver detailed coverage metrics to assess the thoroughness of the test suite. Offer actionable feedback to design engineers, focusing on identifying gaps and suggesting enhancements to elevate test effectiveness and broaden coverage scope. Quality Assurance and Process Optimization: Uphold the highest standards of verification quality. Initiate and implement process improvements for increased efficiency and effectiveness. Qualifications ME/BE in Electrical Engineering, Computer Engineering, or related field. Experience: A MINIMUM of 8-15 years in ASIC verification in the area of data center networking. Technical Skills: Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, UVM) with a strong understanding of ASIC Design and Verification flow. Experience with coverage, gate/timing/power simulations & test-plan documentation is required. Prior experience with Ethernet and PCIe Protocols and Serial and Parallel VIP verification modes. Strong prior experience with High speed Serdes. Communication Skills: Exceptional communication abilities, capable of effectively coordinating, and articulating complex technical issues in a clear manner. Why Join Us? At Eridu AI, you ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. "},"

Talentica Software, started by industry veterans and ex- IITB grads, is a product engineering company that helps tech-native enterprises and startups turn their ideas into market-leading products. We deliver innovative, high-quality products at an accelerated pace by combining the product mindset of our human experts with the power of AI. Over the last 22 years, the company has worked with over 200+ startups, with most clients based in the US, ensuring many successful exits. In 2022, Great Place to Work recognized Talentica Software as Indias Great Mid-Size Workplace. What were looking for? We are seeking a skilled .NET C# Developer who thrives in a dynamic, innovation-driven environment and is passionate about building scalable, high-performance web APIs. If you are excited to solve complex problems and collaborate with talented peers, you ll fit right in. What you ll be doing ? Build robust web APIs using C# and related OOP languages Write efficient, multi-threaded code for both client UI and server-side frameworks Work with SQL programming, MS SQL Server or equivalent RDBMS, and cloud database technologies Apply strong OOP design principles and software design patterns to new and existing codebases Develop and consume RESTful web services and APIs Thoroughly test, debug, and optimize code to ensure quality and performance Collaborate effectively within agile teams, both local and remote Contribute positively to team problem-solving and code reviews To be successful in this role, you should have: Qualification: A Bachelors degree in Engineering or Technology (B.E/B.Tech) from any recognized college in India. Experience: 6 to 8 Years Skills Proficient in building robust and scalable web APIs using C# or related object-oriented programming languages. Experience writing code for multi-threaded environments; both client UI and server framework Experience with SQL programming, MS SQL Server or similar RDBMS, or Cloud database technologies Strong OOP design skills Solid algorithmic skills and experience applying design patterns to both new and existing code Working knowledge of using RESTful web services and APIs Willingness to thoroughly test and debug code that you, or others, may write Successfully work in a team environment and approach challenges with a problem solving, can-do, positive attitude Experience working in an agile development environment with local and remote teams Nice to have (But not mandatory) Experience in Web UI technology frameworks like React, or comparable Experience with cloud platforms (GCP, Azure or AWS) Knowledge of additional programming tools, languages and protocols

About the job Enovix (Nasdaq: ENVX) is an advanced silicon battery company based in Fremont, Calif. Enovix is on a mission to power the technologies of the future. Everything from IoT, mobile and computing devices, to the vehicle you drive, needs a better battery. Our disruptive architecture enables a battery with high energy density and capacity without compromising safety. We are scaling our silicon-anode, lithium-ion battery manufacturing capabilities to meet customer demand. Responsibilities: Lead process development to improve battery performance to meet final product performance and reliability requirements. Design and run well-designed experiments based on DOE methodologies. Perform battery physical characteristic analysis and extract critical insights. Effectively collaborate with colleagues around the world - in California, India, Korea and Malaysia. Perform FMEA and root cause analysis. Effectively communicate the results to various stakeholders. Qualifications: BS, MS, or PhD in Chemical Engineering, Materials Science Engineering, Physics, Chemistry, Mechanical Engineering or related field with 2+ years industry experience. Strong knowledge of battery chemistry and physics is desirable. Experience working with battery testers or related electronics is a plus. Experience with using leading-edge battery and/or semiconductor material characterization techniques to drive failure analysis, understand degradation mechanisms, or improve yield. Experience with statistical analysis methods to drive experiment design and conclusions. Demonstrated capability to effectively analyze process data and extract/summarize meaningful information. Familiarity with SPC, DOE, FMEA and 8D methodologies. Enovix is an equal opportunity employer

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: Team and Job Description Microchip s Data Center Solutions BU (DCS) is a leader in providing optimized semiconductor-based solutions with highly integrated software that enable the world s data center infrastructure. We are seeking a dynamic, highly technical Product Management leader to join our team. As a key member of our team, you will interact closely with customers, architects, technologists, partners and cross-functional teams to define and deliver competitive and complete silicon-based solutions. This is a unique opportunity to be in a high growth, high visibility, and high impact role driving a successful product strategy built on the most advanced silicon technologies in the world. Key Responsibilities and Expectations: This position will drive customer engagements, design wins, growth, product and business planning activities across all DCS Product Lines and Solutions with a focus on system management, performance telemetry, security, RAS Management, ease of integration and overall user experience. Responsibilities include: Define the roadmap to deliver on a differentiated and compelling vision that delivers unique and best-in-class user experience for all our products. Drive detailed collateral, tools, training, software and product features prioritized to optimally increase customer delight. Work closely with customers, applications teams and support engineering to define the proper metrices, measures, and show continues improvement of customer experience. Drive Collaboration with Microchip cross-functional teams and managing the products from concept, through the planning cycle and timely production ramp and delivery to customers. Lead across multiple product execution teams to deliver a compelling value proposition. Lead in-depth customer engagements, working closely with them on roadmap development, proof of concepts, reference designs and system level solutions. Collaborate and support go-to-market teams, sales, field support teams, marketing. Present at all levels of the organization including executives. Requirements/Qualifications: Preferred qualifications Bachelor s degree in engineering or compute science; MBA preferred 10+ years of experience in product management, product marketing, or other customer-facing product roles within the semiconductor industry. Deep understanding of Data Center infrastructure and architectures that enable Data Center Compute, Accelerated and AI. Strong background in Data Center management and security protocols like PLDM, SPDM, OpenBMC, OCP Standard, and technologies like PCIe (required), Ethernet, CXL, NVMe. Understanding of emerging Scale-up and Scale-out technologies. Strong strategic thinking with analytical skills. Experience in a similar role engaging with Hyperscale customers and large OEM s/ODM s and key ecosystem partners. Excellent communication and presentation skills, with ability to articulate complex concepts with clarity and simplicity backed up with data. Growth mindset, with focus and determination to drive impactful results. Willingness to travel as needed for customer meetings, industry events, and trade shows Travel Time: 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Looking for an experienced dynamics person who is passionate about building therapy, concept & products that customers love, Develop & implement product strategies, Involve in Product Demos to hospitals, developments and innovations, inhouse training

locationsIndia, Bangaloreposted onPosted Today job requisition idJR0275251 Job Details: About The Role : Intel is at the forefront of the wireless communication industry, offering cutting-edge products that set the standard for performance and innovation. We are seeking a highly skilled SerDes PHY System Engineer to join our team. In this pivotal role, you will be responsible for the design and development of physical layer components for high-speed SerDes systems, ensuring their performance and reliability. Key Responsibilities: SerDes PHY DesignLead the design and development of the physical layer for SerDes systems, including transmitter and receiver architectures, equalization techniques, and signal integrity. Simulation and ValidationConduct comprehensive simulations using MATLAB and Python, along with lab testing, to validate the performance and compliance of the SerDes PHY, optimizing it for high-speed data transmission. Calibration TechniquesDevelop and implement calibration methods to enhance the performance of the SerDes PHY, ensuring high-quality data transmission. CollaborationWork closely with cross-functional teams, including digital design, hardware, and software, to ensure seamless integration of the PHY layer into the overall SerDes system. DocumentationMaintain detailed and up-to-date documentation of design specifications, test plans, and results. Problem-SolvingAddress and resolve complex technical issues related to the SerDes PHY, ensuring optimal performance. Quality AssuranceImplement quality control measures and best practices to ensure the reliability and robustness of the SerDes PHY. Qualifications: Bachelor's degree in Electrical Engineering; a Master's degree in a relevant field is preferred. Minimum of 5 years of experience in wired or wireless communication systems. Proven experience and enthusiasm for lab work, collaboration, and solution development. Prior experience in DDR/PCI/GDDR7/UCI will be added advantage. Proficiency in scripting and programming languages such as C, C#, MATLAB, and Python. Experience in silicon development and SerDes technologies is advantageous. Strong problem-solving abilities and analytical skills. Self-motivated and capable of executing tasks in uncertain environments. Demonstrated leadership skills and ability to drive initiatives in a matrix organization. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

The right engineer will drive the success of power IP (Intellectual Property) and features in AMD (Advanced Micro Devices) products through leadership & coordination, resolution of technical dependencies, and achievement of schedule commits. This is a high-visibility and widely multi-functional role, spanning pre-silicon architecture to post-silicon implementation & product delivery. THE PERSON: Your curiosity will drive your learning and innovation to improve how we as a group, and an organization, can get better every day. Your peers will provide you a results-oriented and encouraging environment for your career growth, fueling your opportunity to be a part of Delighting Our Customers. KEY RESPONSIBILITIES: Looking for security engineer with strong system and software security fundamentals. Candidate should have : Strong knowledge in cryptography fundamentals, including asymmetric and symmetric cryptography: All modes of symmetric algorithm AES Asymmetric algorithm like RSA, ECC Knowledge for Digital signature and Digital certificate X.509 format. Understanding of system design and security component in it. Understanding of different phases of Secure Development lifecycle of a solution Experience in threat modeling techniques, preferably with hands-on experience using Microsofts threat modeling tool and STRIDE methodology Experience in Root of Trust-based security development and trusted OS development Strong analytical skills required Secure communication protocols like TLS, SSH C language (Essential), C++ and RUST (desired). Must be a self-starter, and able to independently drive tasks to completion PREFERRED EXPERIENCE: Product development or systems engineering background with hardware platforms and their software & firmware ecosystems Excellent verbal communication and written, presentation skills Excellent interpersonal, organizational, analytical, planning, and technical leadership skills Proven record of accomplishment in delivering large multi-functional product solutions Experience working in a fast-paced matrixed technical organization and multi-site environment Product or program management ACADEMIC CREDENTIALS: bachelors or Masters degree in Computer or Electrical Engineering or equivalent

Meta is looking for ASIC Engineer, Infra Silicon Enablement to join our dynamic team and embark on a rewarding career journey. you will be a key contributor to our engineering team, responsible for verifying the functionality and performance of ASIC designs. You will work on complex projects, ensuring that ASICs meet quality standards and specifications. Key Responsibilities : Verification Planning : Collaborate with design and architecture teams to create verification plans that outline the scope, goals, and strategies for ASIC verification. Testbench Development : Develop and maintain verification environments, including testbenches, models, and test sequences, using verification languages such as SystemVerilog and UVM. Test Case Design : Create and execute test cases to verify the functionality, performance, and compliance of ASIC designs with project specifications. Functional and Code Coverage : Ensure comprehensive functional coverage and code coverage metrics are met, identifying verification gaps and proposing solutions. Simulation and Emulation : Utilize simulation and emulation tools to run test scenarios, debug issues, and track the behavior of the ASIC design under different conditions. Debugging and Issue Resolution : Investigate and resolve issues identified during verification, working closely with design and software engineers to analyze and rectify problems. Performance Testing : Verify the performance of ASICs under various scenarios, such as speed, power, and reliability, and optimize performance parameters. Documentation : Maintain clear and organized documentation of verification plans, testbenches, test results, and issues identified. Verification Tools and Methodologies : Stay current with verification tools, methodologies, and industry best practices to enhance the verification process. Collaboration : Work collaboratively with cross-functional teams, including design, architecture, and software development, to ensure the success of ASIC projects.

- We work with a team of component validation, integration, protocol test engineers, firmware developers and system engineers to create firmware verification test cases and end to end physical layer performance- Design and develop validation frameworks for the 4G/5G firmware Also, design, develop, and execute test cases for the 4G/5G firmware and debug and analyze issues found during the testing- Create test automation of 4G/5G UEs, test simulators and test gNodeBs - Verify key protocol, signal processing and numerical algorithms with very tight time, latency and energy budgets - Work with Systems / Firmware teams to perform validation of new and existing features - We are looking for candidates who can assist in the development of pre-silicon emulation systems/virtual platforms and use them for pre-silicon firmware design and HW verification Also, evaluate and implement cutting edge tools for build, formal verification and test In-depth understanding of 5G and 4G 3GPP physical layer and protocol stack procedures and configurations Experience with firmware test case planning, design, and development for the 4G/5G functional and performance scenarios Strong understanding of automation tools and scripting languages, such as Python, C/C++, Java (a plus) Solid understanding of multiple 4G/5G signaling and physical layer test equipment (Keysight/Anritsu/R&S) along with their automation interfaces Strong analysis and debugging capabilities to be able to define issues and work with firmware development and systems design teams to close these issues Deep understanding of software engineering principles, and core computer science fundamentals Fundamental facility with build and source code control tools Versatile to learn new architecture, frameworks and experience with network emulators, silicon prototyping, emulation systems, and virtual platforms a plus Education & Experience Bachelors degree in Electrical Engineering, Computer Science or related experience is required

- Trouble shooting issues in scientific approach with the use engineering tools/ techniques such as decoupled molding, scientific molding approach, Tolerance Analysis, SPC, DOE and Six Sigma techniques- Take the leading role in driving the improvement of productivity and quality of plastic part manufacturing, molding and tooling techniques- Serve as Apple s internal expert for molding process by using a thorough understanding various material properties and tool component fabrication techniques- To take part in new material development, new process development and innovation- Frequent travel within region is required Minimum 8 years in plastic tool design, mold making, molding industry and minimum 5 years in molding process position Bachelor Degree and above in Engineering, Plastics Technology, Polymer Science or equivalent Preferred Qualifications Experience in developing plastic processing parameters with hand-on experience in mold setup, process optimization and problem solving Experience in managing and develop precision parts, high pace and mass volume products with multiple vendors in parallel Good knowledge of geometric dimensioning, hot runner systems application and scientific molding technique Systematic, analytical & strong trouble shooting skills are a must to possess Able to analyze mold flow analysis, scientific study and provide improvement feedback Good knowledge in wide range of materials such as engineering plastic, liquid silicon rubber, thermal plastics, primer and epoxy Extensive experience in molding process setup, improvement and optimization Proficient in written, presentation and verbal communication

The success we are targeting will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problems in new ways. If that sounds like the kind of environment that you find intriguing, then lets talk.As a Software EPM, you will get a front row seat to deliver the best experience to our users. You will need experience with software development fundamentals, proven leadership capabilities, excellent communication skills, and a desire to work with an amazing engineering team to develop ground-breaking initiatives in the cellular software space. If you relish responsibility and are excited by the opportunity to build products that delight millions of customers then we want to hear from you - please apply! Description We are looking for someone to drive, own, and ship all aspects of large, multi-functional efforts and feature areas. Partner with engineering teams throughout feature development from architecture, design, implementation, and validation both in pre and Post Silicon phases. Proactively identify, prioritize, and drive resolution to program issues. Present and communicate new feature initiatives, top issues, risks, critical achievements to executive leadership. Help the team with ongoing improvements to the program management processes. Collaborate with cross functional SW and HW Engineering and Quality teams. At least 3+ years of program management experience in wireless software, system and platforms development. Good Understanding of cellular communications technologies (5G-NR/4G LTE/ UMTS/GSM/CDMA) is a significant plus. Driving multi-functional efforts across major technical fields: SW, HW, Silicon, and QA. Outstanding communication and presentation skills to engineers, managers, and execs. Preferred Qualifications Identifying risks, developing mitigation strategies, and facilitating resolutions. Sound technical foundation and a highly motivated self-starter. Knowledge of software engineering standard methodologies, program life cycle and related dependencies. Strong leadership skills and ability to inspire team members. BTech/MTech/MS EE/CS/CE or equivalent relevant experience

SILICON DESIGN ENGINEER 2 THE ROLE: As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence . THE PERSON: Software engineer with strong C++, C Python skills along with GPU architecture and ISA exposure for GEMM kernel development KEY RESPONSIBILITIES: GPU ISA understanding and kernel development for MI instinct customising architecture for optimal kernel Performance modelunderstanding for debug and optimisation Emu/Sim expertise for kernel customising and debug Familiarity in Driver based emu setup run and debug PREFERRED EXPERIENCE: 2+ experience in GPU performance ACADEMIC CREDENTIALS: Bachelor s or M aster s degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance .

About Tekion: Positively disrupting an industry that has not seen any innovation in over 50 years, Tekion has challenged the paradigm with the first and fastest cloud-native automotive platform that includes the revolutionary Automotive Retail Cloud (ARC) for retailers, Automotive Enterprise Cloud (AEC) for manufacturers and other large automotive enterprises and Automotive Partner Cloud (APC) for technology and industry partners. Tekion connects the entire spectrum of the automotive retail ecosystem through one seamless platform. The transformative platform uses cutting-edge technology, big data, machine learning, and AI to seamlessly bring together OEMs, retailers/dealers and consumers. With its highly configurable integration and greater customer engagement capabilities, Tekion is enabling the best automotive retail experiences ever. Tekion employs close to 3,000 people across North America, Asia and Europe. Key Responsibilities Requirements and Strategy: Drive the product roadmap and development requirements for partner integrations. Own feature requirement and user journeys for integrations in Parts module within the Tekion application. Own Go-to-market and roll-out for new partnerships: Develop and run end-to-end data integration framework, migration, and testing for the new partners. Plan the onboarding for new users on the Tekion platform Go-to Product Technical Expert: Troubleshoot production-escalation issues with your strong software and technical skills. And train internal and external customers on new product Integrations Lead cross-functional team: Work collaboratively with team members across all departments including Engineering, Product, Product Marketing, Analytics, Sales, Business Development, and Data Classification Skills & Qualifications We want that small percentage of the population that is passionate about what they do, likes to solve complex problems, is prideful of their work and wants to be part of an elite culture that is progressive, always evolving, and loves working with others to accomplish great things! 1 or more years of Product Management experience with an empathy for users, and understanding of their process and requirements Ability to write user stories, use cases and workflows, simplify the requirements, create mock-ups and a good understanding of system engineering concepts Drive prioritization and collaboration with engineering teams Excellent communication skills including technical writing skills Ability to envision product ideation through post-production release support Perks and Benefits Competitive compensation Generous stock options Medical Insurance coverage Work with some ofthe brightestmindsfrom Silicon Valley s most dominant and successful Companies

to assist in catering to the needs of management and accounts function. The ideal candidate will play a key role in daily finance tasks and cross-functional coordination. Key Responsibilities: Manage customer invoicing and accounts receivable processes Handle customer correspondence related to invoicing, payments, and receipts Accurately input financial data into internal systems Perform ad-hoc finance and administrative tasks as required Assist with intercompany transaction management and account reconciliations Requirements: Atleast 6-12 months of relevant experience Bachelor s degree in accounting, Finance, BBA, or BSc in a related field Strong English language skills with excellent written and verbal communication High attention to detail and ability to work independently in a fast-paced environment We have an amazing team of 700+ individuals working on highly innovative enterprise projects & products. Our customer base includes Fortune 100 retail and CPG companies, leading store chains, fast-growth fintech, and multiple Silicon Valley startups.

Confiz is hiring: Software Engineer - .Net We are seeking a skilled .NET Backend Engineer to develop and maintain APIs and integration solutions on Azure. The ideal candidate will have expertise in .NET backend engineering, design patterns, databases, and services within the Azure ecosystem. Responsibilities: Implement APIs and microservices in .NET. Deploy serverless solutions using Azure Functions, Logic Apps and API Management. Document integration processes and provide technical support for deployed solutions. Collaborate with cross-functional teams to align technical solutions with business objectives. Monitor and optimize performance using Azure Monitor and Application Insights. Requirements: Proficiency in C#, .NET. Expertise of RESTful APIs, Excellent problem-solving and communication skills. Familiarity with cloud integration patterns and practices will be a plus. Good to have Azure Functions, Azure Logic Apps and APIM. We have an amazing team of 700+ individuals working on highly innovative enterprise projects & products. Our customer base includes Fortune 100 retail and CPG companies, leading store chains, fast-growth fintech, and multiple Silicon Valley startups.

Are you looking for a unique opportunity to be a part of something greatWant to join a 20,000-member team that works on the technology that powers the world around usLooking for an atmosphere of trust, empowerment, respect, diversity, and communicationHow about an opportunity to own a piece of a multi-billion dollar (with a B!) global organizationWe offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: You will be working with our Design team from Hyderabad to develop STA tests. These tests are intended to catch timing violations at block level /SoC. In this role you will have an opportunity to understand in depth FPGA/SoC silicon architectures at block level as well as full chip level, to develop constraints and, debug the setup, perform static timing analysis and debug Timing violations. Interact with Physical design Teams and propose fixes for the timing violations. You will work closely with design engineers, custom engineers and layout engineers to ensure FPGA division deploys new products with the highest quality and shortest time to market. Skills will be developed to work on multiple projects supporting key functions within the organization. Good communication and presentation skills are required. Requirements/Qualifications: Perform Static Timing Analysis ASIC blocks and full chip with industry lead EDA tools like prime-time / Tempus, understand different interfaces, ASIC blocks and work on constraints and develop different STA modes at full chip level. Track post layout netlist releases spef extractions and integrate the new releases into full chip STA environment. Perform verification processes with modelling and simulation using industry standard simulators Maintain technical expertise and provide training to juniors Contribute to cross group communication to work towards standardization and group success Proactively solicit input from Standards, CAD, modelling and layout to ensure the design quality Drive innovation into the future generation with dynamic work environment Previous strong experience in STA and making timing constrains Experience in taking an industrial specification and implementing the respective IP Good understanding on timing/area/power/complexity trade-offs on complex interface design Familiar with IP level verification and strong RTL debugging capabilities Experience in frontend implementation tasks such as synthesis and logic equivalence Experience in large scale mix signal circuitry design including logic implementation/verification, timing analysis/optimization an advantage Excellent problem-solving and analytical skills A self-motivated, enthusiastic team player who enjoys working with others Good communication skills with the ability to convey complex technical concepts to other design peers in verbal and written form. Travel Time: 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Expertise in Symbol and Foot print creation using OrCAD capture & Allegro tool Expertise in Cadence Tool. Good Knowledge in library management, CIS Component Information System & CIP -Component information portal. How to leverage the capture CIS/CIP database management functionality for PCB schematic design. Worked on Orcad Centralized library Secondary Proficient to specify OEM component sources based on design engineering specs Proficient in Silicon Expert and similar tools to find second sources, validate component life cycles, etc. Proficient in creating footprints and symbols in Allegro/OrCAD Experience managing Allegro/OrCAD libraries Good in creating documentation for component release into TCE Footprint, Orcad, Allegro, Librarian, Component Engineer, Cadence

About Skylo Skylo is a global Non-Terrestrial Network service provider based in Mountain View, CA, offering a service that allows smartphone and IoT cellular devices to connect directly over existing satellites. Skylo s direct-to-device service is now live across four continents, with more than 50 million square kilometers of coverage, in partnership with multiple satellite operators, mobile network operators (MNOs), Tier-1 chipset makers, and OEMs. Devices connected over satellite are managed and served by Skylos commercial NTN vRAN, featuring a 3GPP standards-based cloud-native base station and core. Skylo provides anywhere, anytime connectivity solutions that seamlessly roam between terrestrial and satellite networks. Our focus is on enabling connected services for people outdoors and connected workflows across three main verticals: mass-market consumer devices, automotive, and industrial IoT. This role is located in Bengaluru, India where we are onsite 3 days a week in office. Summary Of How You Will Impact Skylo We are seeking an experienced and proactive Recruiter to join our growing team in India. Based in Bengaluru, India, you will manage end-to-end recruitment processes for a mix of technical (e.g., software engineering, IT, data science) and general (e.g., operations, sales, marketing) roles. This role is ideal for someone who thrives in a dynamic, international environment and is passionate about finding and engaging top talent. How You Will Contribute Manage full-cycle recruitment across various departments, with a focus on both technical and non-technical positions. Partner with hiring managers to understand role requirements, team culture, and candidate profiles. Proactively source candidates through various channels (LinkedIn, job boards, events, referrals, etc.). Coordinate the scheduling of all candidate interviews for assigned roles. Screen applications, schedule and conduct interviews, and coordinate technical assessments where applicable. Ensure a seamless candidate experience throughout the recruitment process. Maintain and update the applicant tracking system (ATS), Greenhouse, and recruitment dashboards. Ensure accurate reporting. Manage 3rd party recruiting agency relationships. POC for local 3rd party recruiting agencies. Collaborate with the People team on onboarding, employer branding and other HR initiatives. Stay informed of market trends, salary benchmarks, and legal hiring requirements in India. Support Diversity, Equity, and Inclusion (DEI) initiatives in hiring. What We Look For 4+ years of full-cycle recruitment experience, including technical roles. Strong understanding of the India labor market and recruitment practices. Experience recruiting in tech startups or multinational companies. Experience using Greenhouse ATS platform. Proven ability to source passive candidates and build pipelines. Excellent communication skills in the English (and local) language is a plus. Ability to work independently in a fast-paced, remote-friendly environment. Familiarity with DPDPA and other relevant hiring regulations in India. Nice to Have Knowledge of India employment law and talent trends. Technical literacy or prior experience working with engineering teams What We Offer With employees working across three continents, Skylo is proud to be an equal opportunity employer dedicated to building an inclusive and diverse workforce. Our worldwide and inclusive culture encourages a flexible approach to work, and we also offer an attractive range benefits such as: Competitive compensation packages including a stock option based equity program Comprehensive benefits including medical, dental, vision, retirement plan Monthly allowances for wellness and education reimbursement A generous time off policy, holidays, and the opportunity to temporarily work abroad Once in a lifetime opportunity to be a part of developing and running world s first commercial, live direct-to-device satellite network and service Access to world-class team and talent across tech domains: software, hardware, chipsets, telecom, satellite and network virtualization Open, transparent, inclusive culture that blends the Silicon Valley, Nordic and South Asia characteristics EEO Statement Skylo is an equal-opportunity employer and we celebrate diversity. We do not discriminate on the basis of race, religion, color, ancestry, national origin, caste, sex, sexual orientation, parent or caregiver status, political affiliation, gender, gender identity or expression, age, disability, medical condition, pregnancy, genetic makeup, marital status, or military service consistent with applicable federal, state, and local laws. We are also committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. Please let us know if you need assistance or accommodation due to a disability.

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional SMTS Verification Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer Responsibilities RESPONSIBILITIES Develop test plans, tests and verification infrastructure for complex IPs/sub-system/SOCs Create verification environment using UVM methodology Create reusable bus functional models, monitors, checkers and scoreboards Drive functional coverage driven verification closure Work with architects, designers and post-silicon teams Qualifications Bachelors / Masters degree in Electronics/Electrical Engineering 5 to 7 year of verification experience exposure in HVL based verification with expertise in SV & OVM Exposure in High Speed IO verification (UFS/PCIE/ XUSB) Good understanding of memory technology and memory sub-system Should have knowledge on all aspects of verification components & verification closure Should have flair for documentation, defining/improving methodology and achieving productivity improvement Ability to provide technical guidance & resolving technical conflicts desired Ability to communicate technical and project issues to business and technical senior management MUST have very good verbal and written communication skills About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow s systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ .

Job Category: Design Verification Job Type: Full Time Job Location: Bangalore Requirements: Bachelor s / Master s degree in Electrical Engineering or Computer Science with 6+ years of relevant experience Verilog / System Verilog based verification experience at Subsystem and Full chip level. Experience with digital system based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols. Experience with System Verilog Assertions with industry standard tools a plus Experience with SOC bot flow, clocking and platform bring up in Emlators or Silicon Desired Experience with Low Power Verification and power management flows. Experience with RTL, GLS level simulations Knowledge and experience working on PCIE/Ethernet and other HSIO desired Experience in UVM/OVM based methodology Development. Responsibilities: Be part of a team to verify complex system on a chip designs. Interact with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using UVM/Sytem Verilog Create complex C/SV tests using reusable test libs Team player and mentor who is self-driven, motivated and guides a team of junior engineers Responsible for quality and timeliness of the team output