locationsIndia, Bangalore time typeFull time posted onPosted 18 Days Ago job requisition idJR0271803 Job Details: About The Role : Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: B.Tech/M.Tech +6 Years of relevant industry experience. Having achieved multiple tape-outs reaching production with first pass silicon. Ability to drive and improve digital design methodology to achieve high quality first silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug. Have experience working in GPU/CPU domain. Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule. Strong verbal and written communication skills. Good understanding of verilog and system verilog, synthesizable RTL. Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

What if companies had truly informed, engaged, and influential employees? This is the challenge that Sociabble decided to take up in 2014, by launching an SAAS platform for Internal Communication , Employee Advocacy , and Employee Engagement . 10 years later, Sociabble is used in more than 180 countries, by companies such as Coca-Cola, Mars, Accor, EDF, Tata, Capgemini, Generali. International since day 1, the company has offices in Paris, Lyon, Boston and Mumbai. Sociabble was founded by two pioneers of the Internet, Jean-Louis B nard and Laurent Gauthier, entrepreneurs and investors for more than 25 years, who in building the company, were inspired by the best of U.S.-based SAAS platforms, without being constrained by the caricatures or culture of Silicon Valley start-ups. Sociabble is identified by U.S. analysts as one of the best solutions on the market today. Simplicity, kindness, respect, exemplarity, fairness, and trust are the values around which the company has developed. The teams consist of a mix of experienced and junior professionals, to facilitate day-to-day learning through mentoring. It is in the Sales team that a permanent position is vacant: The mission We are seeking a highly motivated, skilled and outbound-focused Account Executive to join our dynamic team in Mumbai. You will be part of the Sociabble International Sales Department and play a pivotal role in expanding our client portfolio across the APAC region , directly contributing to Sociabble s growth. You will navigate through long and complex sales cycles aimed at strategic project acquisitions, ensuring a thorough understanding and management from prospecting to deal closure . Responsibilities: Prospecting and identifying potential Enterprise and Mid-Market clients in APAC region by conducting deep analyses of the market and using sophisticated sales strategies to effectively engage with prospects at multiple organizational levels. Lead and qualify prospect meetings with C level decision makers , present Sociabble through demos. Manage a pipeline of strategic deals , providing timely and accurate forecasts to the sales management team, and close the deals . Collaborate closely with internal teams, including Legal (for contract stages), Product (for staying updated on new features), Security, ABM/Marketing (for market deals and lead generation ads), and Presales (for technical support and pricing assistance), ensuring smooth progress through complex sales cycles. Engage in team development activities like benchmarking, idea sharing, and workshops to enhance collective expertise and performance. Work closely with Customer Success Managers (CSMs) to develop and close upsell and cross-sell opportunities with strategic existing clients. The ideal Candidate You have a minimum of 5 years of experience in similar Account Executive roles targeting Enterprise accounts in Tech (ideally SaaS) across international markets (APAC & India) Outbound is second nature to you; you excel in using creativity to identify, reach, and convert your prospects into clients. You have already managed long and complex sales cycles involving multiple stakeholders, including strategic decision-makers . Outstanding interpersonal and communication skills , with the capability to interact effectively across global teams. Strongly client-oriented, you have an analytical mindset that enables you to quickly identify and act on future opportunities. You are also known for your active listening skills and ability to anticipate client needs. Native or bilingual proficiency in English , with a strong understanding of the cultural nuances in APAC markets . Extended use of CRM and other sales tools, ensuring that the data is clean and insightful. A drive to reach and surpass sales targets and to find ways to improve continuously. The perfect match? You will thrive at Sociabble if You have a strong taste for new technologies, the world of SaaS and digital transformation, and wish to practice in a constantly evolving environment. You are looking for a job with strong responsibility coupled with freedom of initiative and would like to get involved in an ambitious project. You wish to participate in an adventure and grow with an ambitious and benevolent team with globally recognized companies to ensure their satisfaction on their projects. You like international, transparent environments where everyone can learn and be heard. Our perks: Join an international Scale Up SaaS that s certified as a Great Place to Work and as a Best Workplace for 2023. Explore your new role with personalized and comprehensive onboarding , followed by workshops, Friday trainings, and year-round training sessions! Enjoy benefits designed for your well-being at work: healthcare support, paid leaves and sick days . Find your perfect balance with hybrid and flexible work (#LI-Hybrid), all while reuniting with your team in our beautiful office in Bombay each Thursdays. Connect with your colleagues through numerous events : afterworks, team buildings, town halls! Choose a committed company : partnership with Tree Nation, where each Sociabble employee plants trees to offset their CO2 emissions. Embody our values : kindness, ambition, humility. At Sociabble, we are Bootstrappers . Recruitment Process: Call (45 minutes) Lousia, Talent Acquisition Interview (1 hour) Brendan, Head of Global Sales Interview (45 minutes) Krusha, Director and Regional Head, Asia Simulation interview (1 hour) Krusha and Brendan Reference check Important information before applying: Permanent Position Based in Mumbai All your information will be kept confidential according to EEO guidelines.

NVIDIA is seeking a highly motivated, experienced Hardware Engineer to join our dynamic and fast-paced Silicon Solutions Group! Artificial intelligence is changing the world significantly starting with the technologies used in our day to day lives, cars we drive, autonomous machines in agriculture farms factories, smart cities and science technology development activities. GPUs are providing spectacular speed ups to scientific and medical research, enabling the advancement of humanity like never before. There has never been a more exciting time to work in Nvidia. As part of the Silicon Solutions Team, we architect and deliver groundbreaking solutions for productizing NVIDIAs chips into consumer, professional, server, mobile, and automotive markets. Silicon characterization, correlation to arch design expectations, finalize product specifications, develop productization techniques and infrastructure around it are part of our responsibilities. Dealing with challenges of the latest process node technologies is also part of the work. With competitive salaries, generous benefits package and an outstanding culture, we are widely considered to be one of the technology world s most desirable employers. We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. What youll be doing: Work with various Arch Design teams to come up with test plans of new features. Collaborate with other validation bring up teams to bring up/characterize silicon power and power saving features. Work with design estimation teams to correlate with pre-silicon expectations. Work with HW and SW teams to do the vital tuning and optimization of silicon power. Develop power consumption models to be used in binning, productization and customer application notes. Characterize and develop various power control mechanisms together with Arch/Design/SW teams. What we need to See: B. Tech or M. Tech in Electronics Engineering stream. At least 3+ years of related work experience. Strong understanding of aspects related to silicon power and performance, technology node impacts, Hardware and Software interactions at system level. Hands-on experience with silicon bring up, validation and productization Good knowledge in board and system design considerations, Power supply design. Very good problem solving and hardware debugging skills. Very good data analysis and logical reasoning skills. Strong familiarity with HW lab environment and understanding of various lab equipment. Experience in working with windows. Linux exposure is highly preferred. An understanding of PC architecture and various commonly used buses. Working experience with scripting languages like perl and/or python is a plus point. Must be a great teammate and ready to collaborate with global teams from diverse cultural backgrounds in a high energy environment. #LI-Hybrid

General Summary: Qualcomm is seeking an experienced and driven Silicon Characterization Engineer to join its hardware engineering group, contributing to the development and validation of industry-leading SoCs. This role focuses on post-silicon validation and characterization of high-performance silicon components such as PLLs , oscillators , and SoC subsystems , ensuring product reliability, performance, and quality. You will work in close collaboration with cross-functional teams, leveraging strong expertise in firmware development , semiconductor fundamentals , and lab instrumentation to execute detailed electrical characterization, develop automation flows, and perform root-cause analysis on silicon behavior. Key Responsibilities: Lead and execute PnP (Performance and Power) characterization of SoCs, including modules like PLLs and oscillators. Develop and validate firmware for multi-core microcontrollers or processors (ARM, RISC-V). Use lab tools (oscilloscopes, logic analyzers, spectrum analyzers, power meters, etc.) for detailed measurements and silicon debug. Automate test and measurement processes using Python scripting to streamline workflows and improve coverage. Analyze silicon performance and compare it against design specs to identify and investigate anomalies. Collaborate with silicon design, DFT, validation, and test teams to optimize test coverage and debug support. Contribute to characterization reports , silicon bring-up plans, and release documentation. Minimum Qualifications: Bachelor's degree in Electrical Engineering , Computer Engineering , or related field and 2+ years of experience in hardware engineering or silicon validation. OR Master's degree with 1+ year of relevant experience. OR PhD in a relevant field. Required Skills: 515 years of hands-on experience in silicon characterization or validation . Deep knowledge of CMOS device operation, solid-state physics , and submicron FET architectures . Strong background in firmware development for embedded platforms (C/C++ for ARM/RISC-V cores). Proficient in Python scripting and automation of lab equipment. Proven experience with automated characterization flows to maximize lab efficiency. Familiarity with semiconductor test and measurement equipment and methodologies. Strong problem-solving skills, attention to detail, and ability to drive root-cause investigations. Self-motivated with excellent initiative and organizational discipline. Preferred Qualifications: Experience in high-volume silicon validation environments . Knowledge of semiconductor manufacturing , test methodologies, and yield optimization. Understanding of thermal and power analysis in SoC systems. Exposure to lab automation frameworks and test data analytics. Key Traits: Strong analytical thinker with a proactive and hands-on approach to problem-solving. Highly collaborative and communicative, capable of working across interdisciplinary teams. Committed to continuous learning and staying updated with semiconductor trends.

We are currently seeking Verification Engineer with strong verification fundamentals to work in Switch Silicon group. Youll join a group of hardworking engineers to craft and implement the next generation innovative Switch Silicon chips. In this position, youll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest throughput and lowest latency! The Networking Chip Design team in India is a new team which is growing at a fast pace. What youll be doing: Verify Switch designs architecture and micro-architecture using advanced methodologies. Build reference models, verify and simulate chip blocks/entities according to specifications. Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW. You are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure, test plans and tests and verify the correctness of the design at SOC level. Use sophisticated verification methodologies like e-specman, SV-UVM etc. What we need to see: BS (or equivalent experience) / MS with 4+ years of experience in design verification. Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.). Perl/python scripting language experience desirable. Ways to stand out from the crowd: Prior experience of Ethernet or InfiniBand Switches, and/or smartNICs or DPUs, and/or high-speed interconnects. Strong debugging, problem-solving and analytical skills. Scripting knowledge (Python/Perl/shell). Good social skills and ability desire to work as an excellent teammate. Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com NVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #LI-Hybrid

Position: Senior QA Engineer Experience: 3+ years Location: Mumbai, Dadar East About Miko: Miko.ai is a Mumbai-based consumer robotics company founded in 2015 by IIT Bombay graduates Sneh Vaswani, Prashant Iyengar, and Chintan Raikar. The company specializes in developing AI-powered educational robots designed to engage, educate, and entertain children aged 4 to 12. Mikos flagship products, such as Miko 3 and Miko Mini, combine conversational AI with interactive learning experiences, aiming to foster cognitive, emotional, and social development in young learners. Miko has a global presence, with offices in Mumbai and Silicon Valley, and its products are available in over 140 countries. The company emphasizes child safety and privacy, ensuring that all interactions are secure and compliant with international standards. Additionally, Miko collaborates with educational content providers to offer a diverse range of learning materials tailored to individual learning paths. For more detailed information about Miko.ai, you can visit their official About the Role: We are looking for Quality Assurance Engineer with 2+ years of experience to join our Quality Assurance team and work with key stakeholders in the organization such as AI and robotics engineers, User Experience designers, product managers and technical program managers to define and implement quality engineering solutions for new features and products ensuring the highest quality of product delivery. Responsibilities: Development of test strategies and creation, execution and verification of test plans via manual testing methodologies for the area of ownership which includes voice and conversation experience, human robot interaction, child focused activities and games. Working alongside the engineering and product teams to maintain and enhance manual and automation test suites to fix bugs and implement new features and modules. Simulate real-world deployments of the products, reproduce customer issues, and perform root cause analysis. Defining and validating quality guidelines and processes for testing and releasing software to production Communicating with multiple teams and coordinating testing efforts and own software quality Requirements: 3+ years of experience working as a Quality Assurance Engineer Expertise in application quality and testing methodologies Experience with some or all testing methodologies: black box, white box, performance, security, integration and UAT. Experience with cross-platform mobile app development tools , technologies and mobile app operating systems - Android, iOS or other mobile platforms Perform functional and linguistic testing to validate grammar, spelling, punctuation, cultural nuances, and translations . Test UI/UX elements for truncation, alignment, and overall readability in the localized language . Evaluate voice AI, speech recognition, and text-to-speech (TTS) outputs for pronunciation accuracy and natural fluency . Collaborate with content, development, and speech engineering teams to resolve localization issues. Execute test cases and exploratory testing for localized features , ensuring cultural relevance in the target market. Identify, document, and report localization defects, providing detailed feedback for improvements . Hands-on experience in UI automation, API testing and should have knowledge in any one programming language preferably Java or Python. Good exposure for testing voice commands and Knowledge of conversational AI . Exposure to smart applications like Alexa or Google will be an added advantage Experience with wireless consumer electronics devices, smart devices, IoT devices is an added plus. Experience with child-focused products, applications and games is added plus

Striim, (pronounced stream with two i s for integration and intelligence), is a unified data integration and streaming platform that connects clouds, data, and applications with unprecedented speed and simplicity to deliver the right data at the right time. Striim is used by enterprise companies to monitor events across any environment, build applications that drive digital transformation, and leverage true real-time analytics to provide a superior experience to their customers. At our company, we believe and expect all of our employees to operate as one with unlimited potential and dignity. Description We are looking for a Software Engineer who is ready to make an impact in realtime data-streaming and large-scale data integration. As a Software Engineer, you will play a pivotal role in designing, implementing, and optimizing the infrastructure that powers our high-performance data streaming platform. This is an exciting opportunity to work with state-of-the-art technologies, collaborate with top-tier engineers, and contribute to the growth of a company that is transforming how businesses harness the power of real-time data. If youre ready to take on complex challenges and drive impactful change, we want to hear from you. Requirements: 2 to 4 years of experience in programming with any one of the object oriented language - Golang / Java / Python / C / C++ . Experience working on Microservices architecture latest distributed systems is a plus Proven professional experience with Cloud platform Knowledge in AWS/GCP/Azure is an advantage Experience with Agile programming methodologies. Ability to thrive in a fast-paced working environment and collaborate with other engineers. Location: Bengaluru Benefits: We offer Competitive salary and pre-IPO stock options Comprehensive health care plans for employees and family members. Gratuity Plan as per the India Gratuity Act Paid Time Off (Annual Leave, Sick Leave, Casual and generous public /bank holidays) Employee Wellness Programs: Access to free online Yoga classes, Gym membership reimbursements, Employee Wellness Assistance Program Sodexo Meal Program Internet reimbursement program Group Term Life Insurance (Go Digit Insurance) Paid Maternity and Paternity leave The chance to contribute to and shape an upbeat, fully engaged culture Our company culture fosters entrepreneurship and nurtures our team members to grow with the company. Come join a Silicon Valley startup focused on delivering a product that s loved by its customers and primed to be a core part of the cloud data stack. We are an equal opportunity employer, and we value diversity at our company.It is in our best interest to continue to foster an environment of diversity, equity, and inclusion to bring the most value to our workforce, customers, and partners. All applicants are considered for employment without attention to race, color, religion, sex, age, marital status, sexual orientation, gender identity, national origin, veteran status, or disability status. For more information on Striims Privacy Policy, click here .

We are looking for a highly skilled Java to join our dynamic development team with 2+ years of experience. This role requires a problem-solving mindset and the ability to work in an agile environment. Responsibilities : Implement APIs and microservices in Java. Deploy serverless solutions using Azure Functions, Logic Apps and API Management. Document integration processes and provide technical support for deployed solutions. Collaborate with cross-functional teams to align technical solutions with business objectives. Monitor and optimize performance using Azure Monitor and Application Insights. Requirements : 2+ years of experience in backend engineering. Proficiency in Java, Spring boot and Azure. Expertise in Azure Functions, Azure Logic Apps or APIM will be a huge plus. Expertise of RESTful APIs, JSON, and XML. Excellent problem-solving and communication skills. Familiarity with cloud integration patterns and practices will be a plus. Knowledge of CI/CD pipelines

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels. Available Job Responsibilities Design and build memory or circuit blocks at the gate or transistor level Simulate and analyze the circuit design using transistor level simulators Extract the layout and perform post-layout simulations and verification Floorplan physical implementation and layout integration of design components Integrate characterization flow to extract timing and power information Develop scripts to automate characterization flow, simulations, and verification Specify and verify various behavioral and physical memory models Document the design specifications, behavioral description, and timing diagrams Help specify silicon test plan and correlate silicon to simulation data Preferred Skills Good understanding of transistor level circuit behavior and device physics Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis Proficiency in running simulators, writing automation scripts, and are tools savvy Understanding of memory behavioral and physical models is a plus Expertise in memory circuit design is a plus Understanding of DFT schemes and chip level integration is a plus Good communication, interpersonal, and leadership skills Motivated, self-driven and good at multi-tasking Passion for solving complex problems and willingness to learn

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels. Available Job Responsibilities Design and build memory or circuit blocks at the gate or transistor level Simulate and analyze the circuit design using transistor level simulators Extract the layout and perform post-layout simulations and verification Floorplan physical implementation and layout integration of design components Integrate characterization flow to extract timing and power information Develop scripts to automate characterization flow, simulations, and verification Specify and verify various behavioral and physical memory models Document the design specifications, behavioral description, and timing diagrams Help specify silicon test plan and correlate silicon to simulation data Preferred Skills Good understanding of transistor level circuit behavior and device physics Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis Proficiency in running simulators, writing automation scripts, and are tools savvy Understanding of memory behavioral and physical models is a plus Expertise in memory circuit design is a plus Understanding of DFT schemes and chip level integration is a plus Good communication, interpersonal, and leadership skills Motivated, self-driven and good at multi-tasking Passion for solving complex problems and willingness to learn .

Job Description Need to work in collaboration with global design teams across sites. Will be responsible for driving innovation in Analog IP designs. Responsible for design of IPs like Switched capacitor circuits , Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools. Should provide technical leadership and mentor junior engineers. Responsible for developing processes and robust design methodology. Help build overall competency in Analog domain. Qualifications Bachelors/ Masters degree in Electrical/ Electronics Engineering with 8+ years of experience in Analog Circuit Design across different technologies. Should have experience in developing analog IPs l

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ years RTL Design/Hardware Engineering experience or related work experience. Strong Domain Knowledge on RTL design(Verilog/VHDL/System Verilog) , implementation, and integration, micro-architecture & designing cores and ASICs Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc Exposure in scripting (Pearl/Python/TCL) Strong debugging capabilities at simulation, emulation, and Silicon environments Collaborate closely with cross-functional teams to research, design and implement performance and power management strategy for product roadmap Knowledge on Designing low power/power management controller IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), on-chip sensor controller Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows Work closely with system/software/test team to enable the low power feature in SoC products Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years RTL Design/Hardware Engineering experience or related work experience. Strong Domain Knowledge on RTL design(Verilog/VHDL/System Verilog) , implementation, and integration, micro-architecture & designing cores and ASICs Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc Exposure in scripting (Pearl/Python/TCL) Strong debugging capabilities at simulation, emulation, and Silicon environments Collaborate closely with cross-functional teams to research, design and implement performance and power management strategy for product roadmap Knowledge on Designing low power/power management controller IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), on-chip sensor controller Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows Work closely with system/software/test team to enable the low power feature in SoC products Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Details: : Intel is a leader in the wireless communication industry, offering products that set the benchmark for performance and innovation. We are seeking a motivated Junior SerDes PHY Integration Engineer to join our team. In this role, you will focus on integrating physical layer components for high-speed SerDes systems, playing a crucial part in ensuring their performance and reliability.Key Responsibilities:SerDes PHY IntegrationsSupport the integration of the physical layer for SerDes systems, including transmitter and receiver architectures, equalization techniques, and signal integrity.Simulation and ValidationAssist in conducting simulations using MATLAB and Python, along with lab testing, to validate the performance and compliance of the SerDes PHY, optimizing it for high-speed data transmission.Calibration TechniquesHelp integrate calibration methods to enhance the performance of the SerDes PHY, ensuring high-quality data transmission.CollaborationWork collaboratively with cross-functional teams, including digital design, hardware, and software, to ensure seamless integration of the PHY layer into the overall SerDes system.DocumentationContribute to maintaining detailed and up-to-date documentation of design specifications, test plans, and results.Problem-SolvingAssist in addressing and resolving technical issues related to the SerDes PHY, ensuring optimal performance.Quality AssuranceSupport the implementation of quality control measures and best practices to ensure the reliability and robustness of the SerDes PHY.Develop SERDES TestsParticipate in the development of comprehensive tests to support integration efforts, including writing scripts for software and firmware in Intel's test environment. Qualifications: Bachelor's degree in Electrical Engineering; a Master's degree in a relevant field is a plus.Passion for lab work, collaboration, and solution development.Familiarity with scripting and programming languages such as C, C#, MATLAB, and Python.Experience in silicon development and SerDes technologies is beneficial.Strong problem-solving abilities and analytical skills.Self-motivated and capable of executing tasks in uncertain environments.Demonstrated ability to contribute effectively in a matrix organization. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : 1) Defines, develops, and performs functional validation in SoC power management for GPUs focusing on validation of IP integration, interaction between IPs, and system level features.2) Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met. 3) Reviews proposed design changes to assess impact on validation plans, tasks, and timelines. 4) Develops Power Management validation methodologies and Validation plans for SoC power management for GPUs, executes validation plans, and collaborates with engineers for feature verification, troubleshooting and failure analysis. 5) Tests interactions between various GPU features using validation infrastructure. 6) Develops post silicon validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing. 7) Performs silicon debug to identify root causes and resolves all functional and triage failures for SoC Power management in GPUs. 8) Develops content to create or increase specific IP interactions, engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (emulation, FPGA) to ensure silicon readiness Qualifications: Bachelors or masters degree in computer science, Electrical Engineering, or a related field with 5 to 10 years of experience. Proven experience in SoC validation specifically in Power management areas Test content development with focus on reset/boot/Active Power/Idle Power/ Thermal areas. Strong understanding of server architectures, hardware components, and operating systems (Windows, Linux) Proficiency in programming like C, C++, Python for test automation, debugging, and test content development. Experience with validation, debug tools involving ITP/JTAG, Test content development tools and frameworks (e.g., Jenkins, GDB, WinDbg). Excellent problem-solving skills and attention to detail. Familiarity with version control systems (e.g., Git) and issue tracking tools (e.g., JIRA). Knowledge of industry standards and best practices related to server reset, platform validation, debugging, and test content development. Good team player, Candidate should have excellent interpersonal skills / strong communication and collaboration skills w/ the ability to work effectively in team environment Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications,processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of verification principles and coverage. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 6 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg.I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages.

NVIDIA is seeking a passionate, creative, and highly motivated engineer to work on architectural power estimation for the world s leading GPUs and SOCs. In this position, the responsibility includes development of advanced power models to estimate chip and board power under product driven use cases. You are expected to understand the high-level chip architecture, application use-cases, low power design techniques, process technology aspects which impact dynamic and leakage power, develop the estimation infrastructure, estimate power consumption under various scenarios. You will be working with architecture, design, synthesis, timing, circuit, and post silicon teams to accomplish your tasks. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. Were united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Architecture, development and correlation of power estimation models/tools for NVIDIAs chips Help architect and develop power models for use-cases, Idle power and IO power. Chip in to design the tools based on these models and their testing methodology/infrastructures Correlate and Calibrate the power models using measured silicon data Analyze and help decide the chip configuration and process technology options to optimize power/performance for Nvidias upcoming chips Help study and contribute to Performance/Watt improvement ideas for Nvidias GPUs and SOCs What we need to see: B. Tech. /M. Tech and 1+ years of experience related to Power / Performance estimation and optimization techniques Strong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS) Strong background in power estimation techniques, flows and algorithms Good programming skills - Python preferred. Good skills with object-oriented programming and design. Ways to stand out from the crowd: Exposure to lab setup including power measurement equipment such as scope/DAQ with ability to analyze board level power issues is a plus Exposure to power analysis EDA tools such as PTPX/EPS Good communication skills desire to work as a great teammate With competitive salaries and a generous benefits package, Nvidia is widely considered to be one of the most desirable employers in the world. #LI-Hybrid

Technical Skills and Competencies Must Have: At least 4 years of hands-on experience in mobile automation script development. Good understanding of various methods for identifying UI elements in both Android and iOS platforms. Automation Framework: Appium with Java Test Runner: TestNG CI/CD Integration: Jenkins Good to Have: Automation experience with Selenium/Java Knowledge of Perfecto Candidate Profile and Competencies Responsibilities: Write robust scripts to ensure the reliability of underlying code functionality. Execute scripts on multiple environments and share reports. Understand existing code and make necessary changes. Work directly with project teams and infra teams. Share analysis and reports of recommendations based on execution results. Be proactive when working on assigned tasks. Learn and apply new performance testing techniques on projects. Work independently and make progress by being resourceful. Own the implementation of scripts and deliver within designated timelines. Provide timely status updates and raise flags as needed. Possess good communication skills to collaborate with internal and external teams.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Physical Design CAD engineer, you will build and support the world"™s best implementation tools and flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area. Roles and Responsibilities Develop, integrate and release new features in our high-performance place-and-route CAD flow Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain, support and debug implementation flows, and resolve project-specific issues Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA. Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science Ten+ years of hands-on experience in place-and-route of high-performance chips - either in a design or CAD role High level of proficiency in Tcl as well as Python Experience with automation Experience with a wide variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Solid understanding of digital design, timing analysis and physical verification Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Physical Design CAD engineer, you will build and support the world"™s best implementation tools and flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area. Roles and Responsibilities Develop, integrate and release new features in our high-performance place-and-route CAD flow Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain, support and debug implementation flows, and resolve project-specific issues Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA. Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science Ten+ years of hands-on experience in place-and-route of high-performance chips - either in a design or CAD role High level of proficiency in Tcl as well as Python Experience with automation Experience with a wide variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Solid understanding of digital design, timing analysis and physical verification Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows

{"company":" About Eridu AI Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is looking to hire highly motivated and talented professionals for its RD center in Bengaluru to join our world-class team. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI s solution and value proposition have been widely validated with several hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World s leading micro-LED display company and developer of the first augmented reality contact lens) . Visit our website to learn more about our impressive list of investors, advisors and leadership team. ","role":" Position Overview We are seeking an RTL Design Director to lead our Networking IC team in Bengaluru. If youre a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. Responsibilities Provide technical leadership and direction for the offshore RTL team. Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design implementation. Perform RTL coding, code reviews, and debugging. Document microarchitecture and RTL subsystems. Support the definition of development flows that improve efficiency and quality of execution. Work closely with Physical Design, Firmware, and Design Verification teams to ensure successful end-to-end RTL implementation. Leverage domain experience with Ethernet, PCIe, protocols to make informed design decisions. Qualifications ME/BE with at least 15+ years of experience. Proven record of successful tape-outs and productization, preferably in networking devices. Ability to translate architecture-level feature descriptions into implementable designs, including clear documentation for execution and verification. Thorough understanding of multiple clock/reset/power domain design challenges and safe/robust design practices. Experience in refactoring/restructuring designs to solve timing/area challenges, including algorithmic and structural design changes. Expertise in optimizing hardware versus firmware implementation for overall product performance/efficiency. Excellent knowledge of industry-standard tools and best-in-class practices for high-quality RTL development. Knowledge of networking protocols is essential. Experience with micro-architectural specification of ASIC s. Good understanding of the ASIC design flow, including DFT and physical implementation requirements. Why Join Us At Eridu AI, you ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles . "},"

Performance modelling and evaluation of ACAP workloads to eliminate bottlenecks as early as possible and guide the architecture of future generation devices. This is a challenging role in the FPGA Silicon Architecture Group in AECG business unit of AMD in Hyderabad. ABOUT THE TEAM: AECG group in AMD designs cutting edge FPGAs and Adaptable SOCs consisting of processor subsystems and associated peripherals, programmable fabric, memory controllers, I/O interfaces and interconnect. KEY RESPONSIBILITIES: Modelling and simulation of workload dataflow networks and clock accurate SOC components. Performance analysis and identification of bottlenecks Quick prototyping, long-term design decisions, and exploring novel architectures Enhancement of the existing tools and knowledgebase Collaborating with architects in the development of next generation devices Collaborating with customer facing teams to identify scope of optimization for future market scenarios Breaking down system level designs into simpler dataflow models and identify bottlenecks, capture memory and communication overheads Knowledge sharing with teammates through thorough documentation PREFERRED EXPERIENCE: Preferred experience in SOC architecture OR Performance analysis. Strong background in Computer architecture, Hardware performance metrics and bottlenecks. Experienced in modelling and simulation of hardware. Experience in performance profiling, creating experiments to address various use-cases and doing design space exploration. Good to have experience of creation of designs for ACAP devices or HLS. Good communication skills ACADEMIC CREDENTIALS: bachelors or Masters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

We are seeking a Talent Partner to directly support our operations, finance, accounting and legal business units. You will apply your creativity and superlative people skills to attract the best of class team members who will resonate with MX mission, mindset and disposition. Job Duties Collaborate with Sr. Talent Partners in establishing strategies for attracting the talent required for MX to execute on its ambitious mission . Implement key initiatives in recruiting key sales-centric disciplines throughout the organization. Collaborate with Talent and Hiring managers in streamlining the full recruiting cycle. Engage in community and industry networking events within the FinTech and startup world. Leverage key metrics in analyzing and refining staffing projections and results. Partner with People Experience and hiring managers to drive the recruiting process through on-boarding. Ensure an amazing candidate experience through high-touch, personalized outreach and engagement. Basic Job Requirements 3+ years of related recruiting experience preferred. Strong understanding of direct sourcing and effective interviewing techniques. Embrace and articulate the MX story, vision, and culture. Proven track record for successfully identifying and qualifying exceptional exception candidates with staying power. Blend of aptitude, communication skills, organizational skills and follow through. Comprehensive expertise in the full spectrum of talent acquisition and retention. Ability and desire to adapt quickly and thrive in a fast paced, often ambiguous, high-stakes environment. Ability to multitask, organize, prioritize, and manage time effectively. Ability to follow-up and follow-through with an engaging touch. Advanced Requirements 2+ years of related recruiting experience at a tech company in the Silicon Slopes region. Strong understanding of various positions, compensation structures, accelerators, local market, and methodologies preferably in the enterprise SaaS space.

The Unified Memory Controller team is looking for a passionate and self-motivatived design engineer to join our growing team. As a key contributor , you will be part of a leading team that develops industry-leading memory controllers used across a wide variety of AMD products. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Microarchitectural design and RTL implementation of IP features Analyze RTL design for power optimization and timing optimization Collaborate with Design verification team to execute on design features/timing/synthesis Participate in design specification and RTL code reviews PREFERRED EXPERIENCE: Digital design engineering experience with 4+ Years. Excellent knowledge of verilog, system verilog, C and a scripting language; experience with python, perl and tcl Proficient in debugging RTL code using simulation tools Knowledge of clockign architectures, synchronization, and CDC methodology DDR, memory controller design experience is preferred Strong understanding of computer architecture ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering