636 Silicon Jobs - Page 3

He / She contributes to the component engineering and obsolescence management for Thales SIX products- Formalizes the function description, technical requirement and specifications- Elaborates the specification and the engineering plans used to develop the product (production of the Data Package Definition - Performs development activity as per the CHORUS 2-0 process- To provide technical expertise and support: The scope of work includes activities related to identifying, assessing, and managing the risks associated with the obsolescence of components used in Thales products- The Component and Obsolescence Monitoring Engineers are expected to monitor the lifecycle of components, forecast potential obsolescence issues, and implement effective strategies to mitigate these risks To ensure continuous availability of critical components for Thales products- To proactively manage and mitigate risks related to component obsolescence- To maintain a high level of product reliability and performance Be accountable for the validation of selected components on our different project and provide feedback where applicable- BOM Scrub: Analysis of BOMs (Bill of Materials), Proactive BOM Scrubbing and Risk Assessment Alert Monitoring: Analyse all obsolescence notifications (PDNs, PCNs, Obsolescence Alerts) from providers and any other sources to identify potential alternate components Continuously monitor alerts related to component obsolescence and input them into the Component Database Evaluate the impact of alerts at the Part, BOM, Assembly, Product/ Unit level, tracking and reporting frequency and severity Suggest alternative components when suitable solution already exists in the Thales preferred parts list, or already exists in the Thales component library- Find the best component solution with the designer and the purchase who respect components strategies Prepare regular reports on alert status and impact, highlighting significant findings and trends Identify Obsolescence and other issues and provide replacement/alternative parts/components to meet project/customer reliability, safety and legislative requirements Cost Mitigation knowledge on obsolescence : Alternate solutions, Bridge Buy, LBO, LTB and other strategies Measure the timeliness of response to obsolescence issues and establish reaction time Management of data within supported Thales tools Skills Required Essential Obsolescence Management expertise BOM/Part Obsolescence Monitoring expertise Experience working with PLM (Wind-chill/ PALMA/Team center ) Parts/component database management expertise PDNs/ PCN processing expertise Data Providers (Silicon Expert, I H S MARKIT, Total Parts Plus ) Obsolescence Monitoring expertise using any or all the data providers Identification of Alternates of all Electrical and Electronic, Mechanical and Software Solutions to mitigate obsolescence issues Change Management in PLM/ equivalent databases Automation of certain process using software language (Excel, Python, VBA Scripts, C, C++ --) Years of experience 2 to 4 years of experience in Component Engineering and Obsolescence Management Educational Qualification Bachelor Degree in Engineering in Electronics/Electrical Engineer Values and Behaviors Ability to work in cross-functional teams and communicate with international teams effectively- Client focused (Customer First) Demonstrates behavior that is consistent with the Thales Behaviors Maintains an ethical approach to business, in line with the Thales ethics policy- Ability to report Good communicator Self-motivated and proactive Reactivity Ability to follow several projects at the same time Language Ability communicate in English verbally and through written form-

You are a seasoned professional with a passion for analog design and a knack for solving complex problems- With a strong foundation in CMOS processes and deep submicron technologies, you bring a wealth of knowledge and experience to the table- You thrive in a collaborative environment, where your excellent communication skills enable seamless interactions with internal development teams- You are adept at executing circuit design tasks with precision, ensuring the highest product quality and efficiency- Your familiarity with ASIC design flow and JEDEC standards for DDR interfaces sets you apart, and you are always eager to learn and adapt to new challenges- Your technical acumen, combined with your dedication and innovative mindset, makes you an ideal fit for our team- What You ll Be Doing: - Ownership of complete physical implementation at block level & chip level- Responsible for delivering timing clean blocks/chip level that meet design targets- - DRC, LVS & IR closure- Evaluates all aspects of the physical design flow from place and route, timing, PV & IR and is able to setup these flows- - Experience in all chip level tasks (P&R, STA, PV, IR) - Work closely with the frontend design team to resolve design issues - The Impact You Will Have: Enhancing the performance and efficiency of our silicon IP portfolio- Contributing to the rapid integration of advanced capabilities into SoCs- Reducing the time-to-market and risk for our customers products- Driving innovation in analog design and setting new industry standards- Strengthening Synopsys position as a leader in chip design and verification- Empowering the development of high-performance, differentiated products- What You ll Need: - Candidates with MSEE/BSEE with 5+ years of related experience- Possesses in depth understanding of specialization area plus working knowledge of one other related area- - Resolves issues in creative ways- - Exercises judgement in selecting methods and techniques to obtain solutions- - Executes project responsibilities from start to completion- - Contributes to moderately complex aspects of a project- - Determines and develops recommendations to solutions- - Works on team-driven or task-oriented projects- - May guide more junior peers with aspects of their job- - Networks with senior internal and external personnel in own area of expertise- - Strong knowledge on scripting using tcl, perl - Who You Are: A collaborative team player with a proactive approach- Detail-oriented with a commitment to quality and efficiency- Innovative and adaptable, always seeking to learn and grow- Effective communicator, able to convey technical information clearly- Problem-solver with strong analytical skills- The Team You ll Be A Part Of: You will join a dynamic team of talented engineers dedicated to pushing the boundaries of analog design- Our team is focused on delivering high-quality silicon IP solutions that meet the unique performance, power, and size requirements of our customers- We foster a collaborative environment where innovation and continuous learning are highly valued- Together, we drive the development of cutting-edge technologies that shape the future of the semiconductor industry

As our Quality Inspector, you ll play a key role in ensuring the highest standards of product quality and supporting continuous improvement initiatives that drive innovation and sustainability- Your impactSuccess means delivering consistently reliable and defect-free materials and assemblies, which will enhance product performance and customer satisfaction- You ll collaborate with supplier quality teams, production, engineering, and safety functions and take ownership of material inspections, non-conformance reporting, supplier audits, and process audits, helping us move toward a more efficient and sustainable future- What You ll Be Doing Inspect and test incoming materials such as metal parts, PCBs, fasteners, and busbars Prepare clear and accurate reports for all inspected materials Create Non-Conformance Reports (NCR) for rejected items and qualification reports for samples Support supplier quality improvement and participate in supplier audits Carry out initial and final inspections of assembled stacks Document all outward inspection results Lead monthly process audits to help us keep improving- What Were Looking For Diploma in Mechanical Engineering or a similar field- 3 5 years of experience in quality inspection or a related job- Experience using testing tools and equipment- Proficient in Microsoft Office or open to learning new computer skills- Works well with others, reliable, and manages time well- Create and spread positivity in workplace and actively support to increase the morale of the colleagues- The candidate who is curious, adaptable to embrace new ideas, best practices and challenges- Candidates from Thane, Navi Mumbai, or Kalyan-Dombivli are encouraged to apply- What Youll Get from Us Join a Performance Management System (PMS) and Root Cause Problem Solving (RCPS) team, where you will strengthen your cross-functional problem-solving abilities- Work closely with diverse stakeholders, enhancing your skills and broadening your perspective- Be an active participant in Safety initiatives to support continuous safety improvements

He / She contributes to the component engineering and obsolescence management for Thales SIX products- Formalizes the function description, technical requirement and specifications- Elaborates the specification and the engineering plans used to develop the product (production of the Data Package Definition - The scope of work includes activities related to identifying, assessing, and managing the risks associated with the obsolescence of components used in Thales products- The Component and Obsolescence Monitoring Engineers are expected to monitor the lifecycle of components, forecast potential obsolescence issues, and implement effective strategies to mitigate these risks To maintain a high level of product reliability and performance BOM Scrub: Analysis of BOMs (Bill of Materials), Proactive BOM Scrubbing and Risk Assessment Alert Monitoring: Analyse all obsolescence notifications (PDNs, Educational Qualification Bachelor Degree in Engineering in Electronics/Electrical Engineer Years of experience 2 to 4 years of experience in Component Engineering and Obsolescence Management Skills Required Obsolescence Management expertise BOM/Part Obsolescence Monitoring expertise Experience working with PLM (Wind-chill/ PALMA/Team center ) Parts/component database management expertise PDNs/ PCN processing expertise Data Providers (Silicon Expert, I H S MARKIT, Total Parts Plus ) Obsolescence Monitoring expertise using any or all the data providers Identification of Alternates of all Electrical and Electronic, Mechanical and Software Solutions to mitigate obsolescence issues Change Management in PLM/ equivalent databases Automation of certain process using software language (Excel, Python, VBA Scripts, C, C++)

PMTS - GFX Design Technical Lead Role: We are currently seeking a highly skilled Principal Member of technical staff (PMTS) Design engineer for GFX top level end-to-end design. Responsibilities: In this role, he/she would be the technical lead responsible for driving design, quality and debug throughput of top-level development and support post-silicon debugs. Working with architects and verification leads and driving quality microarchitecture specifications. Developing design infrastructure and needed improvements Developing design strategy for quality. Driving design closure to meet schedule with quality Working with each domain (sub-system) lead and guide them to get better quality and design outcome. Helping management with risk assessment on features, quality, and schedules Working with sub-system design leads to identify potential areas of formal verification. Requirements: BS +14 years or MS +12 years work experience preferred. Should have end to end GFX/Compute design experience and system knowledge. Experience with advanced design methodologies and microarchitecture. Familiarity with all verification areas and tools and confirmed understanding of verification/technology interactions Good understanding of memory hierarchy, caches, address translations schemes. Good understanding of general dram technologies and address translation schemes Familiarity with GFX pipeline and GPU design is plus Familiarity with Computer organization/architecture. Strong analytical/problem solving skills and pronounced attention to details. Formal property-based verification knowledge is an added plus. Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required Academic credentials: B.E/B.Tech or M.E/M.Tech degree in ECE / Electrical Engineering / Computer Engineering Location: Bangalore, India #LI-NS1

We are now looking to hire strong performance verification engineers with a sharp understanding of CPU and memory architecture. NVIDIA makes some of the fastest CPUs in the world and is solving problems, with its vast arsenal of CPUs, GPUs and SW, in areas such as High-performance computing, Automated driving, Medical imaging and much more! We are seeking highly motivated engineers to join this dynamic and innovative team that owns performance alignment of CPUs and CPU fabrics made by NVIDIA! Do you want to be part of the team that explores and defines the next generation of CPUs What will you be doing: Responsibilities will include development of test plans and strategies, develop simulation environments, system bring-up, validation, and automation to deliver best-in-class CPUs. Develop and maintain CPU simulator infrastructure, hardware CPU test and performance infrastructure. Analyze and validate CPU and fabric performance, helping to understand current, and guide the development of future CPU products. Definition and development of tool chain and workflows that enables the full system performance alignment. Silicon based competitive analysis of NVIDIA CPUs. What we need to see: Masters or Bachelors degree in EE/CS or equivalent experience 5+ years of experience preferably in the areas of CPU / SOC Performance Verification and Analysis Strong understanding of computer system architecture and operating system fundamentals. Hands-on experience with HDLs such as Verilog / System Verilog. Knowledge of verification methodologies and tools for IP and SoC level verification. Experience with System Verilog, C/C++, Python languages and relevant frameworks. Background with debug on Silicon. Ways to stand out from the crowd: Detailed knowledge of the ARM and/or x-86 architecture. Prior experience with performance analysis of CPUs. Experience with analysis and characterization of CPU workloads. #LI-Hybrid

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! What you ll be doing: Work on structural and functional verification of low power aspects of NVIDIA s family of chips. Come up with test plans and coverage plans of these features. Write test cases, test bench components like assertions and coverage points, and own verification convergence. Collaborate with system level and unit level teams to cover the features well from functional, electrical, performance, and noise aspects. Work with architects, designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks. Validate the effectiveness of the low power features on silicon. What we need to see: BS/MS or equivalent experience with specialization related to Low Power techniques and Verification. 2+ years of experience. Fundamental understanding of power basics including transistor-level leakage/dynamic characteristics of VLSI circuits. Knowledge of power intent formats - UPF/CPF. Experience in Static Power check - tools like VCLP/MVRC or similar. Hands-on knowledge in Power aware dynamic verification - NLP/MVSIM or similar tools. Experience in design and verification tools (VCS or equivalent simulation tools, Verdi or other debug tools). Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS). Ways to stand out from the crowd: Good software programming skills. Python/Perl/C++ preferred. Confident debugging and problem-solving skills. Good communication skills and ability & desire to work as a great teammate. With competitive salaries and a generous benefits package, Nvidia is widely considered to be one of the most desirable employers in the world. #LI-Hybrid

SE NIOR SILICON DESIGN ENGINEER 1. Must have SoC implementation knowledge with deep level expertise in at least one domain. Have responsibility for processes of significant technical importance and for results in SoC implementation and/OR related areas. Solve complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation. Influences technical decisions that have a significant impact on final product. Requires limited supervision and is evaluated according to project performance. Coaches and mentors less experienced staff; influences others as a technical leader. very good communication and presentation skills Proficiency in scripting Required Skills: SoC implementation expertise. Multi million gates integration. Low power implementation, Constraints validation, Formal verification Floorplanning, Power planning. Clock Tree Synthesis (CTS). Awareness of Synthesis, SCAN and DFT implementation Static Timing analysis (STA). Analysis: IR, EM, Noise. Physical Verification #LI-PK2

MTS SILICON DESIGN ENGINEER (AECG ASIC TFM Lead) THE ROLE: As a Silicon Design Engineer in the AMD AECG ASIC TFM (Tools Flows Methodology) team, you will work with design experts to come up with the best implementation methodologies/flows and work on development and support of the BE flows. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Define and drive key Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Excellent physical design and timing background. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. At Amazon, DFT (Design-for-Testability) is a multi-faceted job that involves architecture definition, logic design, verification, test patterns generation, chip bring-up and more. As a DFT Engineer, you will impact and see the device through its entire lifecycle, from definition stage to high volume production. You will be working in close collaboration with multiple VLSI engineering groups including design, verification, backend, test, reliability and more. As part of the chip design group, you will: Contribute to the design and verification of DFT logic and components Help to drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon Review sign-off level timing closure using static timing analysis of DFT modes Perform wafer probe testing, ATE testing, silicon bring-up, diagnosis and support for physical failure analysis Take high volume chips to production with high coverage ATE test program BS degree in Computer Engineering/Electrical Engineering 5+ years in semiconductor companies as a DFT lead/manager Chip design experience in Verilog and System Verilog Chip verification experience, UVM methodology Scan insertion tools and methodologies MBIST and BISR, BIHR insertion tools and methodologies EFUSE controllers and related structures Top level DFT architecture definition experience Gate-level simulations Static timing analysis, DFT related timing closure Scripting (Perl/Tcl) MS degree in Computer Engineering/Electrical Engineering or related field Excellent communication skills. Should be able to well communicate and establish relations with internal customers , Manufacturing, and equipment vendors Energetic, self-motivated Pro-active, oriented on execution Attentive to details and quality Team player, with the ability to work in a rapidly evolving/changing environment Ability to work well with overseas partners

SENIOR PHYSICAL DESIGN ENGINEER SmartSoC is looking for smart and enterprising Physical Designer Engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. This role will involve Physical design at the block and chip level of complex designs in the latest technologies. Desired Skills and Experience- 3 – 10 years relevant experience Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background of Floor planning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing and Signal Integrity closure Experience at taping out multiple chips, strong experience at top level at latest technology nodes Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

SENIOR VERIFICATION ENGINEER- SV UVM SmartSoC is looking for smart and enterprisingDesign Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. SmartSoCs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM. Job Responsibilities- Build SV, SV UVM, OVM based environments. Work with many different networking and other protocols Desired Skills and Experience- 3 to 10 years of experience in IP verification Good experience in SV/ UVM based verification project. Good debug skills is a must. Experience in building components like Scoreboard, functional coverage & writing sequences using SV/UVM based Verification environment One of the following experiences is important: Experience in Video/Display domain in particular DP, oLDI, MIPI CSI/ DSI Experience in any one high speed protocol like USB3, PCIe, MIPI, Unipro etc Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USADelaware

RTL DESIGN LEAD ENGINEER The ideal candidate will be required to work on both IP development and integration into SoCs catering to various markets and tech nodes. The job will involve RTL design, front-end tools flow, and SoC integration/porting-related tasks. Desired Skills and Experience- 8+ years of Experience Engineering experience with exposure to front end ASIC tool flows Should be self-driven and independent in tracking and closing tasks with respective holders. In depth knowledge of AHB and bus infrastructures like matrix and fabrics Good understanding of ARM based SoC Architecture Exposure to ARM Cortex A/M integration or support Good understanding of SoC DV methodology Good experience in Low-Power design methodology Hands-on experience with ASIC tools Lint, CDC etc System Verilog/Verilog RTL coding Power aware RTL coding/design knowledge Understanding of Clock-Structures/Scheme Good Communication Skills Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USATexas

Pre-Silicon Validation Engineer Experience4 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Creating test environments, checker strategies, and test generators for validating embedded power management firmware in the SOC Communicating effectively, coordinating and working with firmware developers and SOC integration teams Potentially participating in the debug of failures in silicon and developing new testing strategies to detect these failures on pre-silicon models Mentoring junior members of the team in their development You should have 3-5 years of experience in the following areas: SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM Reading and interpreting technical specs and Register Transfer Level (RTL) code SW development skills (Unit Testing, Test Driven Development) Hands-on Debug Preferred Skills and Experience: Expertise in any of one domain like Audio, Performance, power management will be a huge plus 4+ years’ experience with writing validation plans and implement those validation plans Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul USATexas

Post Silicon Validation Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Experience in silicon lab validation for power management ICs. Experience with validation of Mixed-signal ICs. Experience in validation test planning, test development, execution, debug and report preparation. Hands-on experience of using lab equipment such as oscilloscope, signal analyzer, signal generator, etc. familiarity of programming and scripting languages like Python, Perl Experience in automation using NI Labview is an advantage Understanding of power management ICs, architecture, specifications interpretation is required Debug skills to zero in on an issue, coordination with cross-functional teams is required Skills Experience LabVIEW, PMIC, Post Silicon Validation, System Validation, Testing Validation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore USATexas

1-3 years of experience in RTL DFT Verification (DFx). Good Understanding of JTAG IEEE-1149.1 and IJTAG IEEE P1687 standard. Understanding of using ICL and PDL files for verification and knows to create a testbench. Experience in JTAG RTL verification within any UVM. Able to debug simulation fails effectively utilizing debug tools like Synopsis Verdi. Basics of system Verilog, Basics of UVM, and preferably System Verilog assertions Scripting knowledge of TCL/Perl. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Physical Design Engineer Experience 4-10 yrs Job Overview: Strong background of ASIC Physical DesignFloor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.. Hands-on experience on technology nodes like 5nm,7nm, 14nm, 10nm. Good knowledge of EDA tools from Synopsys, Cadence and Mentor Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS) Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida

We are seeking a highly skilled and motivated Mixed Signal Verification Engineer to join our team with 8+ years of expeirence. As a Mixed Signal Verification Engineer, you will be responsible for developing and implementing testbenches, checkers, and tests using System Verilog. You will also play a key role in creating and utilizing real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations. Ownership of Analog/Mixed designs at the chip and/or block level will be an important aspect of this role. Responsibilities: Develop and build Mixed-Signal testbenches, checkers, and tests using System Verilog. Create and utilize real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations. Take ownership of Analog/Mixed designs at the chip and/or block level, ensuring successful verification. Good Understandingof GLS simulations Collaborate with design engineers to understand design tradeoffs and create high-level models for design analysis. Perform behavioral modeling for verification simulations to validate the functionality and performance of mixed-signal designs. Debug and resolve issues arising from verification simulations and work closely with the design team to address any design-related concerns. Stay updated with the latest advancements in mixed-signal verification methodologies and tools, and drive continuous improvement initiatives. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Candidates need to have good experience in Tessant tools Candidates need to have good experience in ATPG pattern generation and simulation(both timing and no timing) Candidates need to have good experience in Scan insertion Experience should be more than 6+ years Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

We are seeking a highly skilled and experienced Lead Verification Engineer with expertise in USB/LPDDR and a strong knowledge of Cadence VIP. The ideal candidate will have a deep understanding of low-power design and verification techniques. Responsibilities: Develop and execute comprehensive verification strategies for USB/LPDDR subsystem designs, considering low-power design requirements. Collaborate with cross-functional teams to define verification goals and ensure alignment with project objectives. Design and implement reusable, scalable, and efficient verification testbenches using SystemVerilog/UVM or C based . Leverage Cadence VIP and other verification IPs to accelerate the verification process. Low-Power Design VerificationApply expertise in low-power design and verification techniques to ensure accurate and reliable verification of power management features, including power states, power domains, and power-aware verification methodologies. : Extensive experience (8+ years) in verification. Strong knowledge of Cadence VIP and verification methodologies (SystemVerilog/UVM). Proficiency in low-power design techniques and power-aware verification methodologies. Hands-on experience with industry-standard simulation and verification tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Questa). Solid understanding of verification languages (SystemVerilog, VHDL) and scripting languages (Perl, Python, TCL). Familiarity with industry standards and protocols related to USB (USB 2.0, USB 3.x) and LPDDR (LPDDR4, LPDDR5). Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

We are seeking a skilled and motivated DDR5/SerDes Verification Engineer to join our organization. As a DDR5/SerDes Verification Engineer, you will be responsible for verifying and validating the functionality and performance of DDR5 memory subsystems and high-speed SerDes interfaces. In addition to strong DDR5 and SerDes verification expertise, knowledge and experience with sideband I2C and I3C protocols would be considered a plus. Candidate should have Design and implement advanced verification environments and test benches using SystemVerilog/UVM Experience4-10 Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Job Location: Bengaluru (BLR) and Hyderabad (HYD) Experience: 7 to 20 years : We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of ARM Micro Architecture to join our team. In this role, you will play a key role in the development of complex digital designs and contribute to the success of our cutting-edge projects. The ideal candidate will have a proven track record in RTL design and a deep understanding of ARM Micro Architecture. Key Responsibilities: Collaborate with cross-functional teams to define and develop RTL designs for advanced microprocessor-based projects. Design, implement, and verify digital logic blocks and modules in accordance with project specifications and quality standards. Utilize your expertise in ARM Micro Architecture to optimize and enhance design efficiency. Perform RTL simulations and conduct thorough functional and timing analysis. Identify and resolve design issues, ensuring the delivery of high-quality RTL designs. Stay up-to-date with industry trends and emerging technologies to continually improve design methodologies. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience as an RTL Design Engineer with 7 to 20 years of relevant work experience. Strong knowledge of ARM Micro Architecture and its application in RTL design. Proficiency in RTL design tools and methodologies. Experience with simulation and verification tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS). Excellent problem-solving skills and attention to detail. Effective communication and collaboration skills. Ability to work effectively in a dynamic and fast-paced environment. If you are a highly motivated and experienced RTL Design Engineer with a passion for innovation and a strong background in ARM Micro Architecture, we encourage you to apply for this exciting opportunity. Join our team and contribute to the development of cutting-edge technology solutions. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Excellent communication skills, both verbal and written Experience: Minimum of 7 years of experience in the field Proficiency in DVT pattern experience Experience with ATE and functional vectors generation Understanding of Stimgen flow Prior experience with AMD is preferred Skills: Strong debugging skills Experience with MBIST, JTAG, and Phy-loopback NoteCandidates are encouraged to provide a detailed resume showcasing their relevant experience and skills. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Job Title: ASIC RTL Design Engineer Position Experience Level: 6 to 10 years Location: Bangalore : We are seeking a highly skilled and experienced ASIC RTL Design Engineer to join our team in Bangalore. The successful candidate will have 6 to 10 years of relevant experience and will play a crucial role in the design and integration of RTL components for complex ASIC projects. The candidate should possess a strong background in RTL UPF, SoC Design Integration, and multi-domain UPF methodologies. Additionally, a strong understanding of resolving VSI issues is required to excel in this role. Key Responsibilities: RTL UPF Experience: The ideal candidate should have a proven track record of working with RTL UPF (Unified Power Format) to efficiently manage power intent for ASIC designs. SoC Design Integration: Experience in the integration of RTL components into System-on-Chip (SoC) designs, ensuring seamless functionality and performance. Multi-Domain UPF: Proficiency in working with multi-domain UPF to address power management across different aspects of the design. VSI Issue Resolution: Ability to identify and rectify VSI (Voltage Storm Immunity) issues to enhance the reliability and robustness of the ASIC design. Additional : In addition to the core responsibilities, candidates who have experience in addressing UPF constraints and issues during the synthesis process and Engineering Change Orders (ECOs), including mitigating RTL-UPF mismatches, will be considered favorably. This position offers an exciting opportunity to work on cutting-edge ASIC projects, pushing the boundaries of design and innovation. If you are a seasoned RTL Design Engineer with the requisite experience and skills, we encourage you to apply and join our dynamic team in Bangalore. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore