636 Silicon Jobs - Page 8

Minimum qualifications: Bachelor's degree in Computer Science, a related technical field, or equivalent practical experience. 2 years of experience in C++ development. Experience in data structures and algorithms. Preferred qualifications: Master's degree in Computer Science, a related technical field, or equivalent practical experience. Experience with compilers and performance optimizations. Experience with Low Level Virtual Machines (LLVM). About the job Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google s needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Build compilers and tools that map ML models (with a focus on computing use cases) to the hardware Infrastructure Support Agreement (ISA). Evaluate various trade-offs of different parallelization strategies such as performance, power, energy and memory consumption. Collaborate with machine learning researchers to improve the domain-specific compiler. Collaborate with hardware engineers to evolve future accelerators.

Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. 8 years of experience in high-performance design, multi-power domains with clocking. Experience in multiple SoCs with silicon success. Experience with Verilog or System Verilog language. Preferred qualifications: Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation. Experience with chip design flow and an understanding of cross-domain involving DV/DFT/Physical Design/Software. Knowledge of one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Lead a team of ASIC RTL engineers on sub-system and chip-level Integration activities including plan tasks, hold code and design reviews, code development of complex features. Interact closely with architecture team and develop implementation (e.g., microarchitecture and coding) strategies to meet quality, schedule and performance, power, and area (PPA) for sub-system/chip-level integration. Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.

Minimum qualifications: Bachelor's degree in Electronics, Computer Science, a related field, or equivalent practical experience. 2 years of experience in a hardware or embedded testing/automation role. Experience testing embedded software on SoC on Linux, Android or Real-Time Operating System. Preferred qualifications: 5 years of experience in a hardware or embedded testing/automation role. Experience in Linux kernel driver test automation and framework development. Experience in Android application development. Excellent programming skills in modern Python. Excellent programming skills in Java, C/C++, JNI. About the job Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Take ownership of delivering exceptional software quality for one or more Intellectual Property (IP) within silicon software. Create and implement test strategies by working with development teams to identify risk areas and fill the testing gaps. Drive test automation using existing test frameworks and work with the Engineering Productivity team to enhance and develop new test frameworks based on test requirements. Cultivate Product and Engineering Excellence as a core value in test engineering and our associated development partners. Triage and analyze test results and incoming feedback to identify areas for improvement. Guide, mentor, and coach other team members with regards to process technology.

Minimum qualifications: Bachelor's degree in Computer Science, a related technical field, or equivalent practical experience. 2 years of experience in designing, developing, or troubleshooting Linux, networking. Experience with creating or optimizing deployment or support processes for linux based desktops and servers, software, and patches. Preferred qualifications: Experience in automating/scripting support processes. Experience with Google Cloud Platform. Understanding of IT infrastructure, with the ability to troubleshoot issues. Excellent customer service, organizational, prioritization, multitasking, communication, and leadership skills. About the job Technical support for a technology company is a big task. As the Corporate Operations Engineer within the IT Support Technician team, your mission is to enable the people and technology that keep Google running. Your team provides the front line user support for all of our internal tools and technologies. Beyond the day-to-day, the team will contribute to longer-term technical projects, process improvement and the documentation efforts that help make the Google magic happen. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Responsibilities Provide support to help improve the productivity of silicon engineers. Develop scripts, tools, processes or solutions to prevent problems, improve user productivity and automate recurring tasks as part of global service improvements. Partner with peers, vendors and other technical support teams to coordinate troubleshooting, process and resolution for incidents and problems in a timely manner. Develop scripts, tools, processes or solutions to prevent problems, improve user productivity and automate recurring tasks as part of and global service improvements.

Minimum qualifications: Bachelor's degree or equivalent practical experience. 7 years of experience in business development, partnerships, management consulting, or investment banking, in the Consumer Electronics, Auto, OEMs, Telecom, E-Commerce/Retail, Apps, Ads, Gaming, or Technology industries. Experience working with C-level executives and cross-functionally across all levels of management. Experience managing agreements or partnerships. Preferred qualifications: 8 years or more of semiconductor experience in the EDA/3PIP/ASIC partner management. Experience in driving EDA/3PIP/ASIC partnership with cross-functional deliverables, with the ability to engage and deliver results. Knowledge of EDA design flows and 3PIP ecosystem. Knowledge of product and technology development processes and strategies, and EDA and IP platforms. Excellent collaboration skills across multiple business units to align and execute deliverables. About the job Google's line of products and services to our clients never stops growing. The Partnerships Development team is responsible for seeking and exploring new opportunities with Google's partners. Equipped with your business acumen and extensive product knowledge, you are right on the front line of interacting with our partners, and helping them find ways to grow using Google's newest product offerings. Your knowledge of relevant verticals and relationships with key industry players will help shape our great applications and content for products such as YouTube, Google TV and Commerce. The Custom Silicon Sourcing team plays a crucial role in the development of Pixel products. The team is responsible for sourcing third-party IP and EDA tools and managing relationships with the suppliers. The goal is to ensure the delivery of committed SoC and chip components. The Global Partnerships organization is responsible for exploring new opportunities with Google's partners. Google s Global Partnerships team works with a wide range of partners to bring the best of Google to power their business. The Global Partnerships team supports Google s own Product teams with essential partnerships to help Google s user experiences in advertising, Search, Assistant, Maps, Travel, Shopping, Payments and more. Teams create product-enabling partnerships, go-to-market strategies and incubate business growth for a variety of products. Responsibilities Drive EDA and 3PIP partner engagements. Manage contract process from start to finish including negotiating agreements, financial terms, timelines, amendments and SoWs. Manage suppliers on an ongoing basis with agreed upon KPIs. Evaluate new supplier engagement opportunities and provide recommendations to the management team, communicate and collaborate with a broad range of cross-functional constituents (e.g., product, engineering, marketing, finance, sales, legal). Build, maintain and evolve relationships with a variety of internal and external stakeholders, partner with key stakeholders and provide insights on product plans and roadmap availability to engineers and program managers.

Minimum qualifications: Bachelor's degree in computer science, a related technical field, or equivalent practical experience. 1 year of experience in IT operations, troubleshooting Linux, technical support, customer engagement and networking. Preferred qualifications: Experience with Google Cloud Platform (GCP). Experience with high-performance computing (HPC) tools and infrastructure. Understanding of customer workflows, pain points, and the design and implementation of technical solutions. About the job Technical support for a technology company is a big task. As the Corporate Operations Engineer within the IT Support Technician team, your mission is to enable the people and technology that keep Google running. Your team provides the front line user support for all of our internal tools and technologies. Beyond the day-to-day, the team will contribute to longer-term technical projects, process improvement and the documentation efforts that help make the Google magic happen. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Responsibilities Provide remote and technical support to engineers, including root cause analysis of IT issues on multiple technologies and platforms, directly contribute to their productivity and operational efficiency. Collaborate and partner with internal peers, external vendors, and other technical support teams to coordinate and expedite troubleshooting, process improvements, and the timely resolution of technical incidents and problems. Develop, implement, and maintain scripts, tools, processes, and automated solutions to prevent technical issues, enhance user productivity, and streamline recurring tasks as part of service improvements. Own and manage IT projects focused on technical solutions and improvements, ensuring design, planning, and delivery. Analyze data to demonstrate the business impact and value of delivered technical projects and solutions.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience 6 years of experience with 4G/5G cellular protocols or Android Connectivity. 5 years of experience in testing, and launching cellular products. 3 years of experience in a technical leadership role. Preferred qualifications: Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Experience in machine learning or connectivity improvements. Experience in analyzing connectivity metrics data points to identify areas for improvement. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will design, develop, test, deploy, maintain, and enhance system solutions. You will collaborate, drive, and work with teams for Pixel phones and other Pixel devices to enhance the cellular connectivity experience of the device adapting based on device and user context. You will characterize the connectivity behavior of the Pixel device and understand any issues and improvements, and work within organization or cross organization to develop new features/frameworks to exploit the possible optimization, improve the debug capabilities and troubleshooting techniques. You will focus on designing and delivering the helpful mobile experience. You will work on the future of Android/Pixel devices and services through the advanced designs, techniques, products, and experiences in consumer electronics.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Responsibilities Work on connectivity specific metrics across stack to propose and design new cellular connectivity features in Android applications or in the Android framework for Pixel, with additional software components on the server side. Lead metrics recommendation that allow the monitoring of the performances of Pixel devices to validate implementations and detect issues that can impact the user experience or the performance of the devices. Leverage advanced machine learning to automate data analysis, identify anomalies, and uncover hidden patterns. Benchmark Pixel cellular power performance, investigate anomalies and propose and implement performance optimizations across the stack. Own and drive improvements for connectivity metrics, alerts, visualizations, and data-motivated insights.

Minimum qualifications: Bachelor s degree or equivalent practical experience. 2 years of experience with software development in one or more programming languages, or 1 year of experience with an advanced degree. Preferred qualifications: Master's degree or PhD in Computer Science or related technical field. 2 years of experience with data structures or algorithms in either an academic or industry setting. 2 years of experience working with embedded operating systems. Experience developing accessible technologies. About the job Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google s needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. With your technical expertise you will manage project priorities, deadlines, and deliverables. You will design, develop, test, deploy, maintain, and enhance software solutions. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Participate in, or lead design reviews with peers and stakeholders to decide amongst available technologies. Review code developed by other engineers and provide feedback to ensure best practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency). Contribute to existing documentation or educational content and adapt content based on product/program updates and user feedback. Triage product or system issues and debug/track/resolve by analyzing the sources of issues and the impact on hardware, network, or service operations and quality. Write product or system development code.

Minimum qualifications: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 2 years of experience with IJTAG ICL, PDL terminology, ICL extraction, ICL modeling with Siemens Tessent Tool. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field. Experience scripting in Python or Perl or other related language. Experience with silicon process and technology nodes for high speed and low power consumption. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Develop test patterns that optimally tests the logic/Memory/Analog Macro under test. Work with internal cross-functional teams, external silicon partners, Product Engineering team, and Intellectual Property (IP) vendors to support structural validation and parametrically characterize the Silicon. Collaborate with cross-functional teams to debug failures (e.g., boards, software, manufacturing, design, thermal issues).

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience with accelerator architectures and data center workloads. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the job In this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes.

Bachelor's degree in Electrical Engineering, Computer Science or equivalent practical experience. 4 years of experience with Design Verification. Experience with System Verilog and Verification techniques. Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science, or a related field. Experience creating/using verification components and environments in methodology (e.g., VMM, OVM, UVM). Experience with scripting languages like Perl or Python. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design verification leads and design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM and/or formally verify designs with SVA and industry leading formal tools. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications: Bachelor's degree in Computer Science, IT, a related field, or equivalent practical experience. 5 years of experience with static timing analysis, synthesis, physical design & automation. Experience in physical design tool automation such as synthesis, P&R and sign-off tools. Preferred qualifications: Experience in extraction of design parameters, Quality of Results metrics, and analyzing data trends. Knowledge of timing constraints, convergence and signoff. Knowledge of parasitic extraction tools and flow. Knowledge of Register-Transfer Level (RTL) languages (e.g., Verilog/SystemVerilog). Knowledge of Static Timing Analysis (STA), Electromigration and IR Drop (EMIR) and PDV signoff methodologies. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Drive the sign-off timing methodologies for mobile System on a chip (SoCs) to push Power Performance Area (PPA) and yield. Analyze power performance area trade-offs across different methodologies and technologies. Work on prototyping of subsystems to deliver optimized PPA recipes. Work with cross-functional architecture, Internet Protocols (IPs), design, power and sign-off methodology teams. Work with foundry to refine signoff methodology to improve convergence and yield.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with Power Management. 4 years of experience with SystemVerilog, Design Verification Test, Universal Verification Methodology. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with Interconnect Protocols (eg. AHB, AXI, ACE, CHI, CCIX, CXL). Experience in low-power design verification. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use. Develop cross language tools and verification methodologies. Create and enhance constrained-random verification environments using SystemVerilog and UVM.

Minimum qualifications: Bachelor's degree in a technical field, or equivalent practical experience. 10 years of experience in program management. Experience in driving program reviews, build schedules cross-functionally, keep program milestones on track. Experience in working with partners on product development schedules, dependencies and budgets. Experience in working with global cross-functional teams such as Engineering, Product, Design and Marketing. Preferred qualifications: 10 years of experience managing cross-functional or cross-team projects. Experience with product development, program management, project management, professional services or engineering management. Experience with chips and embedded systems used in Mobile devices. Experience with working in the Consumer Electronics industry including executing technical programs with external partnerships. About the job A problem isn t truly solved until it s solved for all. That s why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, you ll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. You ll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Responsibilities Establish cadence for portfolio reviews, decision making, prioritization, and resource management; Work on improvements and the impact. Drive program performance gains correlated to execution velocity. Be a change advocate responsible for initiating and leading multiple organizations through pivots needed to address shifts in business trends and priorities. Lead planning framework for a program portfolio including collaborating over resourcing decisions, planning cadence, and planning stakeholders. Collaborate with partners and product engineering teams and work on setting and managing schedules and milestones. Coordinate with Asia-Pacific (APAC) teams for travel and Google Video Conferencing (GVC).

Minimum qualifications: Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience. 5 years of experience in DFT specification definition architecture and insertion. 3 years of experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent). Experience with ASIC DFT synthesis, STA, simulation, and verification flow. Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.). Preferred qualifications: Master's degree in Electrical Engineering, or a related field. Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST). Experience in SoC cycles, including silicon bring-up and silicon debug activities. Experience in fault modeling. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design, insert, and verify the DFT logic. You will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Develop DFT strategy and architecture, including hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO. Demonstrate ownership from DFT logic, pre-silicon verification, to co-work with test engineers post silicon. Insert DFT logic, including boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, Clock Control block, and other DFT IP blocks. Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces. Document DFT architecture and test sequences, including boot-up sequence associated with test pins. Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support post-silicon test team.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, ComputerScience, a related field, or equivalent practical experience. 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases,and test environments. Preferred qualifications: Master s degree in Electrical Engineering, Computer Science, or equivalent practical experience. Experience with low power, debug, Gate Level Simulation (GLS), formal verification. Experience in driving cross functional teams for quality tape-outs Experience leading design verification of IPs, successfully delivered to many SoCs. Experience in driving or owning Sub system level verification and navigating the dependencies with Stakeholders. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Plan the verification of digital design blocks at Sub System level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SVA and industry leading formal tools. Debug tests with design engineers to deliver functionally correct design blocks. Participate with architecture, design teams, Sival and Software (SW) teams in defining the overall verification strategy of our SoCs. Be the primary point of contact for functional verification of the IP for cross-functional teams.

Minimum qualifications: Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, or equivalent practical experience. 8 years of experience working with CPU/GPU benchmark characterization Experience with microarchitecture technology. Preferred qualifications: Master's degree in Electrical, Mechanical Engineering, or equivalent practical experience. Experience with performance analysis tools. Knowledge of system software components, such as Linux, drivers, and runtime. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Collaborate with architecture and system design teams to define clear verification goals and objectives, with a focus on CPU-specific features and performance, particularly within the ARM architecture. Design and implement reusable DV infrastructure components, including testbenches, stimulus generators, and checkers, tailored for CPU verification within the ARM ecosystem. Create and enhance CPU testbench DV flow, focusing on compilation/linking, memory loads, debug hooks, and adherence to ARM specifications. Define and track key coverage metrics to ensure thorough verification and identify potential design flaws in CPU Sub-System. Contribute to power-aware verification, gate-level simulations, and post-silicon CPU bring-up. Work with AMBA buses like CHI (Coherent Hub Interface) and ACE (AXI Coherency Extensions), as well as cache coherency protocols.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in DFT/DFD flows and methodologies. Experience working with fault modeling, test standards and industry DFT/DFD/ATPG tools and with Application-Specific Integrated Circuits (ASIC) DFT, synthesis, simulation and verification flow. Experience developing DFT specifications and driving DFT architecture. Preferred qualifications: Experience using EDA tools like Design Compiler, DFT Max, FastScan, TetraMax, Tessent, SpyGlass, Modus, Tessent, and TestKompress, VCS, NC-Verilog, and waveform debugging. Experience with User Defined Fault Models (UDFM) generation like Cell-Aware and other fault models like GDD, SDD. Experience with STA constraints development and analysis for DFT modes and SDF simulations. Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST and JTAG related issues Knowledge of various Test standards (such as IEEE 1149.10, 1149.6, 1500, 1687) and test formats (such as BSDL, ICL, PDL, STIL, CTL). About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define Design for Excellence (DFX) specifications and develop flows and methodologies for new technology node implementation. Implement/Integrate and verify Design for Testing (DFT) logic, for example, memory built-in self test (MBIST), scan chains, DFT compression, Test Access Port (TAP) controller, BSCN, iJTAG instrumentation, functional BIST, logic BIST and eFuse logic on test chips. Work with silicon engineering team to create test plans and generate test patterns. Participate in post-silicon activity like bring up, diagnostics and characterization. Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies. Provide support to internal teams.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience with Formal Verification (e.g., sequential equivalence checking, Security Path verification, connectivity, low power and Formal property verification). Experience with programming languages (e.g., Python/Perl and TCL). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Science, or a related field. Experience with regression setup and management. Experience with formal sign-offs of industry Application-specific integrated circuit (ASIC) designs. Knowledge of formal verification applications such as sequential equivalence checking, and connectivity checking and data-path verification. Knowledge of formal methodology and formal abstraction techniques. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Plan the formal verification strategy, create the properties and constraints for digital design blocks. Use different formal verification applications to resolve multiple tests like clock-gating verification, low power, connectivity and security path verification. Utilize formal property verification tools combined with formal verification closure techniques to verify properties. Contribute improvements to methodologies and scripting to enhance formal verification results.

Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 10 years of experience with Power and Performance modeling and Analysis. 5 year of experience in people management and developing employees. Preferred qualifications: Master's degree or PhD in Electronics/Computer Science, or a related technical field. Experience with power and performance analysis of hardware IP, System on a chip and use cases to meet the system goals. Experience with producing trade-off analysis for engineering reviews and product roadmap decisions. Knowledge of inter-dependencies of an embedded system. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Manage a team of engineers working on Power and Performance measurements and analysis. Work with a cross-functional team (e.g., Architects, software development, Validation, etc.) in power estimation and use case definition. Perform workload analysis, modeling and system analysis for power or performance and Thermal. Analyze, develop and debug pre-silicon and post-silicon application power/performance. Produce detailed documents for the proposed implementation.

Minimum qualifications: Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering or equivalent practical experience. 3 years of experience with standard GPU workloads like Manhattan/3DMark. Experience with GPU architecture and AMBA Bus protocols like AHB/AXI/ACE. Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science, or a related field. Experience with performance verification of ASICs and ASIC components. Experience with verification of low power techniques. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Be part of a team to verify complex digital design blocks (e.g., CPU, Graphics Processing Unit (GPU), Image processor) by understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Master s degree in Electrical Engineering, Computer Science, or equivalent practical experience. Experience in one or more of the following; high speed controller and physical layer for peripheral component interconnect express, display port, universal serial bus, universal flash storage or low speed IOs such as improved inter-integrated circuit, serial peripheral interface or universal asynchronous receiver transmitter, etc. Experience with Interconnect Protocols (Advanced eXtensible Interface, AXI Coherency Extensions, Coherent Hub Interface, Cache Coherent Interconnect for Accelerators, Compute Express Link). Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Plan and execute the verification of high speed Inputs/Outputs (IOs) ( PCIe, display port, universal serial bus or universal flash storage ) or low speed IOs (improved inter-integrated circuit, serial peripheral interface or universal asynchronous receiver transmitter), IP/subsystem functional verification, power controller and chips pervasive IP. Create and enhance constrained-random verification environments using SystemVerilog and UVM or other industry-standard methodologies. Create and maintain verification environments using SystemVerilog, Universal Verification Methodology (UVM), and define and implement testbench components, such as drivers, monitors, scoreboards, and checkers. Develop cross language tools and verification methodologies. Identify and write all types of coverage measures for stimulus and corner-cases.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with digital logic design, computer architecture, and circuit theory. Experience in scripting language (e.g., Python, Perl) or a hardware description language (e.g., Verilog, VHDL). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience in low-power design verification. Experience developing and maintaining verification testbenches, test cases, and test environments. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.

Minimum qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test including silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. Experience with ATPG, Low Value (LV), Built-in self test (BIST) or Joint Test Action Group (JTAG) tool and flow. Preferred qualifications: Experience with a programming language like Perl with Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC) and DFT timing and Static Timing Analysis (STA). Knowledge of performance design DFT techniques. Knowledge of the end to end flows in Design, Verification, DFT and Partner Domains (PD). Ability to scale DFT. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Work on a team of Design for testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, Static Timing Analysis (STA) checks. Write a Pattern delivery using Automatic Test Pattern Generation (ATPG). Work with Silicon bring-up. Work on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug and deliver debug patterns. Perform Silicon data analysis.

Minimum qualifications: Bachelor's degree in Computer Science, Electrical Engineering or equivalent practical experience. 8 years of experience in compilers (optimization, parallelization, etc.) Experience in Multi-Level Intermediate Representation (MLIR) or Low Level Virtual Machines (LLVM). Preferred qualifications: Master's degree or PhD in Computer Science or a related field. Experience compiling for heterogeneous architectures across IPs, including but not limited to CPU, GPU, and NPUs. Experience running a large program, or several projects. Experience in compiler development for accelerator-based architectures. About the job Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google s needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. The compiler team is responsible for analysis, optimization, and compilation of machine learning models aiming the EdgeTPU Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Work as part of the EdgeTPU compiler team, including analyzing and improving the compiler quality and performance on optimization decisions, correctness and compilation time. Develop parallelization and scheduling algorithms to optimize compute and data movement costs to execute machine learning workloads on the EdgeTPU. Work with EdgeTPU architects to design future accelerators, the hardware/software interface, and co-optimizations of the next generation EdgeTPU architectures. Work with product managers, researchers in identifying key machine learning trends, future use cases, etc. Collaborate with machine learning model developers, researchers, and EdgeTPU hardware/software teams to accelerate the transition from research ideas to user experiences running on the EdgeTPU. Manage a team of experienced compiler engineers.