636 Silicon Jobs - Page 11

Who We Are Simpplr is the AI-powered platform that unifies the digital workplace - bringing together engagement, enablement, and services to transform the employee experience. It streamlines communication, simplifies interactions, automates workflows, and elevates the everyday experience of work. The platform is intuitive, highly extensible, and built to integrate seamlessly with your existing technology. More than 1,000 leading organizations - including AAA, the NHS, Penske, and Moderna - trust Simpplr to foster a more aligned and productive workforce. Headquartered in Silicon Valley with global offices, Simpplr is backed by Norwest Ventures, Sapphire Ventures, Salesforce Ventures, and Tola Capital. Learn more at simpplr.com . Role Overview: As a Principal Data Scientist, you will spearhead cutting-edge AI initiatives and deliver a world-class AI-driven enterprise search solution, Agentic platform, recommendations and other key AI initiatives. You will provide strategic direction, foster innovation, and ensure the successful execution of our product roadmap. You should have a deep understanding of AI/ML technologies, a proven track record of leading successful AI products, and a passion for pushing the boundaries of whats possible. Key Responsibilities: Foster a collaborative, innovative environment and ensure the team stays insulated from external distractions. Drive the end-to-end product lifecycle from ideation and design to implementation and deployment, ensuring delivery excellence with a focus on quality, speed, and innovation. Provide deep technical guidance in AI, machine learning, NLP, and search technologies, staying current with cutting-edge advancements. Champion AI ethics and responsible development: Ensure that AI projects are developed and deployed ethically and responsibly, considering potential biases and societal impacts. Effectively communicate and collaborate with cross-functional stakeholders, confidently advocating for the team s priorities and managing external expectations. Collaborate with cross-functional teams: Work closely with product, engineering, marketing, and other teams to integrate AI solutions into existing workflows and develop new AI-powered products and features. Actively consider product-market fit, customer value, and revenue implications, adopting a founder-like approach to growing and refining the product feature. Independently make key decisions and take ownership of the product s success, proactively addressing challenges and opportunities. Insulate the team from external noise, ensuring they maintain clear focus and direction. Experience & Skills: 7+ years of professional experience. Proven track record of successfully leading and managing AI and search-related product development. Demonstrated hands-on expertise and deep expertise in Artificial Intelligence, Machine Learning, NLP, Information Retrieval, computer vision, reinforcement learning and enterprise search technologies. Strong understanding of enterprise search technologies and architectures. Proven track record in building, scaling, and managing AI-powered products. Excellent leadership, communication, interpersonal, problem-solving, and analytical skills. Proven ability to articulate a clear vision and align teams behind that vision. Strong experience in strategic planning and execution within agile environments. Demonstrated resilience, adaptability, and ability to thrive in fast-paced, evolving environments. Ability to professionally and effectively push back against stakeholder demands. Founder mentality with the ability to create, articulate, and execute a compelling vision and strategy. Qualifications: Bachelors degree in Computer Science, Engineering, AI, Data Science, or related fields. Advanced degree (Masters or PhD) preferred. Bonus Points: Publications in top AI conferences or journals. Experience with cloud-based AI platforms (AWS, Azure, GCP). Simpplr s Hub-Hybrid-Remote Model: At Simpplr we believe that when work is good, life is better and that belief guides all we do. Including how we approach our flexible work model. Simpplr operates with a Hub-Hybrid-Remote model. This model is role-based with exceptions and provides employees with the flexibility that many have told us they want. Hub - 100% work from Simpplr office. Role requires Simpplifier to be in the office full-time. Hybrid - Hybrid work from home and office. Role dictates the ability to work from home, plus benefit from in-person collaboration on a regular basis. Remote - 100% remote. Role can be done anywhere within your country of hire, as long as the requirements of the role are met.

Title: Standard Cell Layout Design About GLOBALFOUNDRIES GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Introduction In this position you will be integrated in our Foundry IP Development team in Bangalore. In close collaboration with other disciplines across our worldwide engineering teams you will be developing layout for Std cell IP which enable our customers to perform product designs at highest quality standards based on Globalfoundries advanced process nodes. Job Responsibilities The development of product grade Standard Cell IP covering the following phases: Layout Design of Standard Cell IPs Layout checks like LVS, DRC, DFM, EMIR Review of Layouts and extend help for other Layout teams Design Kit prep from layout side, verification and validation Layout automation and script support Being a good team player, taking key initiatives for productivity improvements and innovation Sign off and release into dedicated IP validation test chips Specification and documentation Support of silicon bring up and characterization Required Qualifications: Bachelor s degree with 10+ years or master s degree with 8+ years experience in semiconductors / Microelectronics / VLSI engineering. Practical experiences in Standard Cell layout design in one or several of the following areas: Layout design and optimization of Combinational and Sequential Cells for various drive strengths and topology options. Layout design of Power Management Kit cells like Level Shifter, Power Gating, Isolation and Always-on Cells. Layout Architecture design for Ultra High Density and High-Performance Libraries. Layout design of custom cells to meet specific low power or high-speed design requirements. Proficient in handling EDA tools from Synopsis, Mentor and Cadence used for layout design like schematic/layout editor, parasitic extraction tools, DRC, LVS, DFM, EMIR, etc. Basic understanding of fabrication steps and flow. Experience in Testchip integration and analysis will be an added advantage. Preferred Qualifications: Good knowledge of CMOS technology Hands-on knowledge of state-of-the-art standard cell layout flows Programming experience applicable to design flow automation tasks The ability to work within a very dynamic interdisciplinary environment as well as dedicated knowledge of 45/32/28nm and below technology nodes are an advantage. You are flexible, highly motivated and have a team-oriented working style. You have shown the ability to communicate as well as work efficiently in an international multi-disciplinary environment. Strong written and verbal communication skills in English are a must.

Title: Standard Cell Layout Design About GLOBALFOUNDRIES GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Introduction In this position you will be integrated in our Foundry IP Development team in Bangalore. In close collaboration with other disciplines across our worldwide engineering teams you will be developing layout for Std cell IP which enable our customers to perform product designs at highest quality standards based on Globalfoundries advanced process nodes. Job Responsibilities The development of product grade Standard Cell IP covering the following phases: Layout Design of Standard Cell IPs Layout checks like LVS, DRC, DFM, EMIR Review of Layouts and extend help for other Layout teams Design Kit prep from layout side, verification and validation Layout automation and script support Being a good team player, taking key initiatives for productivity improvements and innovation Sign off and release into dedicated IP validation test chips Specification and documentation Support of silicon bring up and characterization Required Qualifications: Bachelor s degree with 10+ years or master s degree with 8+ years experience in semiconductors / Microelectronics / VLSI engineering. Practical experiences in Standard Cell layout design in one or several of the following areas: Layout design and optimization of Combinational and Sequential Cells for various drive strengths and topology options. Layout design of Power Management Kit cells like Level Shifter, Power Gating, Isolation and Always-on Cells. Layout Architecture design for Ultra High Density and High-Performance Libraries. Layout design of custom cells to meet specific low power or high-speed design requirements. Proficient in handling EDA tools from Synopsis, Mentor and Cadence used for layout design like schematic/layout editor, parasitic extraction tools, DRC, LVS, DFM, EMIR, etc. Basic understanding of fabrication steps and flow. Experience in Testchip integration and analysis will be an added advantage. Preferred Qualifications: Good knowledge of CMOS technology Hands-on knowledge of state-of-the-art standard cell layout flows Programming experience applicable to design flow automation tasks The ability to work within a very dynamic interdisciplinary environment as well as dedicated knowledge of 45/32/28nm and below technology nodes are an advantage. You are flexible, highly motivated and have a team-oriented working style. You have shown the ability to communicate as well as work efficiently in an international multi-disciplinary environment. Strong written and verbal communication skills in English are a must. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

" For many organizations, the most valuable asset is their data. Whether source code, product designs, customer records, financial results, or pricing models, every organization has information they don t want to get in the hands of competitors, sold on darknet marketplaces, or exposed publicly. Keeping that data safe has been a challenge, until now. Cyberhaven gives organizations the tools to safeguard their data from theft or misuse. In the process, we ve become the standard for Data Detection and Response (DDR), the category we helped create. We need you to make sure we are shipping a shiny and polished product, free from hitches, glitches, snags, hiccups, crashes, or any other defects. Youll be architecting and developing a safety net that makes it hard for bugs to sneak through. This involves contributing to our modern test automation platform. You wont be afraid to speak up for quality when a deadline is approaching and there is pressure to roll features out. You ll be in close contract with the development and product teams as well as company founders and executives. Exciting stuff is waiting for you! We ve got a pretty cool tech stack over here and making sure everything is tested inside out is not exactly a routine task. There s a rich UI, a microservices-based backend with steep performance and scalability requirements, deep integration with Windows, macOS and Linux, and a diverse set of cloud APIs for integration with SaaS applications. What Youll Do Develop and maintain scalable test frameworks. Perform API testing, UI testing, and end-to-end testing of our AI data lineage engine. Leverage AI for test automation. Build and maintain CI/CD pipelines and test automation systems. Deliver new automated tests across multiple applications and projects. Support release preparation and conduct release testing. Collaborate closely with developers to ensure product specifications are accurately implemented and tested. Who You Are Software engineer with experience in architecting and scaling automated test systems. Proficient in at least one of our primary programming languages: Golang, Python, or TypeScript. (While expertise in all three isn t required, strong skills in at least one are essential.) Passionate about writing clean code and building innovative solutions. A break-it mindset able to anticipate, identify, and prevent subtle bugs and edge cases. Hands-on experience with automated testing of APIs and web applications, including performance testing. Strong knowledge of modern CI/CD practices and tools, especially GitHub Actions. High attention to detail and commitment to maintaining top-tier product quality. Solid understanding of client-server architecture, REST APIs, gRPC, and streaming protocols. Comfortable operating in a fast-paced, agile environment. Energized by working with a dynamic, collaborative team. Excellent written and verbal communication skills in English. Based in India. What you can count on Competitive salary and stock options Excellent benefits such as private health insurance Flexible time off (paid) Career advancement opportunities Creative, knowledgeable and motivated team with alumni from CrowdStrike, Google, Amazon to grow with Fast-paced environment with the ability to make a large impact Cyberhaven is the AI-powered data security company revolutionizing how companies detect and stop the most critical insider threats to their most important data. Weve raised over $250M from leading Silicon Valley investors like Khosla and Redpoint. Cyberhaven is also backed by founders, executives, and security leaders who have built transformational technologies at Crowdstrike, Nutanix, Palo Alto Networks, Meta, Google, Slack, and others. Our company values are: Think Deeply and Use Sound Reasoning Step Up and Take Ownership Continuously Learn and Grow Obsess About Customers Enjoy the Journey Reach for Ambitious Goals Cyberhaven is committed to creating a diverse environment and is an equal opportunity employer. All qualified applicants will receive consideration for

Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Job Description In your new role you will: Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency powerconversion for applications using GaN devices. Design and verify pre-silicon analog/mixed-signal integrated circuitblocks, including incorporating features for testing and quality assurance, and providing support for top-level integration. Assist in defining the requirements for analog and mixed-signalblocks, aligning them with IP Module architecture, and ensuring compliance with requirements through documentation. Estimate effort and planning design work packages to meet project milestones. Provide essential support to physical design engineers, post-silicon verification, production testing, and other critical activities extending beyond the design phase. Your Profile You are best equipped for for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone.

We are looking for test engineers with 4+years of experience for test solutions development in ETS / V93K tester platform for power products. Job Description In your new role you will: Test solutions development in ETS / V93K tester platform for power products. Test hardware development for engineering test hardware and production load boards, probe cards. Work with design, product, application and test engineers on developing test solutions for automotive test coverage . Involve in new products Silicon bring up, yield debug, characterization,product qual activities and release design to production. Your Profile You are best equipped for for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone.

Engineer II What you will do As a member of Johnson Controls India, this position will be part of the IEC global platforming project team that supports the GEC for Global Hardware Platforming program for electronics components and products for different PBUs. He/she will be responsible for JCI product & component level data analysis from the various resources such as PLM, ERP, SharePoint etc. and support the global platforming team. He/she will have to interact with different stakeholders from different departments of JCI such as all engineering teams, procurement teams, platforming SMEs, design & library teams, etc. This person will understand different JCI products/business and their design, manufacturing and documentation best practices & possess the capability to manage changes. He/She will oversee the technical team executing the Global Parts Library (GPL) part creation to ensure process, quality, and schedule are met along with supporting the establishment of the GPL life cycle governance. How you will do it Understand the overall global platforming project objective, the scope of work, different data extraction sources and expectations Managing the Customer with Customer centricity approach Understand and follow the best practices for documentation for data analytics, project deliverables, internal engineering methods and manufacturing conventions Shall manage integrity, availability, and confidentiality of the data stores and databases Will support the platforming team for all Mechanical / Electronics component data collection, verification and analysis Validate various data sources for accuracy and completeness Perform data gathering and data analytics using JCI tools and Microsoft Excel features Provide analysis report either in excel pivot tables & charts or dashboard and/or in PPT Should have a strong understanding of Windchill, PLM tools and Silicon expert Shall have experience in Mechanical, Electronics & Electrical component level analysis Should be able to perform BOM (Mechanical / Electronics) scrubbing and provide lifecycle analysis report Should have good knowledge on component classification and CAD(MCAD / ECAD) Should have good knowledge on CREO, AutoCAD and other mechanical design tools Should have basic knowledge about ERPs (SAP, ECC etc) and PLM ERP interconnections What we look for BE (Mech/ECE/EIE/EEE) - minimum 7+ years of experience in Component Engineering, PLM and MCAD & ECAD 5+ years of experience in working with Hardware and Component Engineering teams and global stakeholders Experienced in using CREO and other Mechanical design tools and Silicon Expert tool Experienced in PLM for the electronic data management system (PTC Windchill) Proficiency with Power BI, Advanced Excel, Word and Power point Knowledge in Electronics product development lifecycle Experienced in handling Mechanical and Electronic components and suggest alternate parts Preferred Strong communication skills and be able to discuss technical topics with individuals and groups with a wide range of technical backgrounds . For more information, please view EEO in the Law. If you are an individual with a disability and you require accommodation during the application process, please visit www. johnsoncontrols. com/tomorrowneedsyou

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IOs and many other leading technologies deployed in our Tegra chips. What you will be doing: You will be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IPs and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit: Architect the testbenches and craft verification environment using UVM methodology Define test plans, tests and verification infrastructure for modules, clusters and system Build efficient and reusable bus functional models, monitors, checkers and scoreboards Implement functional coverage and own verification closure Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust What we need to see: You should be BTech/MTech with 5+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs: CPU verification, Memory controller verification, Interconnect verification High Speed IO verification (UFS/PCIE/XUSB) 10G/1G Ethernet MAC and Switch Bus protocols (AXI/APB) System functions like Safety, Security, Virtualization and sensor processing Experience in the latest verification methodologies like UVM/VMM Exposure to industry standard verification tools for simulation and debug is a requirement Exposure to Formal verification would be excellent Good debugging and analytical skills. Good interpersonal skills, ability to work as an excellent teammate with e xcellent communication skills to collaborate with cross-cultural teams and work in a matrix organization With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If youre creative and independent, with a genuine real passion for technology, we want to hear from you. #LI-Hybrid

Need to work in collaboration with global design teams across sites. Will be responsible for driving innovation in Analog IP designs. Responsible for design of IPs like Switched capacitor circuits , Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools. Should provide technical leadership and mentor junior engineers. Responsible for developing processes and robust design methodology. Help build overall competency in Analog domain. Qualifications Bachelors/ Masters degree in Electrical/ Electronics Engineering with 8+ years of experience in Analog Circuit Design across different technologies. Should have experience in developing analog IPs li

SE NIOR SILICON DESIGN ENGINEER (AECG ASIC PD ENGINEER) THE ROLE : The position will involve working with a very experienced physical design team and is responsible for delivering the physical design of blocks/tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation chips in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 5-7 years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

SMTS SILICON DESIGN ENGINEER (AECG ASIC TFM Lead) T HE ROLE : As a Silicon Design Engineer in the AMD AECG ASIC TFM (Tools Flows Methodology) team, you will work with design experts to come up with the best implementation methodologies/flows and work on development and support of the BE flows. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. K EY RESPONSIBLITIES : Define and drive key Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Provide technical support to other teams P REFERRED EXPERIENCE : 12+ years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4

Job Responsibilities Conduct ESD/LUP research and experiments to investigate how to design-in the best ESD and latch-up design and layout solutions that minimize product defects due to electrostatic discharge (ESD) or latch-up (LUP) events. Design ESD test structures to fully evaluate the high current and voltage properties of the ESD IO, input or power clamps circuits. Assess the fundamental ESD properties of each type of ESD circuit elements, from active diffusions to BEOL metal layers, by wafer level transmission line pulse (TLP and vf-TLP) measurements to develop on-chip protection from ESD and or LUP events. Analyze ESD and latch-up (LUP) test structure data and generate ESD/LUP design rules and Guidelines. Develop and expand the ESD and latch-up circuit models based of the measured ESD data. Supervise and arrange full-chip ESD design review process (Schematic and Pathfinder analysis) for each design prior to tapeout. Apply Pathfinder type ESD current density and resistance verification tool to ensure full die layout meet all ESD design rule requirements. Manage and coordinate first silicon ESD and latch-up design validation tests and perform root cause ESD and LUP analysis, as necessary, to ensure that product meets Micron s minimum qualification requirements. Continually improve product design and reliability by introducing innovative ESD designs. Successful candidates for this position will have: A strong knowledge of advanced semiconductor device physics, including deep submicron CMOS devices. A good understanding of state-of-the-art CMOS process technology and electrical circuit analysis. Experience in Cadence design tools for design, layout, and verification tools. Hands-on experience in ESD characterization analysis using wafer level transmission line pulse (TLP) test equipment. Experience waveform generators, oscilloscopes, source/measure units, Agilent and/or Keithley parametric analyzers/testers, and impedance analyzers. Familiarity with ESD analysis tools like PERC or PathFinder or similar software tools. Strong data analysis skills are required to extract the high current ESD properties and develop ESD/Latch-up design rules for critical ESD circuits. Strong oral and written communication skills are required to provide ESD/LUP technical leadership with diverse worldwide teams in Design, Product Engineering, R&D characterization, and Quality Assurance teams. Minimum Qualifications: A BS Electrical Engineering, Microelectronics, or related discipline with 3-5 years of experience, OR A MS in Electrical Engineering, Microelectronics, or related discipline with 2 years of experience, OR A Ph.D. in Electrical Engineering, Microelectronics, or related discipline. Preferred Qualifications: An MS/Ph.D. in Electrical Engineering, Microelectronics, or related discipline, with 8+ years of experience. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidates true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

About the job At BairesDev , we ve been leading the way in technology projects for over 15 years. We deliver cutting-edge solutions to giants like Google and the most innovative startups in Silicon Valley. Our diverse 4,000+ team, composed of the world s Top 1% of tech talent, works remotely on roles that drive significant impact worldwide. When you apply for this position, you re taking the first step in a process that goes beyond the ordinary. We aim to align your passions and skills with our vacancies, setting you on a path to exceptional career development and success. IT Recruiter at BairesDev We are looking for an IT Recruiter who will be in charge of the end-to-end recruitment process. The Recruiter will conduct the interviews and is responsible for understanding the profiles of the candidates and engaging them in our process. We are looking for someone with great soft skills to work with candidates, who is interested in talking with candidates, and who pays close attention to details. What You ll Do: Review the candidates online information to assess their general fit. Contact candidates through phone calls, Zoom, LinkedIn, or mail to validate their interest and motivate them to participate in our process. Interview candidates to assess their qualifications by validating their profile, experience, interests, commitment, and logic and common sense questions. Manage the end-to-end recruitment process and keep the system records updated. What we are looking for: 4+ years of experience in end-to-end recruiting processes. Strong interpersonal and communication skills. Proficiency in using recruitment tools and applicant tracking systems. Ability to build rapport with candidates from diverse backgrounds. Strong attention to detail and organizational skills. Mandatory: IT recruiting experience Must be located in India. Advanced level of English. How we make your work (and your life) easier: 100% remote. Excellent compensation in USD. Hardware setup for you to work from home. Flexible hours make your schedule. Paid parental leave, vacation, & national holidays. Innovative and multicultural work environment. Collaborate and learn from the global Top 1% of talent in each area. Supportive environment with mentorship, promotions, skill development, and diverse growth opportunities. Join a global team where your unique talents can truly thrive!

Roles and Responsibility 3+ years to 10 yrs design experience Experience with owning chip level DFT and Post Silicon debug / analysis Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification. Must have experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation. Understanding generation of functional patterns for ATE Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc) Design experience in MBIST / LBIST is an added advantage. Good understanding of constraints development for Physical Design Implementation / Static Timing Analysis. Preferred Skills/ Experience Experience with TCL / Perl is preferred. Understanding of IC design with Analog circuits and it s design cycles is an added advantage. Effective communication skills to interact with all stakeholders. Team and People Skills: The candidate should have good people skills to work closely with the systems, analog, layout and test team Must be highly focused and remain committed to obtaining closure on project goals

Forza Silicon is a Business Unit in the Materials Analysis Division of AMETEK, Inc. Forza s history begins at the formation of the CMOS imaging industry where company co-founders, Barmak Mansoorian and Daniel Van Blerkom were a critical part of the Photobit team. Along with Photobit Co-founder, Dr. Eric Fossum, and many others, the team pioneered the development of CMOS imaging technology. Founded in 2001, Forza Silicon has established itself as an innovator and industry leader in the field of mixed-signal IC and CMOS imaging designs that have set the standard of the possible. Primarily through long standing customer relationships and partner referrals, Forza Silicon has grown to where today the company employs one of the industry s largest and most experienced independent CMOS imaging engineering teams. To learn more about Forza Silicon, please go to www.forzasilicon.com Postition Summary: This position will report to the engineering manager and assume engineering responsibility to plan, manage, and oversee detailed sensor design and analysis for custom CMOS image sensors. This position will involve all phases of a design project, including specification and architectural design, detailed circuit design, simulation, layout, verification, and design bring-up and test. The candidate will also be expected to interface extensively with customers and external vendors to communicate specifications, design status, technical details, etc. Primary Responsibilities: Oversee all phases of sensor design: specification, design and tapeout, test, transition to product. Work with customers to understand sensor requirements, translate requirements to detailed specifications, and develop sensor architecture to ensure specifications are met. Work collaboratively with a team of engineers to execute design according to technical specification and schedule in an efficient manner. Perform detailed circuit analysis, design, simulation, layout, verification of mixed-mode circuits Interface with foundry partners to understand process details in support of design implementation, manage pixel design and performance, and oversee tapeout and fabrication. Work with test engineers to facilitate development of test hardware, test plans, and oversee chip bring-up and characterization efforts and results. Position Requirements B.S. in Electrical Engineering (M.S./Ph.D. preferred) 4-7 years of experience in practical analog/mixed signal design for image sensors or other relevant areas. Expert at transistor level circuit design, simulation, verification using modern EDA tools from Cadence, Siemens, Synopsys, etc. Knowledgeable in ADC architectures for image sensor readoutRelevant experience with bandgaps, bias, op-amps, switched-cap circuits, LDOs, PLL, SERDES, high-speed TX, general feedback, and compensation techniques. Expert in noise analysis, transistor/capacitor matching and sources of errors in analog integrated circuits. Experienced in all stages of mixed-signal chip design (preferably in the context of image sensors) flow including DFT, timing analysis, top chip integration and tapeout, and silicon bring up. Experience leading a design team is highly preferred. Excellent communication skills are required.

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

Job Description: Minimum of ten years of hands-on Test Development experience (DFT, EDA tools, etc..) Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization Stakeholder influencing and people skills must be excellent. Needs to be able to set aggressive goals and manage risks effectively Must have a thorough understanding of tool development methodology. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. MS or Ph.D. Engineering degree (EE or equivalent) with 3-10 years semiconductor industry experience.

Experience : 3 to 10 Years Qualification : Bachelors or Masters (Electronics and Communication Engineering or equivalent) Job Description: As an Emulation Engineer, youll be an integral part of a dynamic team dedicated to creating cutting-edge ASIC solutions for High-Performance Computing (HPC) systems. Your role will involve defining the validation strategy leading to functional sign-off for these high-performance computing designs. Key functions and responsibilities: Proficient in various emulation technologies, including simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods. Familiarity with tools such as Palladium, Protium, Veloce, or Zebu. Good Knowledge of SystemC/C/C++ and UVM/SV verification languages Experience with SystemVerilog and C++ for modelling RTL components and transactors. Ability to develop C/C++/SystemC/SV tests in HDL-HVL (Hardware Description Language-Hardware Verification Language) Co-emulation platforms. Understanding of compilation and build flow. Skilled at building images from scratch, making necessary design modifications to adapt to emulation. Work closely with verification teams to define and implement comprehensive pre and post silicon test plans. Interface effectively with design, verification, validation, and software development teams to understand their needs from an emulation perspective. Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip systems). Balancing performance and ease of debug. Proficient in post-silicon bring-up, debugging, and issue reproduction on emulators. Familiarity with Python and TCL scripting languages. Exposure to domains such as PCIe, CXL, DDR, Flash, Memory, USB, and CPU. Strong communication and collaboration skills to work effectively with cross-functional teams and domain experts. Successfully manage multiple design releases and provide support for debugging customer issues.

SMTS SILICON DESIGN ENGINEER PREFERRED EXPERIENCE: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 13+ years of relevant experience Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges Circuit timing/STA, and practical experience with tools Working knowledge of C; embedded experience a plus Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards Been exposed to memory controller and PHYs from different IP vendors Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software Version control systems such as Perforce, ICManage or Git Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

We are on a mission to power the data productivity of our customers and the world, by helping teams get data business ready, faster. Our technology allows customers to load, transform, sync and orchestrate their data. We are looking for passionate, high-integrity individuals to help us scale up our growing business. Together, we can make a dent in the universe bigger than ourselves. Role Purpose Matillion is a fast paced hyper-scale software development company. You will be based in India but working with colleagues globally specifically across the US, the UK and in Hyderabad. The Enterprise data team is responsible for producing Matillions reporting metrics and KPIs. We work closely with Finance colleagues, the product team and Go To Market to interpret the data that we have and provide actionable insight across the business. The purpose of this role Is to Increase the value of strategic information from the data warehouse, Salesforce, Thoughtspot, and DPC Hub by providing a context for the data aiding analysts to make more effective decisions Reduce training costs by documenting data context, history and origin Reduce time-to-value of data analytics by assisting analysts find the information they need Improve communication between data users in data engineering, Go-To-Market, Product and Finance Identify and reduce redundant data and processes. What will you be doing? Create and maintain meta-data for our core data assets Manage the metadata repository, Confluence Define and implement review schedule for metadata Agree metadata with relevant stakeholders Define data quality criteria for each data asset Build data quality report for each data asset Build a data quality report to report on overall data quality Working with our AI tools, specifically Gemini & MAIA to automate and reduce the effort needed to maintain our data artefacts Identify data to be archived/delete based on the defined retention policy What are we looking for? Experience of Netsuite and Salesforce Knowledge of Kimbal modelling methodology Knowledge of Snowflake and Thoughtspot Ability to work with business stakeholders Ability to work with technical stakeholders Excellent stakeholder management skills Ability to negotiate with stakeholders with different objectives Ability to document work clearly and concisely Experience of working with remote teams.

MTS SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 8-12 years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com . What Youll do Lead and execute complex data science initiatives that support high-impact business decisions. Responsible for the development, deployment, and communication of advanced analytical models. Provides technical guidance to junior data scientists and partners closely with cross-functional teams to drive data-driven outcomes Responsibilities Designs and implements advanced statistical and machine learning models to solve complex business problems. Leads full-cycle analytics projects, including problem definition, data exploration, model development, evaluation, and deployment. Collaborates with stakeholders to align data science solutions with business goals and priorities. Provides technical mentorship to junior team members and contributes to knowledge sharing across the team. Translates complex modeling outputs into actionable insights and presents findings to senior leadership. Stays current on industry best practices and emerging trends in AI, machine learning, and data science tools. Contributes to continuous improvement in analytical workflows, code standards, and data governance. Applies sound judgment to navigate ambiguous problems and propose scalable solutions. Performs other duties as required in support of the data science team and organizational goals. Required Qualification and skills Bachelor s degree in Data Science, Computer Science, Statistics, Mathematics, or a related field; Master s preferred. Minimum of 4 years of experience in data science, machine learning, or advanced analytics. Advanced proficiency in Python or R, SQL, and machine learning libraries (e.g., scikit-learn, TensorFlow). Strong grasp of statistical analysis, experimental design, and model evaluation techniques. Excellent written and verbal communication skills, with the ability to influence both technical and non-technical stakeholders. Demonstrated experience in leading complex data projects and driving measurable business outcomes. Experience with cloud-based data platforms (e.g., AWS, GCP, Azure) and MLOps practices is a plus. Benefits & Perks: Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: In this role, the Engineer will apply and lead Broadcoms proven design methodology and milestone flow to meet Broadcoms rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification. Responsibilities include, but not limited to: Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt. Implement timing and functional ECO P&R, Extraction, Physical verification, work towards STA closure Build automation flows wherever needed/adapt to existing flows for re-use Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO Needs to be automation savvy with high expertise in one of the programming languages used in the industry Clearly know requisites for executing his/her job and lead by example Bring tangible improvement in TAT with better quality Minimum Qualifications: MSEE/MSCS 3+ years (BSEE/BSCS 5+ years) A deep understanding of backend digital design flow Proficient in timing constraints, physical constraints Proficient in handling EDA tools across floorplan / partition / placement / cts / route stages for SoC TOP. Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk Proficiency in Tcl and Perl Excellent analytical skills Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone .

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: In this role, the Engineer will apply and lead Broadcoms proven design methodology and milestone flow to meet Broadcoms rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification. Responsibilities include, but not limited to: Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt. Implement timing and functional ECO P&R, Extraction, Physical verification, work towards STA closure Build automation flows wherever needed/adapt to existing flows for re-use Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO Needs to be automation savvy with high expertise in one of the programming languages used in the industry Clearly know requisites for executing his/her job and lead by example Bring tangible improvement in TAT with better quality Minimum Qualifications: MSEE/MSCS 3+ years (BSEE/BSCS 5+ years) A deep understanding of backend digital design flow Proficient in timing constraints, physical constraints Proficient in handling EDA tools across floorplan / partition / placement / cts / route stages for SoC TOP. Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk Proficiency in Tcl and Perl Excellent analytical skills Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

SE NIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the physical integration and verification team , you will work closely with the physical design implementation, IP teams and fab contacts to achieve quality tapeout and first pass silicon success. THE PERSON: A successful candidate will work on block level and SoC physical integration, verification and tapeout with physical design engineers. The candidate is expected to be detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work with PD team on subsystem and block level physical verification and signoff Work closely with physical design implementation and signoff team to achieve faster TAT Work closely with CAD team to come up with new flows and methodologies in the physical verification domain PREFERRED SKILLSET: 6+ years of relevant experience Sound knowledge of physical verification and design flows Hands on experience on industry standard tools such as Calibre and ICV Sound understanding for DRC/LVS decks. Should be able to make updates as required. Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .