Reviewing Die, package, and PCB physical layout designs Modeling, simulating, and verifying high-speed interface performance against specifications Participating in the improvement of SI/PI methodology flows Collaborating and networking with other teams on task-oriented projects Independently driving SI/PI research and development activities Ensuring designs meet stringent performance, power, and size requirements The Impact You Will Have: Enhance the performance and reliability of high-speed interfaces Contribute to the development of cutting-edge technology in chip design Improve SI/PI methodology flows, increasing efficiency and accuracy Foster collaboration and innovation across globally distributed teams Drive research and development initiatives to stay ahead in the industry Support Synopsys mission to lead in the Era of Pervasive Intelligence What You ll Need: Bachelors or Masters degree in Electrical or Electronics Engineering Minimum of 5 years of relevant experience Proficient in Transmission line theory and time/frequency-domain analysis Experienced with SPICE and familiar with 3D field solvers Conversant with working of DDR and PCIe/Ethernet interfaces Good verbal and written English communication skills Experience in scripting languages such as Python and TCL is a plus Familiarity with both Windows and Linux operating system

We are seeking a highly motivated Product Engineer who is passionate about advancing technology and solving complex design challenges. You are innovative, dependable, and have a strong technical background in transistor-level analysis. With a minimum of 5 years of hands-on experience, you possess exceptional expertise in debugging circuit-level issues for SRAM, RF, ROM memories, and Standard Cells. You have a deep understanding of static timing concepts and CMOS engineering fundamentals, coupled with proficiency in TCL or other scripting languages. Your excellent communication and social skills enable you to collaborate effectively with cross-functional teams, including R&D, Field AEs, Sales, and Marketing. You thrive in a dynamic environment, driving new products and features that exceed customer expectations and contribute to the success of Synopsys. What You ll Be Doing: Drive new products and new product features that exceed customer needs. Work with R&D to enable timely implementation of new products and features, and important bug fixes. Provide consultation to prospective users and/or product capability assessment and validation. Provide tool trainings to customers and Field AEs. Provide technical expertise to sales staff through sales presentations and product demonstrations. Assist the sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications for the development and implementation of customer applications/solutions. The Impact You Will Have: Influence technology and solution roadmaps through collaboration with R&D. Ensure overall consistency of end-to-end design and analysis flow to meet customer needs. Drive new tool evaluations and help customers with the adoption and continuous usage of our tools. Enable Chip Design customers to achieve optimal Timing, Power, and Characterization goals. Enhance predictability and productivity for designers through advanced tool features. Identify and resolve design issues early-on, minimizing costly late-stage silicon problems. What You ll Need: BS degree in Electrical Engineering or related field. Minimum of 5 years of recent hands-on experience in transistor-level analysis. Expertise in debugging circuit-level issues for SRAM, RF, ROM memories, and Standard Cells. Proficiency in static timing concepts and CMOS engineering fundamentals. Knowledge of TCL and/or other scripting languages. Who You Are: Innovative and motivated. Dependable and detail-oriented. Excellent communicator and collaborator. Proactive problem solver. Adaptable and eager to learn

Designing and developing high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, clock cells, and other complex circuits. Creating and refining environments for post-layout netlist extraction. Applying your expertise in CMOS device characteristics, design rules, latch-up, and electromigration to ensure robust designs. Optimizing digital circuits for better performance, power, and area (PPA). Performing statistical and variation analysis to enhance the reliability of designs. Collaborating with cross-functional teams to integrate designs into larger systems. The Impact You Will Have: Contributing to the creation of cutting-edge semiconductor technologies that power a wide range of applications. Enhancing the performance and efficiency of standard cell circuits, impacting the overall quality of our products. Driving innovation in power optimization and clock cell design, leading to more energy-efficient solutions. Improving the reliability and robustness of our designs through meticulous analysis and optimization. Collaborating on projects that shape the future of technology and influence industry standards. Leveraging your skills to solve complex engineering challenges, contributing to the success of Synopsys. What You ll Need: Experience in Standard Cell Circuit design of high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, and clock cells. Strong knowledge and hands-on experience in developing environments and extracting post-layout netlists. Good understanding of CMOS device characteristics, design rules, latch-up, and electromigration. Proficiency in digital circuit design and optimization for better PPA. Hands-on experience in statistical/variation analysis

Designing, implementing, and optimizing CI/CD pipelines for cloud and hybrid environments. Integrating AI-driven pipeline automation for self-healing deployments and predictive troubleshooting. Leveraging GitOps (ArgoCD, Flux, Tekton) for declarative infrastructure management. Implementing progressive delivery strategies (Canary, Blue-Green, Feature Flags). Containerizing applications using Docker & Kubernetes (EKS, AKS, GKE, OpenShift, or on-prem clusters). Optimizing service orchestration and networking with service meshes (Istio, Linkerd, Consul). Implementing AI-enhanced observability for containerized services using AIOps-based monitoring. Automating provisioning with Terraform, CloudFormation, Pulumi, or CDK. Supporting and optimizing distributed computing workloads, including Apache Spark, Flink, or Ray. Using GenAI-driven copilots for DevOps automation, including scripting, deployment verification, and infra recommendations. The Impact You Will Have: Enhancing the efficiency and reliability of CI/CD pipelines and deployments. Driving the adoption of AI-driven automation to reduce downtime and improve system resilience. Enabling seamless application portability across on-prem and cloud environments. Implementing advanced observability solutions to proactively detect and resolve issues. Optimizing resource allocation and job scheduling for distributed processing workloads. Contributing to the development of intelligent DevOps solutions that support both traditional and AI-driven workloads. What You ll Need: 5+ years of experience in DevOps, Cloud Engineering, or SRE. Hands-on expertise with CI/CD pipelines (Jenkins, GitHub Actions, GitLab CI, ArgoCD, Tekton, etc.). Strong experience with Kubernetes, container orchestration, and service meshes. Proficiency in Terraform, CloudFormation, Pulumi, or Infrastructure as Code (IaC) tools. Experience working in hybrid cloud environments (AWS, Azure, GCP, on-prem). Strong scripting skills in Python, Bash, or Go. Knowledge of distributed data processing frameworks (Spark, Flink, Ray, or similar)

* Responsible for functional verification involving coherent and non-coherent IP designs. * Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. * Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * Developing verification plans and driving functional coverage-driven verification closure of real designs. * Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: * Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. * Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. * Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. * Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. * Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. * Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: * B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. * Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * You will be responsible for functional verification involving coherent and non-coherent IP designs. * Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: * Excellent problem-solving, debugging, and analytical skills. * Strong programming skills and familiarity with object-oriented programming concepts. * Creative and innovative mindset. * Excellent verbal and written communication skills. * A collaborative team player with a passion for functional verification. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Responsible for PCIe/CXL next-gen Controller IP features Customer pre/post sales PCIe/CXL protocol related communication Utilizing advanced design methodologies and tools to achieve high-quality results Mentoring and guiding other engineers, promoting best practices, and fostering a culture of continuous improvement Communicating with internal and external stakeholders to align on project goals and deliverables. What You ll Need: Extensive experience in digital ASIC design and physical aware synthesis. In-depth knowledge of PCIe, CXL , AXI, CHI and similar IO protocols. Proficiency in advanced digital design tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 20+ years in relevant domain. Who You Are: A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity.

"> Search Jobs Find Jobs For Where Search Jobs Technical Writer Hyderabad, Telangana, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 10602 Date posted 04/17/2025 Share this job Email LinkedIn X Facebook Alternate Job Titles: Senior Technical Writer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performan ce silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: Energetic, experienced, and organized, you are a writer who thrives in a vibrant environment and is passionate about cutting-edge technology. You have a knack for turning complex technical information into clear, concise, and user-friendly documentation. With a strong background in technical writing within the software or hardware industry, you bring a blend of creativity and precision to your work. You are a team player who can also work independently, and you take pride in delivering high-quality content on time. Your excellent communication and interpersonal skills enable you to collaborate effectively with engineers and other stakeholders. You are always eager to learn and adapt to new technologies, ensuring that your documentation remains relevant and up-to-date. If you care about doing a good job, about details, and about contributing to a dynamic team, Synopsys is the place for you. What You ll Be Doing: Planning, organizing, writing, and editing a variety of customer documentation. Collaborating with engineers to understand product functionalitie s and features. Creating user manuals, reference guides, and online help content in various formats. Ensuring documentation is accurate, clear, and comprehensive. Maintaining and updating existing documentation to reflect product updates. Utilizing authoring tools such as FrameMaker and Oxygen to produce high-quality content. The Impact You Will Have: Empower customers to effectively use and optimize Synopsys products. Enhance user experience through clear and accessible documentation. Support product adoption and customer satisfaction. Contribute to the success of product releases with timely and accurate documentation. Facilitate better communication and understanding between customers and the engineering team. Help maintain Synopsys reputation as a leader in semiconductor IP solutions. What You ll Need: Degree or masters in electronics, science, hardware, computing, software, physics, mathematics, or engineering disciplines. Other technical disciplines considered. 3-5 years of technical writing experience in the software or hardware industry. Excellent problem-solvin g skills with strong logical reasoning. Proficiency with authoring tools such as FrameMaker and Oxygen. Excellent English writing and speaking skills. Who You Are: Excellent communication and interpersonal skills. Energetic and capable of learning new technologies as necessary. Team player with the ability to work independently. Detail-oriente d and committed to delivering high-quality work. Proactive and able to take ownership of projects with minimal supervision. The Team You ll Be A Part Of: You will be part of a dynamic and experienced Technical Publications team that works closely with world-class engineers to create essential customer documentation. Our team is committed to empowering customers worldwide with comprehensive and user-friendly content that enhances their experience with Synopsys products. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

We are seeking a Senior FPGA Verification Engineer to join the Ericsson Silicon organization. In this key role, you will provide strategic leadership to a team of dedicated engineers focused on developing world-class Radio and RAN Compute products. You will lead the FPGA verification team in defining, implementing, and optimizing verification strategies and environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, you'll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking What you will do Lead the definition of advanced verification requirements and strategies for FPGA and/or ASIC designs based on functional specifications and Ericsson development processes. Architect and implement comprehensive verification environments and test cases to execute verification plans, ensuring high-quality deliverables. Analyze and optimize functional and code coverage metrics, driving towards completion targets and continuous improvement. Debug RTL in collaboration with designers, Collaborate with hardware, software, systems, and integration teams to understand overall product requirements and drive strategic and efficient solutions. Champion the continuous improvement of products, tools, and processes, contributing thought leadership and innovative ideas. Produce and oversee the generation of comprehensive verification documentation, ensuring clarity and precision including test procedures and results documentation. Devise test plans that cover functional verification and on target lab verification. Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA/ASIC verification, including leadership roles. Exceptional knowledge of UVM and SystemVerilog Proven ability to architect and create RTL testbenches from scratch, demonstrating advanced technical skills. Strong knowledge of object-oriented programming and embedded software design and testing. Expertise with modern FPGA device families and tools Experience with scripting languages such as Python, Tcl, shell scripting, etc An analytical and strategic approach with a results-oriented mindset and the ability to deliver under pressure. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A masters degree in Electrical or Computer Engineering or equivalent

We are seeking a seasoned SoC Architect with expertise or significant interest in System Architecture. You have had significant success driving architecture, product roadmaps and product requirements. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead architecture teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements Knowledge sharing and other contributions to Platform & System Architecture As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels Excellent communication, management, and presentation skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: bachelors or masters degree in related discipline preferred

We are looking for an adaptive, self-motivative EMIR engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The EMIR team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Good understanding of IR/Power-Domain-Network signoff at SOC & block level Experience in RHSC tool Good at scripting python/perl/tcl Must have knowledge of Physical Implementation (Synthesis and Place&Route) Effective communication ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering with 5+Yrs of exp.

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

About You: You are a talented and dedicated Senior Layout Design Engineer specializing in analog and mixed-signal (A&MS) integrated circuits. You excel in collaborative environments, working seamlessly with cross-functional teams to drive technological innovation. Your meticulous attention to detail and unwavering commitment to quality are hallmarks of your work. You are constantly striving to enhance layout design methodologies and best practices, utilizing your profound knowledge of semiconductor process technologies and industry-standard EDA tools. Your exceptional problem-solving abilities, effective communication, and strong teamwork make you an indispensable asset. What You ll Be Doing: Develop and implement layout designs for A&MS integrated circuits. Optimize layouts using industry-standard EDA tools. Perform physical verification and design rule checks. Participate in Layout reviews and provide feedback. Collaborate with circuit designers on specifications and constraints. Enhance layout design methodologies and best practices. Stay updated with industry trends in A&MS layout design. The Impact You Will Have: Ensure high quality and performance of A&MS integrated circuits. Drive innovation with cutting-edge layout designs. Improve manufacturability and reliability through meticulous design. Contribute valuable feedback during design reviews. Foster continuous improvement in design methodologies. Mentor junior engineers by sharing your expertise.

About us Headquartered in the Silicon Valley with offices in London, Hyderabad and Singapore, Accellor is a Microsoft Gold Partner and a premier Salesforce Partner that uses best-of-breed cloud technology to deliver superior customer engagement and business effectiveness for clients. We bring a deep understanding of Financial, Retail, High Tech, Healthcare, and Retail industries, rolling out end-to-end implementation of salesforce.com and powerful third-party apps. We also build products that are sold on the AppExchange and used by both boutique businesses and Fortune 500 companies. Majority of our team members based at Hyderabad, delivering best of breed cloud solutions to customers in the US, UK and APAC region. We ve created an atmosphere that encourages curiosity, constant learning, and persistence. We encourage our employees to grow and explore their interests. We cultivate an environment of collaboration, autonomy and delegation - we know our people have a strong work ethic and a sense of pride and ownership over their work. They are passionate, eager, and motivated - focused on building the perfect solution but never losing sight of the bigger picture. Job Description Work with Sales and Marketing teams and Sales directors to ideate and assemble business proposal for software product development and related services. Prepare professional response to RFP/RFI s. Be part of the pre-sales proposal lifecycle or bid management. Create high-quality client facing presentations and documents (in MSOffice) related to software products, technology services. Prowess in English language will be required to articulate solutions and proposed software success roadmaps. Work with technical leads and product designers to understand and articulate business solutions. The job may require flexibility in work hours to collaborate with stakeholders in different time-zones of USA or UK. Must to Have:- Must have excellent presentation and technical documentation skills (suggestively on Microsoft O365 tools). Must have excellent written and verbal English language skills. US experience (remotely supporting is fine). Services/consulting experience. Cloud/AI experience is mandatory. Must be qualified for customer facing. Good to Have:- Experience developing supporting pre-sales and marketing is desirable. Thorough understanding of the Software Development Lifecycle (e.g. Requirements, Design, Development, Testing). Excellent interpersonal, research, and communication skills. Technical person converted to presales is preferred but not mandatory. Midsize company experience would be a plus. Educational Qualifications Must be a Graduate or post-graduate. MBA would be a plus. Exciting Projects: We focus on industries like High-Tech, communication, media, healthcare, retail and telecom. Our customer list is full of fantastic global brands and leaders who love what we build for them. Collaborative Environment: You Can expand your skills by collaborating with a diverse team of highly talented people in an open, laidback environment or even abroad in one of our global canters. Work-Life Balance: Accellor prioritizes work-life balance, which is why we offer flexible work schedules, opportunities to work from home, and paid time off and holidays. Professional Development: Our dedicated Learning Development team regularly organizes Communication skills training, Stress Management program, professional certifications, and technical and soft skill trainings. Excellent Benefits: We provide our employees with competitive salaries, family medical insurance, Personal Accident Insurance, Periodic health awareness program, extended maternity leave, annual performance bonuses, and referral bonuses. Disclaimer Accellor is proud to be an equal opportunity employer. We do not discriminate in hiring or any employment decision based on race, color, religion, national origin, age, sex (including pregnancy, childbirth, or related medical conditions), marital status, ancestry, physical or mental disability, genetic information, veteran status, gender identity or expression, sexual orientation, or other applicable legally protected characteristic

Roles and Responsibility 5 years to 15 yrsdesign experience. Experience withowning chip level DFT and Post Silicon debug / analysis. Understanding of DFTarchitectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISRetc.), scan chain insertion and verification. Must have experiencegenerating scan patterns and coverage statistics for various fault models likestuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, patterngeneration for Memories(E-fuse etc.). Experience debugging tester failures ofscan patterns, diagnosis and pattern re-generation. Understandinggeneration of functional patterns for ATE Knowledge of atleast any one of an industry standard DFT tools (Cadence Modus, SynopsysTetramax, Mentor Tessent Tools, etc) Design experience inMBIST / LBIST is an added advantage. Good understandingof constraints development for Physical Design Implementation / Static TimingAnalysis. Responsibilities: Must have experience generating scan patterns andcoverage statistics for various fault models like stuck at(Nominal and VBOX),IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E- fuseetc.). Experience debugging tester failures of scan patterns, diagnosis andpattern re-generation. Understanding generation of functional patterns forATE Knowledge of at least any one of an industrystandard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools,etc) Design experience in MBIST / LBIST is an addedadvantage. Good understanding of constraints development forPhysical Design Implementation / Static Timing Analysis. Desired Skills: Preferred Skills/ Experience Experience with TCL / Perl is preferred. Understanding of IC design with Analog circuits andit s design cycles is an added advantage. Effective communication skills to interact with allstakeholders. Team and People Skills: The candidate should havegood people skills to work closely with the systems, analog, layout and testteam Must be highly focused and remain committed toobtaining closure on project goals

As a member of the Strategic Silicon Solution Group Full Chip Low Power Design and Signoff team, you will help bring to life cutting-edge designs. You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success. THE PERSON: A successful candidate should have minimum 8 to 15 years approximate work experience. He will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power design/signoff, and mentor/coach/guide Design Engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Expertise in Full Chip Power Delivery Network Design, Implementation and Signoff Must have good understanding of RDL & Power grid design. Must know the NPV Static, Dynamic & SEM Run. Must have good experience of Vectored dynamic, CPM & Ramp up time analysis and current analysis. Must have experience on Full chip, Sub-system level & tile/block/partition level EMIR analysis and signoff Should have good knowledge of package level EMIR analysis. Expertise in low power design and implementation such as clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption. Should have good knowledge on simulation of special cell s with target power analysis. Should possess good knowledge of Power switch insertion, Secondary PG design towards improvising PPA. Mentor/coach/guide design engineers to achieve the project goal. Should have hands on experience on tools like Redhawk-SC, ICC2 & Prime Time or equivalent industry standard tools. Should have good scripting experience in Shell, Python, Perl, TCL, UNIX PREFERRED EXPERIENCE: Understanding of ICC2 or Fusion Compiler Physical Design flows/methodologies or equivalent tools. Expertise on tool expected. Experience in TCL/Python and other languages needed. Should be strong in scripting and decode/debug old existing scripts. Experience with RHSC, PTPX, ICC2, Fusion Compiler Experience with mentoring a team on lower tech node (5/3nm) projects on PDN (EMIR) Experience in Full Chip/Sub-system level Physical Verification including DRC, LVS, DFM, ESD, High voltage checks etc, ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer/Electronics/Electrical Engineering with 5+Yrs of exp

Contribute to the development of new memory products through the design optimization of memory circuits (such as pitched cells, datapath , pumps & regulators, I/O, Controller ) . Understand design specification at the chip level and breakdown of functions into circuit sub components , in the analog and/or digital domain. Create schematic description of circuit functions at the schematic level or behavioral level, using industry available capture tools, such as Cadence Composer and the Verilog behavioral language. Verify the circuit functionality in the analog and/or logic domain, using industry available simulators such as Hspice , Hsim for the electrical analysis and NC-Verilog for the digital design verification Provide design documentation (schematic, behavioral, simulation) at the circuit level and chip level, including lesson learned update. Provide clear directions and documentation and interact with layout team to ensure that the block layout is fully compliant with designer s expectations in the terms of performances . Cooperates with PE for silicon debug and verification Additional tasks may include new circuit conception and design.

Pre-silicon design simulations, and post silicon validation for the product. Perform simulation to silicon matching activities by running simulation and microprobing critical circuits to capture waveforms to compare back to simulations and analyze the results for improvement of the design. Work closely with the Design Teams on forward looking design features, innovations and circuit development activities. The Design characterization engineer will be responsible for performing product characterization and debugging (using Bench test equipment, microprobe, ATE, etc.) Determine design implications on manufacturability, test product features and debug early silicon and verify design features. Qualifications and Skills include: The preferred candidate needs to have Design / Product engineering background including circuit design, product characterization and debugging on Memory Working knowledge in the following areas: Circuit / logic design, Semiconductor device physics is a plus. Working knowledge of the following area is a plus: Bench test equipment (O-Scope, Logic Analyzers). Experience with Teradyne Magnum Test program, C++, Python, Statistics. Effective oral and written communication with strong analytical, problem solving, and project management skills

Identify growth opportunities within product categories based on market trends, consumer behavior, and competitive analysis. Develop and execute strategies for product positioning, pricing, and promotional activities that maximize growth and profitability. Collaborate with cross-functional teams including marketing, sales, and content to drive category initiatives and ensure alignment with overall business goals. Analyze performance metrics and customer feedback to inform category development and enhance the customer experience. Manage relationships with external partners and vendors to expand product offerings and improve market presence. Monitor industry trends and competitor activities to identify potential risks and opportunities for market positioning. Lead and mentor a team by fostering a collaborative environment and driving results-oriented performance. Key Responsibilities: Work closely with the core team to generate new course ideas and enhancements to existing products. This is done with the goal of revenue generation or conversion improveme

Wheelson Technologies is looking for Pre-Post Silicon Validation Engineer to join our dynamic team and embark on a rewarding career journey. A Validation Engineer is responsible for planning, executing, and documenting validation activities to ensure that processes, systems, and products meet specified requirements and comply with regulatory standards This role involves collaboration with cross-functional teams, adherence to quality protocols, and maintaining compliance with industry regulations Key Responsibilities:Validation Planning:Develop and implement validation master plans, protocols, and procedures Define validation strategies based on project requirements and regulatory guidelines Protocol Development:Create, review, and approve validation protocols, including Installation Qualification (IQ), Operational Qualification (OQ), and Performance Qualification (PQ) Ensure that validation protocols are aligned with industry standards and regulatory requirements Execution of Validation Activities:Conduct validation testing according to approved protocols Collaborate with cross-functional teams to execute validation activities, including equipment, process, and cleaning validation Investigate and troubleshoot any deviations or issues encountered during validation Data Analysis and Documentation:Collect and analyze validation data, ensuring accuracy and completeness Prepare comprehensive validation reports summarizing results and conclusions Maintain accurate and organized validation documentation for audit purposes Compliance Management:Stay current with industry regulations, guidelines, and best practices related to validation Ensure that validation activities comply with relevant regulatory standards (eg, FDA, EMA) and company policies Collaboration and Communication:Collaborate with other departments, including Quality Assurance, Engineering, and Production, to ensure a holistic approach to validation Communicate validation status, findings, and recommendations to stakeholders Continuous Improvement:Identify opportunities for process improvement and efficiency in validation activities Participate in the development and implementation of corrective and preventive actions

Position Summary As a Senior Product Education Engineer at Harness, you will become an expert in Harness products to teach others to become experts. You will be the source of truth and lead others on operational recommended practices, implementation guidance, and solution architecture drawing upon your engineering experience. The Harness product suite empowers individuals and companies to provision, secure, connect, and run applications in the cloud according to the modern cloud operating model. For this role you should be comfortable working with code, configuration, and the command line. This role is cross-functional between product, engineering, sales engineering, and customer success. You should be excited about taking feedback and requests from the field, coming up with creative solutions to real-world problems, and documenting and presenting those solutions for others to learn from. You should be passionate about devops, microservices, security, teaching, and education both internally for Harness employees and externally for Harness users and partners. About The Role Ability to lead multi-day instructor-led training [ILT] for a variety of size customers and partners at Harness. Create hands-on lab exercises and interactive experiences to help practitioners become confident with Harness products. Create questions and answers to further Harness Certified Experts certifications. Write recommended and best practice guides for using Harness products in production. Curate educational resources created by other Harness staff and the open source community. Write clear, step-by-step guides for specific industry or customer use cases. Create or convert existing code samples to work on multiple cloud providers and for mixed workloads. Build automations helping further automate our ILT and certification offerings and ecosystem. Collaborate and build consensus with other education engineers, sales engineers, product management, engineering, and solution architects to understand customer use cases and document solutions to their problems. ABOUT YOU Genuine curiosity in learning how to learn and how to teach others to learn efficiently. Excellent written and verbal communication skills - this will be tested during the interview process and is required to be successful. Previous experience with any Harness product (production experience is not required). 4+ years of experience in a customer-facing technical role such as technical trainer, sales engineer, technical account manager, customer success engineer, enterprise architect, software engineer, DevOps engineer, or other relevant work experience. 1+ years experience in a programming language such as JAVA/Go/Python/NodeJS. 2+ years experience in cloud native technologies such as Kubernetes. 1+ years experience in public cloud technologies such as AWS/Azure/GCP. Experience with observability solutions such Prometheus/Open Telemetry/DataDog/AppDynamics. Experience operating and maintaining cloud infrastructure in a production environment is preferred. Experience with audio/video (recording, microphones, Adobe Premiere Pro, Screenflow or Camtasia) is preferred, but not required. Experience with graphic design or visual explanations is preferred but not required. Experience delivering curriculum, exams, and certifications via training partners is preferred but not required. Experience in teaching or education. This could be as a technical evangelist, tutor, or mentor is preferred but not required. Experience in LMS solutions to deliver interactive training and credentialing such as Instruqt is preferred, but not required.

The Software Development Manager(SDM) experience is a unique one at Amazon. Teams are structured in small groups with a strong impetus to innovate, drive end to end ownership and meet critical business goals. Fresh college graduates get to rub shoulders with a seasoned software engineers and researchers with industry leading technical abilities, solving challenging engineering problems that affect millions of Amazon customers. Engineers also get to collaborate and work with teams across the globe, in the process being exposed to a range of technologies, best practices and solution patterns. Our learning series sessions and Principal talks are among the most popular presentations with healthy debate and a cross pollination of ideas. All this contributes to the grooming of the fungible Amazon engineer who has exemplary technical skills, sharp business acumen and a strong drive to get things done. Amazon Device OS team is responsible for building Amazon Common Software (ACS) for Echo, TV, and other IoT devices. ACS for IoT devices is a software stack integrates that enables easy integration of Alexa Voice Services (AVS), Frustration Free Setup (FFS) and AWS IoT Device SDK for Device makers and silicon vendors. ACS software powers Alexa enabled Echo Show, TV, speakers, wearables and the other smart home products The Role: The Software Development Manager (Manager-III) with AI/ML experience to manage a two-pizza development team in Bangalore. The team is working on an innovative AI-driven big data solution, handling billions of data daily through GenAI-driven NLP queries. This SDM will be part of the Device OS organization and will be responsible for hiring, coaching, and leading a development team that creates innovative Cloud solutions enabling new/unique experiences for our customers on a wide range of Amazon Devices. The team also develops scalable micro-services and solutions that enable Device Makers to quickly build and launch devices quickly and in a cost-effective way. As a Software Development Manager, you will be responsible for hiring and leading a team of engineers developing software. In this position you will partner with product managers, technical program managers and other internal stakeholders. This hands-on position requires broad engineering competence in Amazon Cloud Stack such as EC2, Lambda, Dynamo DB and Java full-stack expertise and a good understanding of the scalable software system design. In addition, it will require demonstrated experience successfully planning, organizing and conducting software development projects in a dynamic environment. Key job responsibilities 1. Bringing thought leadership and ThinkBig ideas in driving GenAI based BigData initiative 2. Understanding on AWS EC2, Lambda, RDS, ES, and Quicksight 3. Complete understanding of AWS service usage and cost. Must bring in frugality in AWS resource related decisioning 4. A leader who can get the work done without enforcing the authority, and enables team to take bold risks 5. A coach who can care his peoples career growth, and empowers to be a SME by developing best out of them. - 5+ years of engineering team management experience - 8+ years of leading the definition and development of multi tier web services experience - 7+ years of engineering experience - Knowledge of engineering practices and patterns for the full software/hardware/networks development life cycle, including coding standards, code reviews, source control management, build processes, testing, certification, and livesite operations - Experience partnering with product or program management teams - Experience designing or architecting (design patterns, reliability and scaling) of new and existing systems

Your mission is to imagine and create a large set of designs based on our chips so that engineers across industries can use our chips effortlessly. This critical piece of work forms the bridge between us and the industry. Outcomes In the first six months, you will create custom designs for these products - smart locks, smart watches, motor controllers, smart meters, access control devices, battery management systems for EVs, industrial automation systems and robot controllers. What will your week look like Most of your week will involve working with the applications team to design solutions. You will need to work with the sales team to understand customers technical requirements and support them when they transition to our chips. This might involve meeting them in their office or hosting them in our office. You may have to help customers set up field tests and ensure their products work as expected. In this role, you will be closely coordinating with three teams The sales team that nurtures leads and brings you the solution the customer is looking for The engineering team to create solutions and feature stacks for customers and also communicate customer feedback The founders who lead technical discussions and make decisions on which features to add to products and how to implement them Travel might be involved, but much time will be spent in our head R&D office in the IIT Madras Research Park in Chennai. You will have to invest time and energy every week to improve your technical knowledge of the field, our products, and those of our prospects. Requirements Technical knowledge of the field is important. The candidate should have a degree in electrical or electronics engineering, have gained tech know-how by working in the field, or both. Hardware design and coding experience are a must. Between 3-5 years of experience in building solutions in an application engineering role, preferably in the semiconductor or electronics industry. Since the work involves coordinating with multiple teams, communication skills are very critical - both written and verbal. Industry awareness is important. The candidate must understand the content of the semiconductor and electronics industry with India as the focus. Key soft skills needed: the ability to plan and deliver tasks on time in full, follow up with collaborators, be responsive, and have similar soft skills to those associated with a good professional. We re on a crazy mission to compete with global giants like TI, NXP, etc. So, the candidate must have the inbuilt desire and motivation to take on a tough challenge.

Create and implement bare metal drivers for peripherals present in the SOC Closely collaborate with designers & verification engineers to identify and fix issues in design. Sample C/C++ application to run in FPGA Requirements Proven working experience in software/hardware engineering. Experience in hands-on development and troubleshooting on embedded targets. Solid programming experience in Embedded C or C++. Proven experience in embedded systems design with preemptive, multitasking real-time operating systems. Excellent knowledge of OS coding techniques, IP protocols, interfaces and hardware subsystems. Adequate knowledge of reading schematics and data sheets for components. Strong documentation and writing skills. Knowledge of Bluespec System Verilog/ Verilog is a plus but is not a mandatory requirement. FPGA knowledge is added advantage.

You will lead conversations with open accounts and nurture them. This might involve meeting them in their office or hosting them in our office. Further, you will have to understand the prospects needs, break them down, and find solutions that use our chips. In this role, you will be closely coordinating with three teams The account-based marketing team that opens accounts (and researches them) The solutions team that builds reference designs around our chips The founders who lead technical discussions and close deals There might be travel involved, but a significant amount of time will be spent in our head office at the IIT Madras Research Park in Chennai. You will have to invest time and energy every week to improve your technical knowledge of the field, our products, and those of our prospects. Requirements Technical knowledge of the field is important. Either the candidate should have a degree in electrical or electronics engineering or should have gained tech knowhow by working in the field, or both. Between 2-5 years of experience in leading sales to Indian business customers, preferably in electronics or manufacturing. Software sales experience is not helpful here. Since the work involves leading conversations, communication skills are very critical - both written and verbal. Industry awareness is important. The candidate must understand the content of the semiconductor and electronics industry with India as the focus. The candidate should be able to find and ingest market trends and perform data analysis to distil information into usable insights. Key soft skills needed: ability to plan and deliver tasks on time in full, manage data and workflow around CRM systems, follow-up with collaborators, responsiveness, and similar soft skills that one associates with a good professional. We re on a crazy mission and intend to compete with global giants like TI, NXP and so on. So, the candidate must have the inbuilt desire and motivation to take on a tough challenge.

About Enovix: Industries of the future Artificial Intelligence, Edge computing, 5G, Electric Vehicles, Augmented Reality and Virtual Reality all require greater battery energy capacity. Building and scaling a 100% active silicon anode has long been a goal of the battery industry because it dramatically increases capacity and performance. Enovix, based in Fremont, California, is the first company in the world to be capable of volume production of advanced Lithium-ion batteries with a 100% active silicon anode using its 3D cell architecture. The company has designed, developed and sampled advanced Lithium-ion batteries with energy densities five years ahead of current industry production. Enovix s initial goal is to provide designers of category-leading mobile devices with a high-energy battery so they can create more innovative and effective portable products. Enovix is also developing its 3D cell technology and production process for the EV and energy storage markets to help widespread use of renewable energy. Responsibilities: Test and implement state-of-the-art separators in Enovix s 3D cell for improved safety without compromising other performance metrics. Work with material suppliers and partners to specify and source materials. Improve methods to rapidly screen candidate materials via short-loop test vehicles for accelerated tests, understand their interactions with other cell components, and predict full cell performance. Design and optimize 3D cells that utilize these materials. This includes directly working with the design team, process module owners, process integration, and test engineers, as well as directing appropriate characterization and failure analysis on various experiments. Analyze in-line process data, metrology data, and electrical test data for rapid feedback to inform the next round of development. Summarize and present results to internal and external customers as appropriate. Qualifications: Masters or higher in Materials Science, Polymer Chemistry, or Chemical Engineering. 2+ years of industry experience working on Li-ion batteries is preferred. Experimental design and data analysis experience with tools like JMP is preferred. Demonstrated tolerance of ambiguity; flexibility to adapt to new situations is required. Ability to work in a fast-paced environment is required. Strong oral and written communication skills is required. The ability to work well with other team members to ensure success of programs is required. Experience working in high volume and pilot production environments is preferred. Enovix in an equal opportunity employer