Designing and optimizing standard cell libraries to achieve targeted PPA. Developing complex circuits including flip-flops, clock gating cells, level shifters, and power gating cells. Collaborating with layout designers to optimize layout parasitics. Engaging in layout extraction and understanding layout-dependent parameters. Conducting timing and power characterization of standard cells. Working closely with cross-functional teams for optimization across the design chain. The Impact You Will Have: Enhancing the performance, power, and area of standard cell libraries. Contributing to the development of high-impact, cutting-edge technology. Driving innovation in complex circuit design and optimization. Ensuring the successful integration of IP blocks into SoCs. Influencing the design and development of self-driving cars, AI, and IoT devices. Supporting Synopsys leadership in the silicon IP market. What You ll Need: Bachelors or Masters degree in Electrical Engineering or related field. 3+ years of experience in standard cell library design. Expertise in CMOS device characteristics and submicron process nodes. Proficiency in designing complex circuits and running high sigma variation analysis. Experience in layout design and optimization. Who You Are: Strong analytical and logical thinker. Detail-oriented with excellent problem-solving skills. Effective communicator and collaborator. Innovative and passionate about technology. Adaptable and able to work in a dynamic, fast-paced environment

Design, fine-tune, and optimize LLMs, retrieval-augmented generation (RAG), and reinforcement learning models for IT automation. Improve model accuracy, latency, and efficiency, ensuring optimal performance for IT service workflows. Experiment with cutting-edge AI techniques, including multi-agent architectures, prompt tuning, and continual learning. Implement MLOps best practices, ensuring scalable, automated, and reliable model deployment. Develop AI monitoring, logging, and observability pipelines to track model performance in production. Optimize GPU/TPU utilization and cloud-based AI model serving for efficiency and cost-effectiveness. Develop tools to measure model drift, inference latency, and operational efficiency. Implement automated retraining pipelines to ensure AI models remain effective over time. Work closely with cloud teams to optimize AI model execution across hybrid cloud environments. Stay ahead of emerging AI technologies, evaluating new frameworks, techniques, and research for real-world application. Collaborate to refine AI system architectures and capabilities, while also ensuring models are effectively embedded into IT automation workflows The Impact You Will Have: Enhance the efficiency and reliability of AI-powered IT automation solutions. Drive continuous improvement and innovation in AI model development and deployment. Ensure scalable and cost-effective AI model serving in cloud and hybrid environments. Improve real-time AI processing with minimal downtime and high performance. Optimize AI systems for performance, security, and cost in IT automation applications. Contribute to the advancement of Synopsys AI capabilities and technologies. What You ll Need: 8+ years of experience in AI/ML engineering, with a focus on model optimization and deployment. Strong expertise in AI frameworks (LangGraph, OpenAI, Hugging Face, TensorFlow/PyTorch). Experience implementing MLOps pipelines, CI/CD for AI models, and cloud-based AI deployment. Deep understanding of AI performance tuning, inference optimization, and cost-efficient deployment. Strong programming skills in Python, AI model APIs, and cloud-based AI services. Familiarity with IT automation and self-healing systems is a plus. Who You Are: Innovative and forward-thinking, constantly seeking to improve and optimize AI models. Collaborative and communicative, working effectively with cross-functional teams. Detail-oriented and meticulous, ensuring high standards in AI model performance and deployment. Adaptable and resilient, thriving in dynamic and fast-paced environments. Passionate about AI and its applications in IT automation and beyond

Working closely with a world-class R&D team, you ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM). Working closely with customers, you will bring the detailed requirements into the factory to enable R&D for a strong, robust, and successful product development. Working closely with product development team, you will validate and end-to-end solution both internally (before shipment) as well as in customer environment. Driving the deployment and smooth execution of SLM solutions into customers projects. Enabling customers to realize the value of silicon health monitoring throughout the lifecycle of silicon bring-up, validation, through in-field operations. The Impact You Will Have: Enhancing Synopsys Silicon Lifecycle Management (SLM) IP portfolio and end-to-end solution. Driving the adoption of Synopsys SLM solutions at premier customer base worlwide. Influencing the development of next-generation SLM IPs and solutions. What You ll Need: BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field. 4+ years of hands-on experience with SoC-level functional verification or Design-for-Test (DFT) or both. Good knowledge of AXI, APB Background in verification, with at least sub-system level verification Debugging abilities to identify issues in functional verification. Knowledge of DMA, ideally should have verified a sub-system with DMA Knowledge of High-speed IO sub-systems like PCIe and USB A thorough understanding of memory mapping concepts is essential. End to end knowledge of how transactions/data flow between the HSIO interface to/from memory Knowledge and experience with Memory BIST/DFT/ATE/SLT/any other test solutions Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions Customer facing experience is a plus - educating/guiding customer on technical details of a solution Good to have: Hands-on debug experience of silicon is a plus Some programming experience to write/debug simple drivers in C Detailed knowledge of the PCIe and USB protocols Architecture/micro-architecture experience Working with FPGAs

Building quality setup environments based on technology data from worldwide foundries. Writing scripts to automate processes and perform quality assurance on the environment. Working with EDA tools, including simulators and verification tools. Collaborating with local and international experts to find solutions to complex problems. Working independently while building productive working relationships with cross-functional teams. Continuously learning and exploring new technologies to enhance your skills and knowledge. The Impact You Will Have: Contributing to the creation of high-quality setup environments that enable efficient technology development. Automating processes to improve efficiency and accuracy in the engineering workflow. Enhancing the functionality and reliability of EDA tools through rigorous testing and verification. Solving complex problems by leveraging expertise from diverse, global teams. Fostering a collaborative environment that promotes innovation and continuous improvement. Driving the success of Synopsys projects and initiatives with your technical skills and dedication. What You ll Need: A bachelors degree and a minimum of 2 years of related experience or an advanced degree in Electronics/Electrical Communication Engineering/Cybernetics or a similar field. Proficiency in at least one programming language such as Python, Tcl, or Perl. An exceptional desire to learn and explore new technologies. Good investigation and problem-solving skills. Familiarity with physical verification flows like LVS/DRC/FILL/DFM and an understanding of layout design rules. Prior experience in Analog design is a plus. Knowledge and experience in tool/runset development/support is a plus. Experience in a UNIX/Linux environment. Strong communication skills and the ability to build productive internal and external working relationships. Who You Are: A collaborative team player who thrives in a diverse and multicultural environment. An independent worker who can manage tasks with minimal supervision. An effective communicator who can convey technical information clearly and concisely. An innovative thinker who is always looking for ways to improve processes and solve problems. A dedicated professional with a passion for technology and a commitment to continuous learning

You are an experienced and dynamic professional with over 15 years of experience in IP design or management, particularly in foundational IP/Interface IP across multiple process technologies up to 3nm. Your background includes significant experience in IP program management, working with cross-functional teams, and engaging with external SOC customers. You excel in presenting status updates to senior management and possess knowledge in SOC design and architecture, product qualification, signal and power integrity, and package design. You hold a BS or MS degree in Electrical or Computer Engineering. What You ll Be Doing: Leading and managing IP design and development projects from initiation through to delivery. Coordinating with cross-functional teams to ensure project milestones and deliverables are met on time. Engaging with external SOC customers to understand their requirements and ensure their needs are met. Presenting project status updates and reports to senior management and stakeholders. Ensuring adherence to quality standards and regulatory requirements throughout the project lifecycle. Driving continuous improvement initiatives within the program management processes. The Impact You Will Have: Ensuring the successful delivery of high-quality IP products that meet customer expectations. Contributing to the strategic goals of Synopsys by effectively managing complex projects. Enhancing cross-functional collaboration and communication within the organization. Driving innovation in IP design and development through effective program management. Building strong relationships with external SOC customers, enhancing customer satisfaction and loyalty. Improving the efficiency and effectiveness of program management processes and practices. What You ll Need: 15+ years of experience in IP design or management in multiple process technologies up to 3nm. Experience in IP program management or working with cross-functional teams. Experience in working with external SOC customers and presenting to senior management. Knowledge of SOC design and architecture, product qualification, signal and power integrity, and package design. BS or MS degree in Electrical or Computer Engineering

Lead the architecture and development of analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY designs. Ensure designs meet PCIe protocol standards, optimizing for performance, power, and area targets. Oversee the porting of PHY designs to different technology nodes, maintaining signal integrity and performance. Collaborate with cross-functional teams to integrate analog circuits into larger SerDes PHY systems. Develop and implement verification strategies for high-speed analog/mixed-signal circuits using advanced simulation tools. Supervise physical layout to minimize parasitics, device stress, and process variation impacts. Review simulation and measurement data for design validation and compliance with PCIe standards. Provide technical leadership and mentorship to junior engineers in analog/mixed-signal design best practices. Document design features, specifications, test plans, and methodologies for future reference. Collaborate with the characterization team to validate the electrical performance of circuits in silicon. The Impact You Will Have: Drive the development of next-generation PCIe 6 and PCIe 7 PHY designs, contributing to the advancement of high-speed interface technology. Ensure that Synopsys analog/mixed-signal circuits meet stringent industry standards, enhancing the companys reputation for excellence. Facilitate the seamless integration of analog circuits into complex SerDes PHY systems, improving overall system performance. Mentor and develop junior engineers, fostering a culture of continuous learning and innovation within the team. Contribute to the successful porting of PHY designs across different technology nodes, ensuring versatility and adaptability. Enhance the companys design verification processes, leading to more robust and reliable high-speed analog/mixed-signal circuits. What You ll Need: PhD with 5+ years, or MTech/MS with 10+ years of experience in analog/mixed-signal circuit design, with a focus on high-speed interfaces such as PCIe 6/7 or SerDes PHY designs. Extensive experience in transistor-level design of high-speed analog building blocks, such as LDOs, Bandgap references, ADC/DAC, PLLs, DLLs. Proven silicon experience in developing PHY circuits that meet strict PCIe standards. Expertise in high-speed SerDes AFE (Analog Front-End) development, including CTLE and CDR design. Experience designing high-speed SerDes transmitters, with in-depth knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis). Strong background in jitter budgeting analysis, including understanding the sources of jitter and strategies for minimizing its impact on signal integrity. Extensive experience with the porting of PHY designs across different technology nodes. Strong expertise in CMOS technologies, including finFET and SOI processes. In-depth understanding of the PCIe protocol, signal integrity requirements, jitter performance, and high-speed clocking. Proven ability to supervise layout design to minimize the effects of parasitics, process variations, and electromigration. Demonstrated ability to lead and mentor design teams, working across departments to ensure successful project outcomes

Collaborate with cross-functional teams to drive product success. Develop and execute product engineering strategies. Serve as the technical interface between teams. Engage with sales and pre-sales teams to align product goals. Build and manage time plans and schedules for product development. Ensure seamless communication and coordination across different levels of the organization. The Impact You Will Have: Drive innovation in VLSI product engineering, influencing the development of cutting-edge technology. Enhance product quality and performance through strategic engineering initiatives. Foster collaboration and knowledge sharing across cross-functional teams. Contribute to the successful execution of complex projects, meeting organizational goals. Enhance customer satisfaction by delivering high-quality, reliable products. Support the growth and development of the Synopsys product portfolio. What You ll Need: Minimum 8 years of experience in VLSI product engineering. Exposure to analog and digital SOC design flows and methodologies. Experience in RTL Development, RTL Verification, and RTL to GDS flow. Proven track record of working on different technology nodes and driving product innovation. Strong customer-centric approach with the ability to manage multiple projects. Who You Are: Excellent communicator with strong written and verbal skills. Adept at interfacing with various organizational levels. Proficient in database management and ensuring data cleanliness. Knowledgeable about industry trends and emerging technologies in VLSI. Motivated and experienced professional looking for a new challenge

Driving the physical implementation of high-speed interface IPs and test-chips from RTL to GDS. Managing timing and physical sign-off to ensure successful project tape-outs. Collaborating with multiple functional groups, including front-end, analog, and CAD teams. Focusing on advanced SerDes developments, including the latest 56/112G PAM4 standards. Leading the physical design team to ensure on-time delivery of projects. Utilizing your software and scripting skills to enhance CAD automation methods. The Impact You Will Have: Contributing to the successful delivery of high-performance silicon IPs that power the Era of Smart Everything. Ensuring the integration of more capabilities into SoCs, meeting unique performance, power, and size requirements. Reducing the risk and time-to-market for differentiated products. Driving technological innovation through advanced SerDes development. Enhancing Synopsys reputation as a leader in chip design and verification. Supporting the companys mission to power the world s most advanced technologies for chip design and software security. What You ll Need: 10+ years of physical design experience with recent contributions to project tape-outs. Intimate understanding of the full design cycle from RTL to GDSII, including chip level. Experience with advanced FinFET nodes, TSMC 16 nanometer or below. Solid understanding of IC design, implementation flows, and methodologies for deep submicron design. Proven track record for technical steering of physical design teams for on-time delivery. Who You Are: Excellent communicator with the ability to engage with peer groups and customers. Autonomous and capable of making timely judgments. Proficient in software and scripting skills (Perl, Tcl, Python). Knowledgeable in CAD automation methods and industry standards in deep sub-micron designs. Able to travel internationally as required

Owning the complete physical implementation process at both block and chip levels. Delivering timing clean blocks and chip-level designs that meet design targets. Ensuring DRC, LVS, and IR closure for all designs. Setting up and evaluating all aspects of the physical design flow, including place and route, timing, PV, and IR. Collaborating closely with the frontend design team to resolve design issues. Executing project responsibilities from start to completion, contributing to moderately complex aspects of the project. The Impact You Will Have: Ensuring the delivery of high-quality, timing-clean designs that meet industry standards. Driving innovation in physical design methodologies and processes. Contributing to the development of cutting-edge technologies that shape the future. Enhancing the overall efficiency and effectiveness of the design team. Providing mentorship and guidance to junior engineers, fostering a culture of continuous learning and improvement. Strengthening Synopsys position as a leader in the semiconductor industry through your expertise and contributions. What You ll Need: MSEE/BSEE with 6+ years of related experience in ASIC physical design. In-depth understanding of physical design specialization, with working knowledge of one other related area. Strong problem-solving skills and creativity in resolving design issues. Experience in scripting using Tcl and Perl. Ability to execute project responsibilities independently and contribute to team-driven projects. Who You Are: Detail-oriented and committed to delivering high-quality work. Collaborative and able to work effectively in a team environment. Proactive and able to take ownership of tasks and projects. Excellent communicator, capable of networking with senior personnel. Mentor and guide to junior peers, sharing knowledge and expertise.

Reviewing Die, package, and PCB physical layout designs Modeling, simulating, and verifying high-speed interface performance against specifications Participating in the improvement of SI/PI methodology flows Collaborating and networking with other teams on task-oriented projects Independently driving SI/PI research and development activities Ensuring designs meet stringent performance, power, and size requirements The Impact You Will Have: Enhance the performance and reliability of high-speed interfaces Contribute to the development of cutting-edge technology in chip design Improve SI/PI methodology flows, increasing efficiency and accuracy Foster collaboration and innovation across globally distributed teams Drive research and development initiatives to stay ahead in the industry Support Synopsys mission to lead in the Era of Pervasive Intelligence What You ll Need: Bachelors or Masters degree in Electrical or Electronics Engineering Minimum of 8 years of relevant experience Proficient in Transmission line theory and time/frequency-domain analysis Experienced with SPICE and familiar with 3D field solvers Conversant with working of DDR and PCIe/Ethernet interfaces Good verbal and written English communication skills Experience in scripting languages such as Python and TCL is a plus Familiarity with both Windows and Linux operating system

An Emulation Expert with deep knowledge of IP interfaces such as PCIe and DDR, and experience with Zebu. You have a proven track record in IP product development focused on emulation and verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Your hands-on approach, collaborative mindset, and proactive attitude drive results. You are passionate about right-first-time development, ensuring traceability of all verification requirements and covering the entire ecosystem of Controller and PHY. What You ll Be Doing: Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification of all its functions, covering both the Controller and PHY. Reporting metrics and driving improvements in Emulation IP. Using your expertise to drive requirements for the Emulation IP and ensure its correct usage and deployment in verification strategies for both Controller and PHY. Staying ahead of evolving standards, understanding future changes, ECNs, and specification errata, and driving this understanding into both the Emulation IP and Design IP teams. Reviewing test plans in both Emulation IP and Design IP to ensure they deliver the required function, feature, and quality to be best in class. The Impact You Will Have: Enhancing cross-functional collaboration to improve product quality and end customer satisfaction. Changing the mindset in the way we use Emulation IP in validating digital designs and architectures. Driving innovation in defining requirements for IP product development, in the context of Emulation. Evolving and integrating best-in-class methodologies within the organization. Standardizing and optimizing workflows to increase efficiency and compliance. What You ll Need: 8+ years of relevant experience. Results-driven mindset. Subject Matter Expert in PCIe and DDR interfaces. Experience with Zebu in the context of technology and IP verification . Proven track record in IP product development, specifically emulation . Experience in cross-functional collaborations. Excellent communication skills and a beacon for change. Adaptability and comfort in a matrixed, international environment .

Developing SignOff ECO optimization algorithms and heuristics. Debugging issues related to design loading and timing/power optimization. Striving for continuous improvements in QoR to achieve faster timing convergence with optimal power overhead. Collaborating with a team of engineers to develop technical solutions to complex problems. Communicating with product engineers to understand and define problem scope. Ensuring strict performance and quality requirements are met. The Impact You Will Have: Enhancing the performance and efficiency of PrimeClosure, the industrys first AI-driven signoff ECO solution. Contributing to the development of cutting-edge algorithms that optimize timing and power in chip design. Improving the overall quality and reliability of our products through rigorous debugging and testing. Driving innovation and continuous improvement in our engineering processes. Supporting customer success by resolving issues and implementing new features based on their feedback. Helping shape the future of AI-driven optimization in the semiconductor industry. What You ll Need: A degree in Computer Science or Electronics. 5+ years of experience in relevant field Strong analytical and problem-solving skills. Proficiency in C/C++ and Linux. Excellent communication and teamwork abilities. A passion for technology and innovation. Who You Are: A collaborative team player who thrives in a dynamic and innovative environment. A proactive and self-motivated individual with a strong attention to detail. An excellent communicator who can articulate complex ideas clearly and effectively. A creative thinker who is always looking for new ways to solve problems and improve processes. A dedicated professional committed to delivering high-quality work

An experienced Verification Engineer who is passionate about technology and innovation. You are a problem-solver at heart with a strong foundation in digital design concepts and hands-on experience in programming with C++ and HDL languages. You thrive in collaborative environments and are comfortable taking on individual contributor or tech-lead roles. You are eager to work on cutting-edge technology, particularly in the field of emulation mode development and deployment for Zebu. Your technical expertise is complemented by excellent communication skills and a team-oriented mindset. What You ll Be Doing: * Developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI. * Implementing designs in C++, RTL, and SystemVerilog-DPIs. * Collaborating with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments. * Creating and optimizing use models and applications for various emulation projects. * Conducting thorough verification and validation processes to ensure the highest quality of emulation models. * Providing technical guidance and mentorship to junior team members when necessary. The Impact You Will Have: * Enhancing the efficiency and effectiveness of our emulation models, significantly reducing time-to-market for new technologies. * Contributing to the development of high-performance silicon chips that power a wide range of applications, from consumer electronics to advanced computing systems. * Ensuring the reliability and robustness of our verification processes, thereby improving the overall quality of our products. * Driving innovation within the team, pushing the boundaries of what is possible in emulation and verification. * Playing a crucial role in the successful bring-up of SoCs, enabling software development in pre-silicon environments. * Fostering a collaborative and inclusive team culture that values continuous learning and improvement. What You ll Need: * Strong programming skills in C++ and a solid understanding of object-oriented programming concepts. * 5+ years of experience in relevant domain * Proficiency in HDL languages such as System Verilog and Verilog. * Familiarity with digital design concepts and verification methodologies. * Experience with scripting languages like Perl or TCL is a plus. * Knowledge of protocols such as ENET, HDMI, MIPI, AMBA, and UART is advantageous. Who You Are: * An excellent communicator who can articulate complex technical concepts clearly and effectively. * A proactive team player who is flexible, resourceful, and responsible. * An innovative thinker who is always looking for ways to improve processes and outcomes. * A detail-oriented professional who values quality and precision in their work. * A lifelong learner who stays updated with the latest industry trends and technologies.

You are a highly skilled and motivated GenAI/LLM Researcher/Engineer with a passion for pioneering advancements in the field of General Artificial Intelligence and Large Language Models. With a strong foundation in AI/ML and software development, you are adept at leveraging your expertise to revolutionize the Electronic Design Automation (EDA) domain. Your in-depth understanding of UVM and EDA tools is complemented by your ability to collaborate effectively with cross-functional teams. You thrive in a dynamic environment, where your innovative mindset and problem-solving abilities drive the development of cutting-edge solutions. Your proactive approach to staying updated with industry trends and advancements ensures that you remain at the forefront of AI technology. What You ll Be Doing: Research and develop novel GenAI/LLM-based solutions for EDA applications, such as Design automation, Verification, and Optimization. Focus on UVM automation using GenAI techniques. Collaborate with cross-functional teams to integrate GenAI/LLM technologies into existing EDA tools and workflows. Design, implement, and optimize AI models using popular frameworks (e.g., TensorFlow, PyTorch). Develop software applications and tools to demonstrate GenAI/LLM capabilities in EDA. Publish research papers and present at conferences to showcase innovative solutions. Stay up-to-date with industry trends and advancements in GenAI/LLM. Work closely with customers to understand their needs and provide tailored solutions. Participate in agile development methodologies, ensuring timely delivery of high-quality solutions. The Impact You Will Have: Drive innovation in the EDA domain through the application of cutting-edge GenAI/LLM technologies. Enhance the efficiency and accuracy of design automation and verification processes. Contribute to the development of state-of-the-art AI models that set new industry standards. Facilitate the integration of advanced AI solutions into existing workflows, improving overall productivity. Shape the future of EDA by introducing novel, AI-driven methodologies. Establish Synopsys as a leader in the application of GenAI/LLM in the semiconductor industry. What You ll Need: Bachelors/Masters in Computer Science, Electrical Engineering, or related field. 5+ years of experience in AI/ML research and development. Strong programming skills in Python, C++, or Java. Experience with popular AI/ML frameworks (e.g., TensorFlow, PyTorch). Familiarity with EDA tools and workflows, and prior experience in UVM. Excellent problem-solving skills and analytical thinking

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: Strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience in tools like DC, ICC2, PT-SI,FC is a definite advantage. Should be a strong team player, excellent communicator as the role involves daily technical interaction with local, US counter parts. What You ll Be Doing: He/She will be part of SNPS DDR/HBM/Ucie IP implementation team and responsible for the implementation and integration of world class DDRs at the cutting-edge technology nodes. Timing closure above ~4GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR/HBM/HBI timing closure, implementation would be an added advantage. Should be very hands-on and able to technically lead a team of 4-6 junior engineers towards successful completion of project on-time and with top quality. Who You Are: Typically requires a minimum of 6+ years of related experience after the post graduation. Possesses a full understanding of specialization area plus working knowledge of multiple related areas. A team player Independently resolves a wide range of issues in creative ways on a regular basis. Customarily exercises independent judgment in selecting methods and techniques to obtain solutions. Performs in project leadership role. Contributes to complex aspects of a project. Determines and develops approach to solutions. Work is independent and collaborative in nature. Provides regular updates to manager on project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job.

Implementing and power signoff of world-class DDRs at cutting-edge technology nodes. Achieving timing closure above ~2GHz and integrating mixed signal macro IPs. Building efficient clock trees with very tight skew balancing. Providing regular updates to your manager on project status. Guiding junior peers with aspects of their job and contributing to their development. Representing the organization on business unit and/or company-wide projects. The Impact You Will Have: Driving the implementation of cutting-edge DDR technology, contributing to the advancement of high-performance computing. Ensuring the power efficiency and performance of our silicon chips, crucial for our competitive edge. Enhancing the reliability and integration of mixed signal macro IPs. Contributing to the overall success and innovation of Synopsys IP solutions. Mentoring junior engineers, fostering a culture of continuous learning and improvement. Representing Synopsys in key projects, influencing the direction and success of our initiatives. What You ll Need: Minimum of 5+ years of related experience in ASIC Physical Design. Proficiency in tools like DC, ICC2, StarRC, and PT-SI. Strong understanding of timing closure, power signoff, and mixed signal macro IP integration. Experience with DDR power signoff and clock tree building. Excellent problem-solving and analytical skills. Who You Are: A strong team player with excellent communication skills. Independent and collaborative, capable of working with minimal supervision. Creative and innovative, able to develop unique solutions to complex problems. Detail-oriented and organized, ensuring high-quality project outcomes. Passionate about continuous learning and professional growth.

You are a seasoned professional with a passion for analog design and a knack for solving complex problems With a strong foundation in CMOS processes and deep submicron technologies, you bring a wealth of knowledge and experience to the table You thrive in a collaborative environment, where your excellent communication skills enable seamless interactions with internal development teams You are adept at executing circuit design tasks with precision, ensuring the highest product quality and efficiency Your familiarity with ASIC design flow and JEDEC standards for DDR interfaces sets you apart, and you are always eager to learn and adapt to new challenges Your technical acumen, combined with your dedication and innovative mindset, makes you an ideal fit for our team What You ll Be Doing: - Ownership of complete physical implementation at block level & chip level. Responsible for delivering timing clean blocks/chip level that meet design targets. - DRC, LVS & IR closure. Evaluates all aspects of the physical design flow from place and route, timing, PV & IR and is able to setup these flows. - Experience in all chip level tasks (P&R, STA, PV, IR) . Work closely with the frontend design team to resolve design issues . The Impact You Will Have: * Enhancing the performance and efficiency of our silicon IP portfolio. * Contributing to the rapid integration of advanced capabilities into SoCs. * Reducing the time-to-market and risk for our customers products. * Driving innovation in analog design and setting new industry standards. * Strengthening Synopsys position as a leader in chip design and verification. * Empowering the development of high-performance, differentiated products. What You ll Need: - Candidates with MSEE/BSEE with 5+ years of related experience. Possesses in depth understanding of specialization area plus working knowledge of one other related area. - Resolves issues in creative ways. - Exercises judgement in selecting methods and techniques to obtain solutions. - Executes project responsibilities from start to completion. - Contributes to moderately complex aspects of a project. - Determines and develops recommendations to solutions. - Works on team-driven or task-oriented projects. - May guide more junior peers with aspects of their job. - Networks with senior internal and external personnel in own area of expertise. - Strong knowledge on scripting using tcl, perl . Who You Are: * A collaborative team player with a proactive approach. * Detail-oriented with a commitment to quality and efficiency. * Innovative and adaptable, always seeking to learn and grow. * Effective communicator, able to convey technical information clearly. * Problem-solver with strong analytical skills.

Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. Responsibilities: DDR I/O Circuit design Requirements- Qualification: BTech/MTech Skills/Experience: MTech+3years / BTech+5years Knowledge of CMOS processes and issues in deep submicron process technologies. CMOS circuit design and layout methodology & flow; basic understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage. Familiarity with ASIC design flow. Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus. Ability to execute assigned circuit design tasks with best product quality and efficiency. Good written and verbal communication skills in interactions with internal development teams.

Defining and developing ASIC RTL design and verification at both chip and block levels. Writing and modifying test cases, checkers, and scoreboards in a system Verilog-based test environment. Collaborating with cross-functional teams to ensure seamless integration of analog and digital components. Conducting AMS verification, particularly for high-speed SerDes designs supporting multi-protocols. Utilizing Synopsys analog mixed-signal design tools for efficient design and verification processes. Programming and scripting using TCL, Perl, and Python to automate and streamline workflows. The Impact You Will Have: Enhancing the performance and reliability of our high-performance silicon chips. Contributing to the development of innovative technologies that drive the Era of Pervasive Intelligence. Improving the efficiency and effectiveness of our design and verification processes. Ensuring the seamless integration of analog and digital components in our products. Supporting the creation of cutting-edge solutions for self-driving cars, learning machines, and more. Driving continuous technological innovation within Synopsys and the broader industry. What You ll Need: Looking for 2+yrs experience with BTech / MTech in VLSI / Electronics/ Microelectronics Knowledge or hands-on expertise/analysis of Analog and digital CMOS circuit designs Knowledge on electrical circuit networks and analysis Knowledge or hands-on Verilog/System Verilog languages and supported methodologies like VMM, UVM Must be able write/modify testcases, checkers, scoreboards in a system Verilog based test environment AMS verification experience in high speed Serdes designs supporting multi-protocols is an advantage. Experience with the Synopsys Analog mixed-signal design tool set is an advantage. Modelling languages Verilog-a/ams can be an advantage Programming/scripting know-how e. g. tcl, perl, python Experience with Linux Good communication skills, ability to take ownership Self-organized to ensure that project timescales are met Who You Are: Excellent communicator with strong interpersonal skills. Proactive and able to take ownership of projects. Self-organized and capable of managing time effectively. Collaborative team player who thrives in a dynamic environment. Detail-oriented and committed to delivering high-quality results.

Designing and verifying complex Analog Mixed-Signal layouts, ensuring high-quality and reliable IPs. Collaborating with cross-functional teams to optimize layout designs for performance and manufacturability. Utilizing advanced tools and methodologies to mitigate deep submicron effects. Conducting floor-planning, routing, and top-level verification. Ensuring compliance with DRC, LVS, LPE standards and addressing ESD and latch-up considerations. Optimizing power routes and addressing EM and IR considerations for robust designs. The Impact You Will Have: Enhancing the performance and reliability of our high-speed SerDes IPs and other critical components. Driving innovation in Analog Mixed-Signal layout design, contributing to cutting-edge technology developments. Ensuring seamless integration and functionality of our IPs in diverse applications. Improving design efficiency and manufacturability through advanced layout techniques. Contributing to the success of our product development lifecycle by delivering high-quality designs. Supporting our mission to lead in chip design and IP integration, shaping the future of technology. What You ll Need: 6+ years of experience in Analog Mixed-Signal layout and verification. Advanced understanding of deep submicron effects and mitigation techniques. Proficiency in using advanced layout design tools and methodologies. Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below. Familiarity with layout design flow, including top-level verification flow, DRC/LVS, LPE.

Developing next-generation high-speed memory interface PHY IPs (DDR/HBM/UCIe) Executing projects in advanced technologies with a focus on analytical and problem-solving skills Designing high-speed IOs for memory interface PHY IP in CMOS/FinFET/GAA Collaborating with cross-functional teams globally to achieve project goals Ensuring product quality and efficiency in all design tasks Staying updated with the latest industry standards and technological advancements The Impact You Will Have: Driving the development of innovative high-speed memory interface PHY IPs Contributing to the integration of advanced capabilities in SoCs Enhancing the performance, power efficiency, and size optimization of target applications Reducing risk and accelerating time-to-market for differentiated products Collaborating with global teams to deliver high-quality products Setting industry benchmarks for advanced analog design technologies What You ll Need: BTech/MTech degree in a relevant field 3+ years of experience in analog design fundamentals and device physics Proficiency in high-speed IO designs in advanced technologies Experience with ESD and reliability concepts Knowledge of JEDEC requirements for memory interfaces and standards Familiarity with signal integrity and/or power integrity is a plus Who You Are: An analytical thinker with strong problem-solving skills A collaborative team player with excellent communication and interpersonal skills Detail-oriented and capable of executing tasks with high precision and efficiency Adaptable and eager to learn new technologies and industry standards Passionate about innovation and technological advancement

"> Search Jobs Find Jobs For * Designing and developing DDR I/O circuits to meet performance and power specifications. * Collaborating with cross-functional teams to integrate analog circuitry into SoCs. * Executing circuit design tasks with a focus on product quality and efficiency. * Conducting layout reviews and ensuring adherence to design methodologies. * Participating in design reviews and providing technical insights. * Staying updated with the latest advancements in CMOS processes and deep submicron technologies. The Impact You Will Have: * Enhancing the performance and efficiency of our silicon IP portfolio. * Contributing to the rapid integration of advanced capabilities into SoCs. * Reducing the time-to-market and risk for our customers products. * Driving innovation in analog design and setting new industry standards. * Strengthening Synopsys position as a leader in chip design and verification. * Empowering the development of high-performance, differentiated products. What You ll Need: * BTech/MTech in Electrical Engineering or a related field. * 4+ years of experience in CMOS circuit design and layout methodology. * Strong knowledge of deep submicron process technologies. * Familiarity with ASIC design flow and JEDEC standards for DDR interfaces. * Excellent written and verbal communication skills. Who You Are: * A collaborative team player with a proactive approach. * Detail-oriented with a commitment to quality and efficiency. * Innovative and adaptable, always seeking to learn and grow. * Effective communicator, able to convey technical information clearly. * Problem-solver with strong analytical skills.

We are looking for a seasoned and enthusiastic professional who thrives on problem-solving, is committed to ongoing learning, and is eager to work with advanced technologies. You possess outstanding communication skills and enjoy working in a dynamic team of highly talented engineers. As the Manager- Analog Design, you have a deep understanding of deep understanding of high-speed circuit design. You are experienced in leading teams, designing and analyzing analog circuits, combined with your knowledge of network/transmission line/SI analysis and semiconductor devices/physics, makes you a valuable asset. managing regression analysis and collaborating closely with design, layout and other stakeholders. You have experience in modeling complex/non-linear circuit behavior to linear models for stability and jitter analysis. Your ability to micro-architect circuits from specifications and focus on enhancing PPA targets and reducing turnaround time sets you apart. You possess a strong grip on design reliability analysis and can work effectively both independently and lead the team. Your excellent communication skills and collaborative nature enable you to work seamlessly with cross-functional teams to achieve project goals. You are dedicated to staying updated with the latest advancements in analog design and are eager to contribute to innovative solutions that shape the future of technology. What You ll Be Doing: * Collaborate with design, Layout, ESD teams to align requirements and resolve bottlenecks effectively. * Innovate and refine design methodologies to enhance scalability, efficiency, and reliability. * Design, develop, and verify high-speed analog and mixed-signal integrated circuits. * Collaborate with cross-functional teams to define design specifications and requirements. * Model complex/non-linear circuit behavior to linear models for stability and jitter analysis. * Perform circuit simulations and layout verification to ensure design accuracy and performance. * Optimize designs for power, performance, and area (PPA) and reduce turnaround time. * Contribute to the development of design methodologies and best practices. The Impact You Will Have: * Advance the design and verification of high-speed analog and mixed-signal integrated circuits. * Ensure the accuracy and reliability of analog designs through rigorous verification and testing. * Collaborate with cross-functional teams to deliver innovative solutions that meet market demands. * Contribute to the continuous improvement of design methodologies and processes. * Support the development of cutting-edge technologies that enhance our products and services. * Drive innovation and excellence in analog design at Synopsys. What You ll Need: * Bachelor s degree in electrical engineering, Computer Engineering, or a related field. * 10+ years of experience in analog circuit design and analysis. * Deep understanding of analog circuits design and analysis techniques. * Experience in modeling complex/non-linear circuit behavior to linear models for stability and jitter analysis. * Good understanding of network/transmission line/SI analysis and semiconductor devices/physics. * Strong grip on design reliability analysis. * Ability to micro-architect circuits from specifications. * Focus on enhancing PPA targets and reducing turnaround time. Who You Are: * A strong leader with excellent communication and mentoring skills. * Innovative and committed to continuous improvement. * Detail-oriented with a strategic mindset. * Collaborative, with the ability to work effectively in a team environment. * Passionate about technology and eager to work on cutting-edge projects

Leading the development of next-generation high-speed memory interface IPs (DDR/HBM/UCIe). Driving projects in new technologies with a focus on analytical and problem-solving skills. Acting as a technical mentor to ensure schedules and product quality are met. Developing and maintaining project schedules, working in cross-functional settings. Demonstrating proficiency in design concepts and methodologies. Taking on people management responsibilities, guiding and developing your team. The Impact You Will Have: Contributing to the development of cutting-edge memory interface PHY IPs that drive technological advancements. Ensuring high-quality product development through effective leadership and technical expertise. Mentoring and guiding your team to achieve their full potential and meet project goals. Collaborating with cross-functional teams to drive innovation and efficiency. Maintaining Synopsys leadership position in the semiconductor industry by delivering top-notch IPs. Shaping the future of technology through continuous innovation and excellence. What You ll Need: Bachelor s or Master s degree in Electrical Engineering or related field. 10+ years of experience in analog/mixed signal design. Knowledge of deep submicron process technologies - CMOS/FinFET/GAA. In-depth understanding of JEDEC requirements for memory interfaces and standards. Familiarity with ESD concepts and signal integrity/power integrity is a plus. Proven ability to lead projects and deliver high-quality products efficiently. Excellent written and verbal communication skills. Who You Are: A visionary leader with a passion for analog design and innovation. Analytical and detail-oriented with strong problem-solving skills. An effective communicator and mentor, capable of guiding and developing your team. Proactive and adaptable, able to thrive in cross-functional settings. Committed to delivering high-quality products and driving technological advancements.

Design, develop, and verify high-speed analog and mixed-signal integrated circuits. Collaborate with cross-functional teams to define design specifications and requirements. Model complex/non-linear circuit behavior to linear models for stability and jitter analysis. Perform circuit simulations and layout verification to ensure design accuracy and performance. Optimize designs for power, performance, and area (PPA) and reduce turnaround time. Contribute to the development of design methodologies and best practices. The Impact You Will Have: Advance the design and verification of high-speed analog and mixed-signal integrated circuits. Ensure the accuracy and reliability of analog designs through rigorous verification and testing. Collaborate with cross-functional teams to deliver innovative solutions that meet market demands. Contribute to the continuous improvement of design methodologies and processes. Support the development of cutting-edge technologies that enhance our products and services. Drive innovation and excellence in analog design at Synopsys. What You ll Need: Bachelor s degree in electrical engineering, Computer Engineering, or a related field. 4+ years of experience in analog circuit design and analysis. Deep understanding of analog circuits design and analysis techniques. Experience in modeling complex/non-linear circuit behavior to linear models for stability and jitter analysis. Good understanding of network/transmission line/SI analysis and semiconductor devices/physics. Strong grip on design reliability analysis. Ability to micro-architect circuits from specifications. Focus on enhancing PPA targets and reducing turnaround time.