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ASIC DFT Engineer

ASIC DFT Engineer

Cisco

4 - 8 years

14 - 19 Lacs

bengaluru

Posted:7 hours ago| Platform:

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Skills Required

jtag atpg scan insertion dft tetramax asic python physical design eda static timing analysis software testing simulation design verification timing analysis rtl silicon validation asic design verilog silicon debugging perl tcl protocols eda tools

Work Mode

Work from Office

Job Type

Full Time

Job Description

Who You'll Work With

You will be in the Silicon One development organization as an ASIC DFT Engineer in Bangalore India with a primary focus on Design-for-Test. You will work with DFT Lead, Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

What You'll Do

Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Who You Are

You are an ASIC Design for Test Hardware Engineer with 4-8 years of related work experience with a broad mix of technologies.

Minimum Qualifications:

Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 4 years of experience.
Knowledge of the latest innovative trends in DFT, test and silicon engineering.
Experience with Jtag protocols, Scan insertion and ATPG.
Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets.
Knowledge of the latest innovative trends in DFT, test and silicon engineering.
Experience working with Gate level simulation, debugging with VCS and other simulators.
Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
Strong verbal skills and ability to thrive in a multifaceted environment
Scripting skills: Tcl, Python/Perl.

Preferred Skills:

Test Static Timing Analysis
Post silicon validation using DFT patterns.

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ASIC DFT Engineer