444 Signal Integrity Jobs - Page 11

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 8+ years Hardware Engineering experience or related work experience. 8+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Overview Experienced STA/Timing Engineer with 3-10 Years of hands-on experience on timing sign off/convergence for complex SOCs. Ability to start immediately on timing analysis/sign-off with PD/Methodology teams across multiple sites and different technology nodes. : STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills. Willing to work in cross-collaborative environment. Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo. Education B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI. Preferred Qualification/Skills Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling. Hands-on experience with STA tools - Prime-time, Tempus Have experience working on timing convergence at Chip-level and Hard-Macro level. In-depth knowledge crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows, methods, and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages – TCL, Perl, Python Basic knowledge of device physics

1. Candidate shall have experience in handling multiple end to end product / project around RF design, analysis, testing, calibration, regulatory compliances and release of products for commercial deployments 2. Relevant experience of 3+ years in RF Design. Responsibilities 1. Lead the design, simulation, and verification of complex analog and mixed-signal circuits, Signal integrity, power integrity, impedance Analysis. 2. Perform advanced simulations and analyses to ensure exceptional circuit performance and compliance with specifications. 3. Create comprehensive documentation of design methodologies, specifications, and outcomes. 4. Multi radio front end and radio optimisation. 5. Extensive knowledge on RF matching, filter design and antenna matching. 6. Conversant with lab equipment like Spectrum Analyzer, Network analyser, RF Signal generators , IQXEL, MT8852 etc. 7. Experience on EMI/EMC, Antenna design, Signal Integrity and Thermal Analysis will be a key skill. 8. Design and develop Regulatory certified BLE, ZigBee, Wi-Fi modules. 9. Work closely with cross functional teams to derive the design specification for Modules. 10. Prototype Board bring-up, Validation and Characterization. 11. Handover design to manufacturing and help to derive the production test plan. 12. Documentation of design, test plan and test results. 13. Supporting Customer support team in debugging critical customer issues. 14. Radio side design and debugging. 15. RF performance evaluation, calibration and optimisation. 16. Link budget and harmonics analysis. 17. Tuning and optimisation of RF front end. 18. Deep understanding on radio chip, physical layer customisations and its impacts on the radio performance. 19. Understanding of various physical layer standards. 20. Willingness to contribute in global standards committee of next generation wireless systems. 21. Ownership of product level EMI/EMC compliances for global requirements as well. 22. Schematic, Layout and BOM selection.

Analog & Mixed-Signal Validation Engineer Job Description In your new role you will: As an Analog & Mixed-Signal Validation Engineer for power productsyou will responsible to measure datasheet parameters for PowerIC s(Controllers, drivers, current sensors, power switches) Debug issues related to IC functioning and parametric failures, and root causing the issues with help of design team. Usage of different type of instruments used in LAB (DMM, Oscilloscopes, Power Supplies, AFG etc) Development of Python Scripts for Test Automation. Collating measurements data and analysing it to find anomalies, trends and identify potential issues in design. Designing of the boards required for testing Power ICs considering power and signal integrity aspects. Work with Test/Product teams in debugging and correlating the results between the ATE and Bench platforms. Your Profile You are best equipped for this task if you have: Master s /bachelor s degree in Electrical/Electronic Engineering or equivalent field of studies. 0-1 years of experience in Analog and Power products characterization Good Analytical skills and understanding of Analog Circuits Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Detail-oriented with a commitment to quality and precision. Ability to develop Python scripts Contact: garima.chauhan@infineon.com We are on a journey to create the best Infineon for everyone.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Design Planning. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Verification. Experience1-3 Years.

Hands on experience in Circuit Design implementation of IPs including LDOs, Band Gap reference, Good working knowledgein Current Generators, POR, ADC/DACs, PLLs, Oscillators, Good working knowledge in General Purpose IOs, Temperature sensor, SERDES, PHYs, Good in Die to Die interconnect, High-speed IOs,

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Analog Circuit design. Experience3-5 Years.

Supports assigned NPI products as key DFM engineer responsible for PCBA manufacturability including compliance with EMS or other DFM guidelines in areas including SMT, BGA repair processes, wave solder, press fit, component package and new part qualification Works with signal integrity teams and PCB suppliers to develop PC board stack-ups Performs DFM reviews of new designs in execution with responsibility for resolving PCBA and PCB manufacturability issues Attends program teams, EMS partner reviews, DFM council or other meetings related to PCBA/PCB DFM issues Uses strong knowledge of interconnect, SMT, solder process/materials and new component packaging as it applies to PCBA manufacturing to improve designs for high yields and ease of assembly In coordination with factory teams, monitors or develops DOE s to identify and confirm process parameters related to PCBA Manages/leads specific mfg. technology related projects as required in collaboration with outside suppliers and internal subject matter experts Provides guidance/support to quality and sustaining mfg. engineering teams for critical quality or manufacturing problems on assigned products REQUIREMENTS BSEE/BSME or higher degree with at least 7-10 years of electronics manufacturing experience Proven track record in supporting new product development teams as an NPI mfg. engineer with responsibility for complex PCBA and/or PCB manufacturability Prefer candidates with both OEM PCBA NPI development and EMS partner factory experience Prefer good/strong knowledge of PCB CAD design and fabrication processes including stack-up analysis and development and understanding of PCB fabrication challenges encountered with complex PCBA s associated with aspect ratios, padstacks, backdrills, and POFV technologies Requires solid knowledge of interconnect and electronic assembly applications and technologies including soldering, press fit, and rework with knowledge of IPC-A-610. Understanding of complex failure mechanisms in PCBA process and or PCB fabrication and knowledge of standard failure analysis techniques (SEM, EDX, X-section, Die and Pry, CSAM) Demonstrated ability to work independently in a fast-paced growth environment Must have excellent English communications skills, both verbal and written. Excellent problem-solving/analytical skills with strong aptitude for teamwork Willingness to travel including domestic and international travel as necessary (estimated 5-10%)

Project description This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. Responsibilities Drive the development of cutting-edge memory-related firmware projects, contributing to the creation of innovative solutions Collaborate with a highly regarded team to bring innovation to memory-related firmware, ensuring solutions are at the forefront of industry advancements Tackle complex challenges by employing strong problem-solving skills, enhancing firmware to meet evolving performance and reliability standards SkillsMust have 7-10 years' experience. Strong with C language programming Working knowledge of git/gerrit Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Nice to have Understanding different vendor implementations and memory timing differences is a big plus

90/130/150nm and higher node with PMIC layout experience. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective actions if needed until result is successful Performs layout in such a way that final result meets the foundry layout rules. Provides extracted netlist for back annotation to DE as specified in the Design document, section layout. Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout. Adds extra useful information to the Block review document, section layout.

PCB design engineer shall provide technical expertise in designing and optimizing PCB designs and to resolve PCB design, reliability, schedule and/or cost issues at internal or external PCB fabricators. Key Responsibilities Read and interpret Electrical/Electronic Schematics. Generate detailed Fabrication drawings of Printed Circuit Boards (PCB) and Gerber files (Artwork). Creates hardware design document that covers design analysis, notes, and specific guidelines followed. Architect, design and develop high performance/bandwidth PCBs Perform PCB layout for analog, digital and RF circuit boards through fabrication and assembly drawings generation. Be a single point of responsibility in transferring schematic net-list design, ID and ME design into the physical PCB design based on electrical considerations such as signal integrity, power integrity, ID and mechanical integrity, EMC-EMI and safety, manufacturing industry spec and end-user usability requirement. Create and manage PCB documentation including fabrication and assembly drawings, Gerber files. Coordinate and approve PCB layout. Prepare BOM and fabrication documentation and follow revision control procedures. Bring up and test of the PCBs and auxiliary electronics. Develop PCB layout concepts that are in line with products that involve efficient manufacturing processes. Qualifications and Skills Relevant Bachelor s or Master s degree in electrical engineering, Design, Electronics Engineering, Embedded System Engineering, ECE or ETC. Desired skills Preferably a minimum of 3 years experience in using two or more of the PCB designing tools from the list given below. Familiar with KiCAD, ISIS, ARES, Allegro or similar industry standard tools. Familiarity with PCB failure modes and reliability in extreme environments including ability to resolve issues arising from these. Excellent knowledge of PCB manufacturing processes and of PCB materials. Strong knowledge of the fundamentals of digital and analog circuit design. Strong logic/board debug, and analytical skills. Apply for a PCB Design Engineer Position Full name Contact number Email address Qualification Working experience

NVIDIA is seeking Silicon Solutions Engineer for system level bringup, debug and validation of GPU and SoC. The sophisticated nature of various chip features poses many exciting debugging situations. Someone with solid understanding and innovative thinking is required for on time release of the products. As part of the Silicon Solutions Team, we are responsible for productizing NVIDIAs chips into groundbreaking consumer, professional, server, mobile, and automotive solutions. What you will be doing: Silicon and board bring up, validation, and debug from prototype to production. Responsible for the GPU and SoC system qualification including feature checks, system stress at PVT conditions, testing of large number of systems and debug of issues affecting any unit of the chip or software. Debug complex ASIC and board issues related to logic design, signal integrity and power delivery in a high energy work environment, with a team that is the best in the business! Understand architecture of next generation chips, develop test plans, scripts and implement. Understand various HW features related to power, performance and safety. Drive the debug of Silicon, Board or Software issues involving many multi-functional teams. Develop new methodologies to improve the silicon validation process and take it to the next level! What we need to see: BTech/BE or MTech/ME degree in Electronics with 2+ years of work experience. Good knowledge in board and system design considerations, experience in silicon design/bring up. Hardware design experience related to high speed subsystem design, High-speed IO protocols, on-chip interconnect would be much appreciated. An understanding of PC architecture and various commonly used buses. Familiarity with scripting languages like perl and/or python. Very good problem solving and debugging skills. Strong data analysis and logical reasoning skills. Must be a standout colleague and ready to work with global teams from diverse cultural backgrounds. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-Hybrid

About the Role This leadership position is pivotal within a global digital data business, contributing to the development of next-generation connectors, cable assemblies, and radio system components. Youll steer a specialized engineering team focused on Signal Integrity, guiding end-to-end product lifecycle activitiesfrom concept to high-volume manufacturing qualificationthrough rigorous design, simulation, and testing. This is more than managementit's strategic direction in a fast-evolving tech space where innovation and precision meet performance. Click to Apply - (https://forms.gle/fqb29wUvjNuV82C57) Responsibilities Strategic Leadership: Lead a globally distributed team of experienced SI engineers. Align design activities with organizational goals, customer expectations, and technical standards. Create and manage work plans, project schedules, budgets, and resource allocation. Technical Oversight: Define signal integrity performance parameters for innovative products. Guide complex simulations for multiple protocols: PCIe, USB, Ethernet, etc. Oversee connector design reviews using electromagnetic simulation tools and test validation data. Ensure adherence to qualification processes for high-speed connector interfaces and cable assemblies. Innovation & Execution: Integrate market trends and customer needs into technical roadmaps. Advocate a data-driven design culture through structured simulation reviews and continuous improvement. Lead advanced packaging and PCB layout exploration to support emerging high-speed protocols. Team Development: Build a cohesive, skilled team through talent assessments, structured onboarding, and continuous upskilling. Foster collaboration across geographies and functional disciplines (mechanical, process, materials, product). Provide clear coaching, feedback, and career development plans. Balance workloads and promote wellbeing through flexible, effective leadership. Key Technologies & Tools Signal Integrity Tools: Agilent ADS, Ansys HFSS, CST CAD Platforms: SpaceClaim, AutoCAD, Creo PCB Design: Altium, layout/fabrication validation Test Equipment: VNA, TDR, BERT Data Analysis: Statistical interpretation, tolerance modeling Simulation Interpretation: Channel modeling, S-parameter validation Ideal Candidate Profile 10+ years in electrical or RF design with progressive experience 3+ years of people management and cross-functional leadership Strong grasp of physical layer system architecture and packaging interfaces Skilled communicator able to present to technical and executive audiences Experienced in high-volume manufacturing qualification and risk analysis Proven success building high-performance teams with global collaboration

Job Description : Hands on experience in Block level PnR convergence with Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus In this position, candidate is expected to lead all block/chip level PD activities including floor plans, placement, CTS, optimization and routing techniques, RC extraction, STA, EM/IR DROP, PV Familiar with deep sub-micron designs below 10nm preferred BE/B Tech/ME/M TECH

This position requires an experienced technical lead familiar with validation processes through multiple product iterations and ideally, prior management experience. In particular, experience with DDR5 buffer chip products for high-speed analog characterization and knowledge of memory interfaces for server and enterprise applications is preferred. This candidate will need to be comfortable with dual roles of serving as a bench characterization lead and manage a small team of supporting engineers locally. Essential Duties and Responsibilities: Component Bench Characterization: Leverage best known test procedures including de-embedding, high-impedance probing, and noise compensation to resolve complex measurement challenges as data rates continue to scale. Support Design/Validation teams to characterize key parameters of high-speed memory devices. Work collaboratively with Designers to debug and optimize performance with open-ended tests that are not only driven by specifications. Validation Infrastructure Development: Develop new test infrastructure to support effective characterization and validation of high-speed memory interfaces. Maintain relationships with contacts for key equipment vendors and participate and lead in pathfinding/roadmap initiatives. Identify cycle time and cost improvements, including automations, to improve validation efficiency. Data Analysis and Reporting: Ability to synthesize results and identify next set of relevant experiments to understand issue. Generate consistent, well-written, and easily understandable reports in different formats as relevant to the audience. Develop and prove creative uses of LLM/AI techniques to analyze large validation data sets and generate effective visualizations and improve cycle time to final reports. Technical Communication: Effectively document test methodology and procedures to ensure reproducible and accurate results. Explain complex topics in appropriate level of detail to each relevant stakeholder. Work effectively with fellow Validation Engineers in diverse regions across language and technical knowledge differences. Team Management: Demonstrate ability to support/assist/mentor direct reports while also nurturing a culture of accountability and independence. Support development of direct reports to grow capabilities and advance in their career trajectory. Qualifications Required Qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, or a related field. 10+ years of hands-on experience in characterizing high-speed interfaces, particularly memory-related applications. Strong understanding of memory interface architecture and operation, preferably DDR5. In-depth knowledge of memory interface protocols and standards (e. g. , JEDEC specifications). Expertise in using typical high speed interface test equipment (BERT, Scope, Compliance S/W). Proficiency in scripting languages (e. g. , Python, Perl) for test automation and analysis. Excellent analytical and problem-solving skills. Strong communication and interpersonal skills. Preferred Qualifications: Masters degree in Electrical Engineering or a related field. Experience with advanced signal integrity measurements and applications for Design correlation. Experience with modern software tools for data visualization, analysis, and reporting; in particular dynamic interactive tools - including LLMs Company Description Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas is a global, multi-billion dollar, publicly traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what s next in electronics.

Role Description: This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products. Qualifications: He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of experience in physical design. He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Lead a team of Physical design engineers and be responsible for their blocks closure Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Expertise in Timing closure on high speed interfaces is a plus Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Contribute/Lead towards Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers as well as custom macros in 2nm and other cutting edge process technologies Job Description Contribute/Lead towards Memory Design Validation of all types of custom memory macros and memory compilers Perform functional verification, root cause design discrepancies, and help resolve them Perform signal integrity analysis, identify design weaknesses, and propose possible solutions to address them Perform transistor level simulations to check for any Power Up or Lock up issues and help resolve them Perform EM/IR analysis/simulations and evaluate impact on timing and internal margins Perform transistor level simulations to validate timing and internal margins, identify timing characterization holes, and help resolve them Perform various QA and validation checks to ensure accurate timing and power models Develop scripts to automate verification flow and data analysis Support silicon debugs and correlation to spice models Coordinate with memory design leads, modelling leads, and managers to define and execute on the memory validation plan Skill Sets Strong expertise in development of memory macros of all types and architectures Strong understanding of transistor level circuit behavior and analysis Good understanding of the layout and their related challenges in sub nanometer process technologies Good understanding of signal integrity, EM/IR, and reliability analysis Good understanding of memory behavioral and physical models Good understanding of DFT Schemes and chip level integration Proficient in running transistor level simulators, writing automation scripts, and are tools savvy Complete hands on experience in using Cadence schematic/layout editor tools Complete hands on experience with transistor level simulators, Monte Carlo variation analysis, waveform viewer tools such as; HSPICE, HSIM, XA, FineSim, XARA, nWave, waveform viewer, etc.. Experience in Skill/Perl/Python Scripting is a strong plus Good communication, interpersonal, and leadership skills Good debugging skills, problem solving and logical reasoning skills Motivated, self-driven and good at multi-tasking .

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Contribute/Lead towards Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers as well as custom macros in 2nm and other cutting edge process technologies Job Description Contribute/Lead towards Memory Design Validation of all types of custom memory macros and memory compilers Perform functional verification, root cause design discrepancies, and help resolve them Perform signal integrity analysis, identify design weaknesses, and propose possible solutions to address them Perform transistor level simulations to check for any Power Up or Lock up issues and help resolve them Perform EM/IR analysis/simulations and evaluate impact on timing and internal margins Perform transistor level simulations to validate timing and internal margins, identify timing characterization holes, and help resolve them Perform various QA and validation checks to ensure accurate timing and power models Develop scripts to automate verification flow and data analysis Support silicon debugs and correlation to spice models Coordinate with memory design leads, modelling leads, and managers to define and execute on the memory validation plan Skill Sets Strong expertise in development of memory macros of all types and architectures Strong understanding of transistor level circuit behavior and analysis Good understanding of the layout and their related challenges in sub nanometer process technologies Good understanding of signal integrity, EM/IR, and reliability analysis Good understanding of memory behavioral and physical models Good understanding of DFT Schemes and chip level integration Proficient in running transistor level simulators, writing automation scripts, and are tools savvy Complete hands on experience in using Cadence schematic/layout editor tools Complete hands on experience with transistor level simulators, Monte Carlo variation analysis, waveform viewer tools such as; HSPICE, HSIM, XA, FineSim, XARA, nWave, waveform viewer, etc.. Experience in Skill/Perl/Python Scripting is a strong plus Good communication, interpersonal, and leadership skills Good debugging skills, problem solving and logical reasoning skills Motivated, self-driven and good at multi-tasking .

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Contribute/Lead towards Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers as well as custom macros in 2nm and other cutting edge process technologies Job Description Contribute/Lead towards Memory Design Validation of all types of custom memory macros and memory compilers Perform functional verification, root cause design discrepancies, and help resolve them Perform signal integrity analysis, identify design weaknesses, and propose possible solutions to address them Perform transistor level simulations to check for any Power Up or Lock up issues and help resolve them Perform EM/IR analysis/simulations and evaluate impact on timing and internal margins Perform transistor level simulations to validate timing and internal margins, identify timing characterization holes, and help resolve them Perform various QA and validation checks to ensure accurate timing and power models Develop scripts to automate verification flow and data analysis Support silicon debugs and correlation to spice models Coordinate with memory design leads, modelling leads, and managers to define and execute on the memory validation plan Skill Sets Strong expertise in development of memory macros of all types and architectures Strong understanding of transistor level circuit behavior and analysis Good understanding of the layout and their related challenges in sub nanometer process technologies Good understanding of signal integrity, EM/IR, and reliability analysis Good understanding of memory behavioral and physical models Good understanding of DFT Schemes and chip level integration Proficient in running transistor level simulators, writing automation scripts, and are tools savvy Complete hands on experience in using Cadence schematic/layout editor tools Complete hands on experience with transistor level simulators, Monte Carlo variation analysis, waveform viewer tools such as; HSPICE, HSIM, XA, FineSim, XARA, nWave, waveform viewer, etc.. Experience in Skill/Perl/Python Scripting is a strong plus Good communication, interpersonal, and leadership skills Good debugging skills, problem solving and logical reasoning skills Motivated, self-driven and good at multi-tasking

Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge. Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of 14nm technode STA analysis, DCD knowledge. Candidate is preferably expert in PT and Tempus tools. Education Requirements B. Tech / M. Tech (ECE) Shift General Work Week Monday to Friday Joining time Immediate to 90 Days

Job Title: System-in-Package (SiP) Engineer - Semiconductor IC Package Design Location: Whitefield, Bangalore, India Tools Experience : Cadence APD/SIP MUST HAVE HAVE SYSTEM-IN-PACKAGE DESIGN EXPERIENCE. Company Overview: izmo Microsystems Pvt. Ltd. (www.izmomicro.com) is a pioneering semiconductor and systems company specializing in System-in-Package (SiP) miniaturization. With state-of-the-art facilities in Bangalore, we offer advanced 3D packaging solutions to meet the demands of high-density, high-performance systems across various industries, including consumer electronics, automotive, telecommunications, and green energy. Position Overview: We are seeking an experienced System-in-Package Engineer to lead the design and development of innovative SiP solutions. The ideal candidate will have a strong background in advanced packaging technologies and a proven track record of delivering high-performance SiP designs from concept to production. Key Responsibilities: Lead the design and layout of complex SiP solutions, including FCBGA and FCCSP packages, from initial concept through to tape-out. Collaborate with cross-functional teams, including digital designers, SI/PI engineers, and manufacturing teams, to define package requirements and ensure design integrity. Develop and optimize package layer stack-ups, padstacks, and design constraints to meet electrical and mechanical performance targets. Conduct feasibility studies, including fan-out analysis, mock-up designs, and package size reduction initiatives. Perform design rule checks (DRC), design verification, and ensure compliance with manufacturing and reliability standards. Drive continuous improvement in design methodologies and workflows, leveraging scripting and automation where applicable. Basic Qualifications: Bachelors or Master’s degree in Electrical Engineering, Mechanical Engineering, Materials Science, Physics, or a related field. Minimum of 5 years of experience with Cadence APD/SIP, with demonstrated ability to independently design and layout FCBGA/FCCSP packages. In-depth understanding of BGA package substrate technologies, assembly processes, and high-speed design principles. Familiarity with bill of materials (BOM), layer stack-ups, and design rules for high-speed applications. Working knowledge of package reliability, signal integrity (SI), and power integrity (PI) considerations. Strong problem-solving skills, with an entrepreneurial mindset and hands-on work ethic. Excellent teamwork and communication skills, with the ability to thrive in a dynamic, cross-functional environment. Preferred Qualifications: Experience with multi-chip modules, interposers, 2.5D, or heterogeneous package designs. Proficiency in scripting languages for design automation and reporting. Understanding of transmission line theory and SI/PI fundamentals. Why Join Us: At izmo Microsystems, you'll be at the forefront of semiconductor packaging innovation, working in a cutting-edge facility equipped with advanced technologies such as 3D die stacking and fine-pitch wire bonding. We offer a collaborative environment where your expertise will contribute to the development of next-generation electronic devices.

RF (Radio Frequency) Engineer Job Title : RF (Radio Frequency) Engineer Location : Chennai, Hyderabad, Bangalore Experience : 1-4 Overview: Specializes in designing and testing RF circuits and systems used in wireless communication, radar, and satellite systems. Key Responsibilities: Design RF front-end circuits and antennas. Perform impedance matching and signal integrity analysis. Conduct RF testing and compliance verification. Work with high-frequency simulation tools. Tools & Technologies: ADS, HFSS, CST Microwave Studio Spectrum analyzers, network analyzers LTE, Wi-Fi, Bluetooth, 5G standards Career Path: Senior RF Engineer RF Systems Architect Wireless Communications Lead

Project Engineer (Design) - Traction Power Supply Systems - Rail Electrification We are looking for a Project Engineer (Design) Traction Power Supply Systems Rail Electrification . Meeting the need for smart-mobility solutions We are making the lives of people who travel easier and more enjoyable while constantly developing new, intelligent mobility solutions. Your new tasks Exciting and future oriented Design responsibility for complete DC Traction Power Supply Equipment within a project with reference to ANSI/IEEE Standards. Preliminary and detail design of DC Traction Power Supply (TPS) substations for electrical railway system. Preparation of detailed electrical engineering drawings of electrical systems and components incl. SLD, general arrangement drawings and overviews, bill of materials, etc. Technical design interface between sub-systems of all DC Traction Power Supply Equipment within the substation review and release of complete DC substation design in each project phase Technical management, planning and controlling of own engineering work package Interaction with sales departments and project management during both, the bid phase, and the project realization phase Technical clarifications with sub-suppliers abroad. Technical support of the manufacturing and the commissioning engineers concerning analysis of technical problems and answering of technical inquiries Participation in technical liaison meetings with customers, suppliers, and Siemens internal departments overseas Your qualification Well-grounded and adequate Design responsibility for complete DC Traction Power Supply Equipment within a project with reference to ANSI/IEEE Standards. Preliminary and detail design of DC Traction Power Supply (TPS) substations for electrical railway system. Preparation of detailed electrical engineering drawings of electrical systems and components incl. SLD, general arrangement drawings and overviews, bill of materials, etc. Technical design interface between sub-systems of all DC Traction Power Supply Equipment within the substation review and release of complete DC substation design in each project phase Technical management, planning and controlling of own engineering work package Interaction with sales departments and project management during both, the bid phase, and the project realization phase Technical clarifications with sub-suppliers abroad. Technical support of the manufacturing and the commissioning engineers concerning analysis of technical problems and answering of technical inquiries Participation in technical liaison meetings with customers, suppliers, and Siemens internal departments overseas