Senior/Principal ASIC Design Verification Engineer (SoC/Subsystem)

Summary:

Lead hands-on verification of complex SoC or large subsystems using UVM/SystemVerilog, owning plan-to-close execution through tapeout and silicon correlation.

Responsibilities:

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  Author verification plans from specs and micro-architecture; build reusable UVM environments from scratch at subsystem or SoC level.
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  Develop constrained-random and directed tests, scoreboards, checkers, coverage models, and assertions (SVA).
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  Drive coverage closure (functional, code, assertion), root-cause complex bugs, and work closely with RTL, architecture, and DFT.
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  Enable SoC-level verification including interface/IP integration, coherency, low-power modes, resets/boot, and performance validation.
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  Support silicon bring-up and correlation of failures to pre-silicon environments.

Must-have qualifications:

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  8+ years of hands-on ASIC verification experience (FPGA or emulation-only work does not count toward the 8 years).
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  Multiple production ASIC tapeouts with ownership of SoC or subsystem-level UVM environments and coverage closure.
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  Expert in SystemVerilog, UVM, SVA, and constrained-random methodologies; strong debug skills with waveforms and logs.
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  Experience verifying standard interfaces and complex subsystems (AXI/ACE, DDR/PCIe, coherency, memory/interrupt fabric, power states).
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  Strong testplanning, stimulus strategy, checkers/scoreboards, and closure discipline.

Nice to have:

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  Low-power verification (UPF-aware), performance/latency verification, firmware-aware verification, emulation acceleration as a complement to UVM.
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  Scripting (Python/Tcl) used to enhance hands-on verification, not in lieu of it.

Discounted / not counted experience:

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  Regression running/triage-only roles or lint/CDC-only roles are discounted.
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  IP-level-only verification without subsystem/SoC integration responsibility is insufficient.
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  Primarily management, methodology-only, or tool-maintenance roles without recent hands-on testbench development will be discounted.
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  FPGA-based validation experience does not count toward the minimum.