Generate test benches and test cases. Perform RTL and gate-level SDF-annotated simulations and debug. May perform mixed-signal (digital + analog) simulations and debug. Interact with our application engineers and provide guidance to customers. Participate in the generation of data books, application notes, and white papers. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Understand tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views. Write RTL Code, with solid Verilog, PERL, and Python skills, and TCL is a good addition. Understand static timing analysis and synthesis, DFT/ATPG skills would be a plus. Knowledge of any high-speed communication protocol is not mandatory but an asset. Previous knowledge in customer support and/or silicon bring-up is a plus. The Impact You Will Have: Strengthen and develop forecasting capabilities based on improved monitoring capacity. Ensure high-quality and reliable silicon lifecycle monitoring solutions. Enhance quality assurance methodology by adding more quality checks/gatings. Support internal tools development and automation to improve productivity across ASIC design cycles. Work with design engineers on new tools/technology and new features evaluation and adoption. Contribute to the successful and smooth operation of the engineering teams. What You'll Need: Bachelor's or master's degree in electrical engineering or a related field. 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design.

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of Processors or ASICs. Minimum 3+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug Formal verification experience

* Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. * Collaborate with cross-functional teams to achieve design goals. * Close the design to meet timing, power, and area requirements. * Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. * Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

Fundamental Knowledge of VHDL: Understanding of VHDL programming basics and digital design principles. Familiarity with Design Tools: Basic exposure to tools such as AMD Vivado and SDK, with some knowledge of Petalinux, Verilog, and Intel Quartus. Introductory Experience in Interface Design: Understanding of high-speed interface concepts, cross-clock domain interactions, and the creation of simple test benches. Synthesis and Debugging Awareness: Basic understanding of synthesis processes and an introduction to debugging tools like ILA and Signal Tap for high-speed designs. Knowledge of Embedded Systems: Familiarity with embedded processor architectures and programmable logic. Hands-On Experience in Debugging: Basic skills in on-board debugging, troubleshooting mixed-signal designs, and understanding interface protocols like SPI and I2C. Interface Protocols Understanding: Introductory knowledge of Ethernet, PCIe, and LVDS interfaces. Programming Skills: Basic command of programming languages such as C and C++. Measurement Equipment Familiarity: Introductory experience with oscilloscopes and logic analyzers. Interest in Advanced Topics: Enthusiasm for learning about radar module design and high-speed memory interfaces

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We craft the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by crafting, developing and testing some of the most sophisticated ASICs being developed in the industry. You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact You will contribute to developing Ciscos progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include: Architect block, cluster and top-level DV environment infrastructure. Develop DV infrastructure from scratch. Maintain and improve existing DV environments. Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus. Ensure complete verification coverage through implementation and review of code and functional coverage. Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist. Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance. Support testing of design in emulation. Lead all aspects of and manage the ASIC bring-up process. Minimum Qualifications Bachelors Degree or equivalent experience in EE, CE, or other related field. 7+ years of related ASIC design verification experience. Proficient in ASIC verification using UVM/System Verilog. Proficient in verifying sophisticated blocks, clusters and top level for ASIC. Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes. Scripting experience with Perl and/or Python. Preferred Qualifications Masters Degree in EE or CE with 5+ years of relevant work experience. Experience with Forwarding logic/Parsers/P4. Experience with Veloce/Palladium/Zebu/HAPS. Formal verification (iev/vc formal) knowledge. Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, TCP).

This position is in a cutting-edge synthesis product, in the area of Logic synthesis and Optimization. The candidate will be required to work on enhancing the optimization flow for performance, power, area (PPA) or runtime. This will involve identifying the opportunity for improving PPA, proposing a good solution/algorithm, implementing it, thoroughly testing it, and supporting it post-deployment. Job Requirements 1. 3+ years of work experience in EDA, preferably in logic optimization and logic synthesis. 2. Strong software skills: minimum 5 years of coding experience in C++. 3. Proficiency in data structures and algorithms. 4. Strong analytical and problem-solving skills. 5. Good understanding of chip design flow. 6. Must be a team player, clear in written and oral communication skills and open to work with diverse teams across multiple time zones. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Role & responsibilities Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment

12+ years of experience in ASIC design Proficient in Verilog coding, RTL design and complex control path and data path designs Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints Experience in writing Verilog testbench and running simulations.

We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other s success, and are passionate about technology and innovation. Qualifications: BE/BTech/ME/MS/MTech Job Responsibilities: Experience: 15+yrs Candidate must be able to generate RTL/handle scalable designs up to 48 billion Gates. Should be able to modify/update the designs to stress Flip-Flops/Wires/Gates/Input Outputs. Should be able use various available scalable compile/Runtime flows for large scalable designs. Should be able to profile and identify the slow performance areas and work with R&D on enhancements. Should be proficient in Verilog/ System-Verilog, scripting and exposure to Emulation platform is a must.

We are seeking a highly skilled and motivated STA Synthesis Engineer to join our offshore development teams . The ideal candidate will have expertise in static timing analysis (STA) to ensure the timing integrity of digital integrated circuits. Develop and execute timing constraints, ensuring compliance with design specifications and performance goals. Prepare detailed STA reports, including analysis and recommendations for improvements. Provide training and support to junior STA engineers and team members Role & Responsibilities : - Timing Constraint Generation : Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design. - STA Setup : Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions. - Timing Analysis : Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). - Clock Domain Crossing ( CDC ) Analysis : Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues. - Multicycle Paths ( MCP ) and False Paths : Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints. - Timing Closure : Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues. - Clock Tree Synthesis ( CTS ) : Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter. - Post-Layout STA : Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure. - Timing Margins : Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation. - Report Generation : Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization. - Cross-Functional Collaboration : Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues. - Methodology Development : Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy. NOTE : Preferred resources holding valid regional work permits only

Job Description- Mandatory Skills 4+ Years of experience with React.js, including hooks, component design, and state management (Redux / Recoil) Strong knowledge of JavaScript (ES6+) Solid understanding of GraphQL and its ecosystem (e.g., Apollo Client, GraphQL Queries & Mutations). Hands on experience of unit testing and testing frameworks (Preferably Jest & RTL) Excellent communication skills Preferred Skills Knowledge of design patterns Working knowledge in Mapstruct, Spring Cloud Streams, Spring Contract Testing Experience in mobility frameworks like React-Native Experience in Java, Springboot,, JAXRS, Mybatis, PostgreAQL, Junit. Experience in build tools like Apache Maven, Webpack

Roles and Responsibilities Work in a team or individually to design, develop and test web based application Design, develop, test and document quality software to user and functional requirements within specified timeframes and in accordance with the best coding standards Generate rapid prototypes for feasibility testing Generate all documentation relevant to software operation Adhere to prescribed development systems, processes procedures and ensure efficient, effective, high-quality delivery Communicate effectively with all stakeholders Perform tasks as specified by the Delivery Lead/Team Lead Qualifications and/or Experience 4-5yrs of experience as a UI Developer with a strong focus on UI. Strong experience in development, design of User Interfaces using different Front end technologies and approaches - SSR, SPA, PWA Apps Strong work experience in React, Redux, Typescript, JavaScript, HTML5, CSS3 and related technologies who can analyze, and develop code. Good understanding of cross-browser, cross-platform, Server-side rendering, Micro Frontends Experience with RESTful API integration Experience with Microsoft Azure or other cloud environments Experience analyzing and tuning application performance Experience with unit testing using Jest and RTL. Strong Experience on UI Libraries like MUI, ANTD, PrimeReact or Similar library . Good understanding of web accessibility concepts. Good working knowledge of CI/CD environments, Git or similar version control tool Proven experience in user interface monitoring tools. Mandatory HTML5, CSS, JavaScript, Typescript REACT, Redux, React Router, Axios Testing Tools- Jest, RTL Cloud: Azure/AWS Highly Desirable: Next JS Micro Frontend PWA External External Roles and Responsibilities Work in a team or individually to design, develop and test web based application Design, develop, test and document quality software to user and functional requirements within specified timeframes and in accordance with the best coding standards Generate rapid prototypes for feasibility testing Generate all documentation relevant to software operation Adhere to prescribed development systems, processes procedures and ensure efficient, effective, high-quality delivery Communicate effectively with all stakeholders Perform tasks as specified by the Delivery Lead/Team Lead Qualifications and/or Experience 5+ of experience as a UI Developer with a strong focus on UI. Strong experience in development, design of User Interfaces using different Front end technologies and approaches - SSR, SPA, PWA Apps Strong work experience in React, Redux, Typescript, JavaScript, HTML5, CSS3 and related technologies who can analyze, and develop code. Good understanding of cross-browser, cross-platform, Server-side rendering, Micro Frontends Experience with RESTful API integration Experience with Microsoft Azure or other cloud environments Experience analyzing and tuning application performance Experience with unit testing using Jest and RTL. Strong Experience on UI Libraries like MUI, ANTD, PrimeReact or Similar library . Good understanding of web accessibility concepts. Good working knowledge of CI/CD environments, Git or similar version control tool Proven experience in user interface monitoring tools. Mandatory HTML5, CSS, JavaScript, Typescript REACT, Redux, React Router, Axios Testing Tools- Jest, RTL Cloud: Azure/AWS Highly Desirable: Next JS Micro Frontend PWA

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Deliver comprehensive training on VLSI Design and Verification, covering topics like Digital Design, Verilog/System Verilog, RTL Design, and UVM. Prepare, update, and structure course materials and assignments as per industry standards.

Semicon Technical Program Manager | Bangalore or Hyderabad | Experience: 7 to10 Years Are you a hands-on technical expert who thrives at the intersection of Digital Design and Program Leadership ? We're looking for a Semicon Technical Program Manager to drive end-to-end execution across high-impact SoC design programs. This is a billed, customer-facing role that goes beyond task trackingyoull own milestones, lead cross-functional sync-ups, and bring structure to complex digital engineering workflows. What You’ll Do: Drive technical coordination across RTL, DV, PD, and STA teams. Track and manage project milestones, deliverables , and dependencies. Lead technical meetings , ensuring alignment between engineering functions. Support internal leadership with timely status updates and reporting. Contribute to program governance , documentation, and issue resolution. What You’ll Need: 7–10 years of experience in Digital Design (preferably PD-focused). Solid understanding of RTL, DV , and Physical Design flows. Prior exposure to program or project management in a technical setting. Excellent communication and stakeholder management skills. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

Summary Established in 2001, EnSilica is a publicly listed company (LON:ENSI), designing industry leading, application specific integrated circuit chips (ASIC), for customers ranging from start-ups to blue chip companies, in industries including: automotive, medical, space and mobile technology companies. With its head office on Milton Park, Oxfordshire, and other offices in Bristol, Sheffield, Brazil (Porto Alegre) and India (Bangalore), EnSilica currently employs more than 160 people. We are looking for a very experienced verification engineer who can not only strengthen the team through their technical expertise but also bring leadership and grow the verification business within EnSilica. You will have a good understanding of different methodologies, but particularly SystemVerilog and UVM. Faced with a new project, you will have the ability to quickly assimilate the verification challenge and help define an effective and pragmatic verification strategy and gain the support of the end-customer for the chosen approach. You will need to understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process. Responsibilities Verification specialist working on customer and internal projects often as the verification lead. Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods. You would also be responsible for the development of a comprehensive verification strategy and plan, along with the architecting and development of the complete test environment. Active participation in the verification community to drive the introduction of new and effective techniques within our business to help solve the verification challenges faced by our customers. Close working with our customers to build a strong relationship that results in repeat business. Education / Key Skills / Experience BE/ME in Electronics /Computer Science 1 group University. 15+ years experience in industry working on a variety of verification projects. Extensive knowledge of verification methodologies particularly UVM and SystemVerilog. Strong experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog. Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests. Strong VHDL/Verilog RTL. Very good understanding of modern verification flows and methodologies and able to influence the EnSilica one toward continuous improvement Ideally you will be familiar with both Mentor Questa and Cadence Incisive tool and ideally some exposure to low power verification using UPF based flows A good understanding of functional safety and quality processes, to achieve ISO26262 or similar standards compliances will be considered as a strong plus Personality Excellent communication and interpersonal skills. Strong and effective presentation skills, able to operate at multiple levels including senior management. Self-motivated achiever who gains satisfaction from providing excellent customer service and has a can-do attitude. Happy to take ownership of problems and provide suitable solutions. Creative problem solving. Team player. Ability to work in a dynamic environment.

Alphawave Semi is looking for Senior Engineer I - ASIC Design to join our dynamic team and embark on a rewarding career journey. Analyze and assess problems. Apply quality principles and methodology in processes to enhance output. Assess new product designs to meet project and product requirements. Create engineering designs. Identify the design needs of clients. Manage disputes and conflicts. Manage product design and development to meet project and product requirements. Oversee Workplace Safety and Health Systems (WSH) for the company.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: Senior/lead DFT Engineer (SCAN) Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Minimum 8+ years of experience in Scan insertion and with good understanding of RTL • Should be able to understand DFT Architecture and perform Scan insertion • Good understanding of RTL • Good understanding of Pin Muxing • Debug S1/S2 violation during Scan insertion • Test point insertion • Support ATPG engineer to debug Scan ATPG DRC's and cove TekWissen Group is an equal opportunity employer supporting workforce diversity.

RoleFront-End RTL Design Automation Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a Senior CAD Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What You Need To Have Tech/B 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks Show more Show less

RoleSenior CAD Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a Senior CAD Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What You Need To Have Tech/B 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks Show more Show less

RoleASIC CAD Lead Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a ASIC CAD Lead Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What You Need To Have Tech/B 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks Show more Show less

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation.Proven expertise in analysing and resolving DRCs/TSVs .Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues.Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery .Hands on experience on industry standard tools used for DFT featuresProficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks.Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs.Excellent analytical and problem-solving skills, with a keen attention to detail.Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design * Experience working with ATE engineers for silicon bring up, silicon debug and validation. * Experience in processor flow and post silicon validation Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic multi-site CAD team at Qualcomm.Our team support Simulation, Emulation, Formal Verification and Post Silicon domains providing ample opportunities to grow and contribute. Responsibilities As a Design Automation Engineer, you will work with RTL, architecture, design, DV, software, and silicon verification users. Develops, maintains, debugs and tests CPU Design Methodologies using Commercial EDA tools Defines and creates flows/scripts to help design teams execute Front-End (RTL) flows seamlessly Create unit, integration, regression, and/or system-level tests to thoroughly validate new features or changes. Work closely with Eng IT teams to setup flows which work well with the Engineering Compute Infra at multiple Datacenters Work closely with design teams to define methodologies, drive flow development, and deploy vendor tools Interfaces with external vendors to define, drive and incorporate the latest design solutions to improve productivity and time to market. Support design engineers on the flow setup and resolve their queries, automate tasks through appropriate tools and scripting. Review and debug code to identify and fix code problems. Qualifications Proficient with Python development and strong working knowledge of Linux operating systems Must have worked on Digital flows/methodologies development in the DV domains. Should have proficient skills with one of DV related tools Xcelium/VCS/vManager/Indago/Verdi or equivalent. Experience with CI/CD platform (like Airflow and Jenkins) and Version Control System (like Perforce and/or Git). MS/BS in Electrical/Computer Engineering with 8-14 years of demonstrated experience in CAD or EDA tools flows architecture, development, and support. Demonstrated experience with various EDA software, flows, and architectures & driving EDA vendors to provide feature enhancements and bugfixes. Ability to document design methodologies & provide training on tools and workflows to design teams Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems

locationsIndia, Bangalore time typeFull time posted onPosted 30+ Days Ago job requisition idJR0270511 Job Details: About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum (must haves) Bachelor's degree in electrical engineering or computer engineering with 3 to 9 years of experience or a master's degree in electrical engineering or computer engineering. 6+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Building emulation models, enabling content Working with Validation Engineers and central CAD teams to support and maintain verification requirements in terms of Automation and tool flow support. Coordinating with Val team on CAD Requirement with support CAD, IT and Engineering Compute Teams. Act as focal point between design and tool vendors for issues and feature enhancements. Training/Supporting Validation Engineers in CAD tool flow and Infrastructure Monitoring and improve existing simulation environments and simulation efficiency. Experience with Performance Validation of GPUs and automation framework using Python is desirable Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *