806 Rtl Jobs - Page 6

Join one of India's most trusted Shopify tech partners and be a part of building the future of e-commerce storefronts. Twizhire is seeking individuals to join a leading e-commerce solutions company that empowers online growth for top brands through custom-built Shopify and Shopify Plus experiences. By prioritizing impact, empathy, and innovation, this company collaborates with brands from strategy to full-stack execution, enabling them to scale faster, better, and smarter. Location: Bangalore (Remote-friendly) What's in it for you - Lead front-end development for a top Shopify tech enabler, contributing to building real products at scale - Hold a high-ownership role with the freedom to architect, mentor, and innovate - Make a direct impact on live e-commerce journeys used by thousands daily - Collaborate with a sharp, values-driven team that emphasizes trust, empathy, and outcomes What You'll Do - Lead and mentor a team of 5-10 front-end developers - Drive sprint planning, architecture discussions, and performance reviews - Architect and develop scalable, modular front-end solutions in React & Next.js - Collaborate closely with UI/UX, backend, QA, and product teams - Ensure accessibility, mobile responsiveness, and WCAG compliance - Review code, guide refactoring, and enforce high standards across the board - Troubleshoot bottlenecks and continuously optimize performance - Keep the team updated with modern React trends and tools What Makes You a Fit - Minimum of 5 years of experience in front-end development; with at least 3 years hands-on experience with React.js & Next.js - At least 2 years of experience leading front-end teams of a minimum of 5 developers - Strong proficiency in JavaScript (ES6+), TypeScript, React Hooks, Context API, and Redux - Proficient in Styled Components, REST/GraphQL, and Next.js SSR optimization - Solid understanding of Git, testing frameworks (Jest, RTL), and CI/CD practices - Bonus if you have experience working with Shopify, Contentful, or a headless CMS - Passionate about frontend architecture, team culture, and performance tuning,

You will be responsible for developing and driving the Power Modelling and Estimation framework for highly optimized, modular, and scalable SoCs. Your main tasks will include working on power analysis, power optimization, simulation, and roll-ups. You should have hands-on experience with PTPX/Power artist and other industry standard power estimation tools. Additionally, you will collaborate with various SoC and IP teams on power projections and requirements, including silicon power capture and correlation with pre-si estimates. Data mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power estimation will also be part of your responsibilities. Minimum qualifications for this position include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a similar field, with at least 10 years of relevant work experience in consumer electronics or semiconductor companies. You should have a minimum of 5 years of experience with system design of small, medium, and large power management or power modeling systems, including hands-on experience with PTPX/Power artist tools. Preferred qualifications include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a similar field, with at least 12 years of relevant work experience. You should have a strong ability to manage multiple projects, grow knowledge and capabilities of the power team, and perform hands-on testing. A background in analog or digital power design would be advantageous. This role falls under the Experienced Hire job type and will be based in India, Bangalore. The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms. CCG aims to deliver purposeful computing experiences that unlock people's potential. As part of the largest business unit at Intel, CCG is investing heavily in the PC, ramping its capabilities more aggressively, and designing the PC experience more deliberately to deliver a predictable cadence of leadership products. By joining this team, you will have the opportunity to fuel innovation across Intel and help enrich the lives of every person on earth. Please note that the work model for this role will be eligible for a hybrid work model, allowing employees to split their time between working on-site at the Intel site and off-site. Kindly be aware that job posting details such as work model, location, or time type are subject to change.,

Location: IN field Sales Goodyear Talent Acquisition Representative: Aanchal Seth Sponsorship Available: No Relocation Assistance Available: Yes Identify, plan and develop new customers in line with business development plans/targets, Provide appropriate and agreed levels of contact, service and support to ensure sales targets are met 3 Monitor sales against agreed targets on a regular basis to ensure they are met and where necessary the need for remedial actions are identified, reported and implemented, Plans own visit schedule in line with agreed customer service levels for that customer segment, Collects reports and analyzes the customer feedback / information on present as well as future market trends in the context of possible further market penetration, Identifies, targets and implements the approved sales strategies in the assigned marketplace, Plans, executes and reports on the sales activities in the assigned sales area, Has expert knowledge on the features and benefits of available products/services, Goodyear is an Equal Employment Opportunity and Affirmative Action Employer All qualified applicants will receive consideration for employment without regard to that individual's race, color, religion or creed, national origin or ancestry, sex (including pregnancy), sexual orientation, gender identity, age, physical or mental disability, ethnicity, citizenship, or any other characteristic protected by law, Goodyear is one of the worlds largest tire companies It employs about 68,000 people and manufactures its products in 53 facilities in 20 countries around the world Its two Innovation Centers in Akron, Ohio and Colmar-Berg, Luxembourg strive to develop state-of-the-art products and services that set the technology and performance standard for the industry For more information about Goodyear and its products, go to goodyear/corporate

Job Description Experience Requirement: 3+ Years Company Overview: Iron Systems is an innovative, customer-focused provider of custom-built computing infrastructure platforms such as network servers, storage, OEM/ODM appliances & embedded systems For more than 15 years, customer have trusted us for our innovative problem solving combined with holistic design, engineering, manufacturing, logistics, and global support services, Job Description: Program management and Execution: End to end Project Planning, program management and coordination (Activities and Resources) Responsible for overall projects processes and deliverables Project on-boarding, daily tracking of performance, proactive communication, and escalation management CSAT: Drive highest level of customer satisfaction and be a customer reference-able account Zero Escalation: Issue Identification, Resolution and Stake holder Management Finance Management: Invoicing, Collection, Account Growth Experience in automation of projects Dashboards & Reporting: Project kick off, Weekly governance, Documentation, Reports and dashboard boards Stakeholder Management Partnership with Customers and Stakeholders with a Customer-focused mindset Process and Service Improvements & Identification of new business Process Consultancy and Improvement Project Initiation, Project Planning and Project Execution Participates in negotiating Service Level Agreements (SLAs) and Operational Level Agreements (OLAs) for the service Handling Change request in Project Management Maintain project documentation and course folders, SLAs, and PMS, Pro-actively report to senior management on all technical issues relevant to their area of responsibility Skills Required: Should possess an outstanding working experience of 3+ years with a bachelor's or masters degree in computer science/IT or other affiliated courses, Should have sufficient organizational skills and ability to carry out multiple and intricate tasks,

Division Department Employment Type Job Purpose To initiate and implement ESSA (Eliminate, Standardize, Simplify and Automate) in existing assets and new projects in core specialization of Electrical Engineering discipline, Accountabilities Standards & Procedures Design III Automation & Obsolescence Audits & Compliance Capability development Education Qualification Electrical Engineering from reputed University, Relevant Work Experience At least 8 -15 year of experience in Engineering roles preferably in Pharma Industry, Minimum 5 years of experience in performing Central Engineering roles preferably in Pharma Industry, Ability to implement new techniques, deep understanding of manufacturing process, planning and organizational skills, prioritization multi-tasking, understanding of financial concepts like CAPEX, OPEX etc, knowledge of automation Competencies/Skills Job Location Patalganga Shift Hours Diversity Requirement

Role & responsibilities: Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog /DFT Analog/PD Extensive experience in Back-end design Experience on Mentor Graphics EDA flow is an added advantage Responsible for development and support of Projects. Responsible for Debugging the source codes in Verilog, SV, and UVM. Responsible for Training Delivery and Support Preferred candidate profile Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design 4 to 15 years industry/teaching experience Good communication & presentation skill

Understand the design specification , PowerOn Specificatio Understand boot firmware and reset flow Develop skills in IBM BIST verification tools and apply them successfull Develop the verification environment and test benc Debug fails using waveform, trace tools and debug RTL cod Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Required technical and professional expertise 4+ years of experience in Design Verification - demonstrated execution experience of verification of logic block Strong in SoC verification Chip reset sequence and initialization. ( for SoA Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL Good programming skills in C/C++, Python/Per Exposure in developing testbench environment, write complex test scenario, debugging and triaging fail Hardware debug skills backed by relevant experience on project Exposure in developing testbench environment, write complex test scenario Good communication skills and be able to work effectively in a global team environmen Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plu Scripting Expertise backed up relevant experience in the sam Writing Verification test plan Functional and code coverage analysis and debug

Understand the design specification , Memory and Memory BIST engine connection Develop skills in IBM BIST verification tools and apply them successfull Develop the verification environment and test benc Debug fails using waveform, trace tools and debug RTL cod Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 4+ years of experience in Design Verification - demonstrated execution experience of verification of logic block Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIS Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL Good programming skills in C/C++, Python/Per Exposure in developing testbench environment, write complex test scenario, debugging and triaging fail Hardware debug skills backed by relevant experience on project Exposure in developing testbench environment, write complex test scenario Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the sam Writing Verification test plan Functional and code coverage analysis and debug

As a Logic Design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

Are you an experienced FPGA Engineer seeking a thrilling opportunity in the field of defence and aerospace technology Join TechFLUENT Solutions Pvt Ltd and become a part of the forefront of radar and FPGA development. As an FPGA Engineer (Firmware Development) with over 5 years of experience in FPGA design and firmware development, you will play a crucial role in the company's cutting-edge projects. Your primary responsibilities will include implementing FPGA-based firmware in VHDL/RTL, collaborating with Xilinx and Microsemi (Microchip) FPGAs utilizing Vivado and Libero tools, and working with various protocols such as SPI, UART, I2C, memory, and high-speed interfaces with FPGA. Additionally, you will be involved in system integration tasks like hardware debugging, lab testing, and FPGA implementation. We are looking for individuals with a strong background in VHDL/RTL FPGA design, hands-on experience with Xilinx and Microsemi FPGA platforms, and proficiency in FPGA development tools like Libero or Vivado. The ideal candidate should possess excellent analytical and problem-solving skills, with a bonus for experience in Radar or RF-based FPGA systems. Preferred qualifications include the ability to thrive in a defence environment. By joining our team, you can expect a competitive salary based on your experience, the opportunity to work on radar systems and high-speed interfaces, hands-on exposure to real-time projects, and a clear path for career growth in defence and aerospace technology. To apply for this position, please send your resume to prasad@techfluent.in with the subject "Application for FPGA Engineer at TechFLUENT Solutions Pvt Ltd." If you know someone who fits this role, feel free to like, share, or refer them to us. Join us in shaping the future of defence and aerospace technology!,

As a CPU/GPU/IP Implementation Methodologies Engineer, you will be responsible for developing innovative methodologies to implement high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tools to enhance the quality of results and streamline the implementation process. Your role will also involve contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs. You will work with industry-leading Synopsys tools like RTLA and Fusion Compiler to address critical design challenges. Collaboration with a global team will be essential to ensure staying ahead of technological advancements and design complexities. Your contribution will be crucial in driving continuous improvement in PPA and turnaround time (TAT) metrics. To excel in this role, you must possess deep knowledge of synthesis, timing closure, power optimization, and constraints management. Your experience with low-power, high-performance design at advanced nodes below 5nm will be valuable. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX is required to effectively carry out your responsibilities. Familiarity with scripting languages such as TCL, Perl, and Python will aid in performing tasks efficiently. A BS or MS in Electrical Engineering or a related field along with 9+ years of relevant experience is necessary to succeed in this position.,

As a Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on cutting-edge technologies such as circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and DSP systems to contribute to the launch of world-class products. Collaborating with cross-functional teams, you will develop innovative solutions and ensure performance requirements are met. To qualify for this role, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 8 years of Hardware Engineering experience. Alternatively, a Master's degree with 7+ years of experience or a PhD with 6+ years of experience in a related field will also be considered for this position. Your primary responsibility will be to develop next-generation SoCs for mobile products and their adjacencies. This role will involve working on all aspects of VLSI development, including micro architecture, platform architecture, front-end design, and design convergence. Additionally, you will oversee physical design and verification aspects to ensure the successful development of SoCs. Key responsibilities for this position include: - Full chip design for multi-million gates SoC - Digital design and development (RTL) - Managing IP dependencies and tracking front-end design tasks - Driving project milestones across design, verification, and physical implementations - Developing architecture and micro-architecture from specifications - Understanding various bus protocols like AHB, AXI, and peripherals such as USB, SDCC - Reviewing top-level test plans and ensuring timing closure - Post-silicon bring-up and debug experience - SoC integration exposure and challenges - Design verification aspects and SoC specification to GDS To excel in this role, you should have a minimum of 15 years of solid experience in SoC design, expertise in Synopsys Design Compiler Synthesis, formal verification with Cadence LEC, and working knowledge of timing closure. Strong communication and leadership skills are essential for effective collaboration with program applicants and mentoring a small to medium-sized group. Qualcomm is an equal opportunity employer committed to providing an accessible process for individuals with disabilities. If you require accommodation during the application/hiring process, please contact Qualcomm via email at disability-accommodations@qualcomm.com or their toll-free number. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security measures related to the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking employment directly with Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted. For further information about this role, please reach out to Qualcomm Careers directly.,

ACL Digital is searching for a skilled and experienced Static Timing Analysis (STA) Engineer to become a part of the growing VLSI team. If you possess expertise in timing analysis and have previously handled full-chip designs, we are interested in hearing from you. As an STA Engineer at ACL Digital, your responsibilities will include driving full-chip STA from RTL to GDSII, developing and verifying timing constraints (SDC) for intricate SoCs, conducting timing closure and sign-off utilizing tools such as PrimeTime, collaborating with RTL, physical design, and DFT teams for ECOs and timing fixes, as well as analyzing timing reports, debugging violations, and suggesting optimization strategies. The ideal candidate should have 5-10 years of hands-on experience in Static Timing Analysis, a proven track record in full-chip STA and timing sign-off, a strong understanding of timing constraints, multi-mode/multi-corner (MMMC) flows, familiarity with scripting languages (TCL, Perl) and STA tools (preferably Synopsys PrimeTime), and excellent analytical, debugging, and cross-team communication skills. This position is based in Pune/Bangalore and requires an immediate notice period. Join ACL Digital to be a part of a dynamic team delivering next-gen semiconductor solutions. You will have the opportunity to work on cutting-edge technology projects with top-tier clients globally.,

Responsibilities: * Collaborate with cross-functional teams on RTL design and verification. * Ensure compliance with industry standards and customer requirements. Health insurance Annual bonus Provident fund

SDE + Instructor (Computer Architecture) Experience: 3 - 5 Years Exp Salary: 15 to 25 LPA Preferred Notice Period: Upto 30 Days Opportunity Type: Office (Sonipat, Haryana) Placement Type: Full-time (*Note: This is a requirement for one of Uplers' Clients) Must have skills: Linux Device Drivers OR VLSI Design OR RTL OR Computer architecture OR Kernel Development About Newton School: Newton School Come be part of a rocket ship thats creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates.We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CREDs Kunal Shah, Flipkarts Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaan’s Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities: Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications: B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats How to apply for this opportunity? Easy 3 Step Process: Click On Apply and register or log in to our portal Upload updated Resume & complete the Screening Form Increase your chances of getting shortlisted & meet the client for the Interview! About Uplers: Our goal is to make hiring and getting hired reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant product and engineering job opportunities and progress in their career. (Note: There are many more opportunities apart from this on the portal.) So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you!

Skills: Billing Search for relevant government/private tenders (GeM, eProcurement sites), Download tender documents and study scope, terms, and eligibility, Coordinate with technical and sales teams to prepare documentation, Prepare and submit tender forms, EMDs, and supporting documents, Track tender deadlines, corrigendums, and submission status, Maintain tender submission records and files (both soft and hard copy),

SDE + Instructor (Computer Architecture) Experience: 3 - 5 Years Exp Salary: 15 to 25 LPA Preferred Notice Period: Upto 30 Days Opportunity Type: Office (Sonipat, Haryana) Placement Type: Full-time (*Note: This is a requirement for one of Uplers' Clients) Must have skills: Linux Device Drivers OR VLSI Design OR RTL OR Computer architecture OR Kernel Development About Newton School: Newton School Come be part of a rocket ship thats creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates.We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CREDs Kunal Shah, Flipkarts Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaan’s Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities: Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications: B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats How to apply for this opportunity? Easy 3 Step Process: Click On Apply and register or log in to our portal Upload updated Resume & complete the Screening Form Increase your chances of getting shortlisted & meet the client for the Interview! About Uplers: Our goal is to make hiring and getting hired reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant product and engineering job opportunities and progress in their career. (Note: There are many more opportunities apart from this on the portal.) So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you!

Company Description Colliers (NASDAQ, TSX: CIGI) is a leading global diversified professional services company, specializing in commercial real estate services, engineering consultancy and investment management With operations in 70 countries, our 22,000 enterprising professionals provide exceptional service and expert advice to clients For nearly 30 years, our experienced leadership with substantial inside ownership has consistently delivered approximately 20% compound annual investment returns for shareholders With annual revenues exceeding $4 5 billion and $99 billion of assets under management, Colliers maximizes the potential of property, infrastructure and real assets to accelerate the success of our clients, investors and people, Job Description Shall be responsible to ensure that the various kinds of drawings that are to be implemented are sound, feasible and financially optimal; and executed as per plan Support during preparation and finalization of MEP designs & drawings and interaction with DPR consultants, Qualifications Graduate of Electrical / Mechanical Engineering, masters preferably in Electrical /Mechanical engineering with minimum 15 years of experience in design IT & IES / Commercial / Industrial / Institutional buildings Exposure in BIM are preferred,

As a React Professional at YASH Technologies, you will have the opportunity to work with cutting-edge technologies and be part of a team dedicated to bringing real positive changes in an increasingly virtual world. Your responsibilities will include working collaboratively in a team or independently to design, develop, and test web-based applications. You will be expected to design, develop, test, and document quality software according to user and functional requirements within specified timeframes and coding standards. Additionally, you will be responsible for generating rapid prototypes for feasibility testing, creating all relevant software operation documentation, and adhering to prescribed development systems and processes for efficient and high-quality delivery. Effective communication with stakeholders and performing tasks as specified by the Delivery Lead/Team Lead are also key aspects of the role. To be successful in this position, you should have a minimum of 8 years of experience as a UI Developer with a strong focus on UI. You should possess strong experience in developing and designing User Interfaces using various Frontend technologies such as React, Redux, Typescript, JavaScript, HTML5, CSS3, and related technologies. A good understanding of cross-browser and cross-platform development, server-side rendering, micro frontends, RESTful API integration, and application performance tuning is essential. Experience with unit testing using Jest and RTL, as well as familiarity with UI Libraries like MUI, ANTD, PrimeReact, or similar, is required. Additionally, knowledge of web accessibility concepts, CI/CD environments, version control tools like Git, and user interface monitoring tools will be beneficial. Mandatory skills for this role include proficiency in Next.js, Node, Tailwind CSS, GraphQL, Fastapi, SOAP, Docker, Gitlab, and GCP. At YASH, you will have the opportunity to create a career path tailored to your aspirations while working in an inclusive team environment. Our Hyperlearning workplace embraces flexibility, emotional positivity, trust, transparency, open collaboration, and continuous learning. If you are looking for stable employment with a great atmosphere and ethical corporate culture, YASH Technologies is the place to be.,

Qualcomm India Private Limited is seeking a Systems Engineer to be part of the Engineering Group, specifically in the Systems Engineering department. As a Systems Engineer at Qualcomm, you will engage in researching, designing, developing, simulating, and validating systems-level software, hardware, architecture, algorithms, and solutions. Your work will contribute towards the development of cutting-edge technology, enabling next-generation experiences and driving digital transformation. Collaboration across functional teams is essential to meet and exceed system-level requirements and standards. The ideal candidate should possess a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field with a minimum of 3 years of Systems Engineering experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with at least 1 year of experience in the same field would also be considered. The job overview includes working with Qualcomm's security architecture/IP and access control team on developing next-generation SOCs for various product categories such as smartphones, tablets, automotive, and IoT. Responsibilities involve assisting product development teams in applying secure hardware design principles at different levels, including individual blocks, computing cores, and SoCs. Experience in software/hardware co-design and familiarity with debug architectures like JTAG and ARM coresight are advantageous. Candidates should have 5 to 7+ years of industry or academic experience in Security, along with expertise in areas such as computer architecture, mobile platform security, ARM TrustZone, operating system security, programming languages like C/C++, Python, RTL, and teamwork across different teams and locations. Strong communication skills in English, both verbal and written, are essential. Preferred qualifications include skills/experience in ARM architecture SoC security design, applied cryptography, trusted computing, hardware firewalls for access control, knowledge in AI/ML, FPGA/ASIC design using SystemVerilog, VHDL, Verilog, SystemC, and familiarity with memory and storage technologies. Educational requirements include a Bachelor's degree or above in Computer Engineering and/or Electrical Engineering. Experience-wise, a Bachelor's or Master's degree with 5-7+ years of Systems Engineering experience is preferred. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities during the application/hiring process. They expect employees to adhere to all policies and procedures, including security measures for protecting confidential information. Staffing and recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes. For more information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is seeking an individual to join the Engineering Group, specifically in the Hardware Engineering department. As part of this role, you will be responsible for creating power specifications for Qualcomm DSP IPs based on the design specifications provided. Your tasks will include developing power intent using UPF for DSP IPs, as well as validating power intent at both RTL level and Gate level (synthesis, PD) using CLP. In addition, you will be required to fix any power intent issues based on PA DV feedback and debug problems related to MV cell insertion during synthesis by modifying UPF accordingly. Another aspect of the role involves projecting dynamic and leakage power of DSP IPs at the beginning of the project and generating dynamic and leakage power numbers using PTPX. It will be your responsibility to track these numbers at different stages of the implementation flow, highlighting any issues related to dynamic and leakage power mismatch compared to the target. You will collaborate with Synthesis and PD teams to resolve these issues effectively. Furthermore, you will work closely with cross-functional teams such as SOC, Sub System, etc., to ensure a smooth handoff of power intent and dynamic & leakage power numbers at various stages of project execution. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering or related work experience. OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering or related work experience. OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualcomm is an equal opportunity employer that is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact Qualcomm at disability-accommodations@qualcomm.com or call the toll-free number provided on the Qualcomm website. Employees at Qualcomm are expected to adhere to all applicable policies and procedures, including those related to security and the protection of company confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities directly with Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted. For more information about this role, please reach out to Qualcomm Careers directly.,

Creating power specifications for Qualcomm DSP IPs based on the design specifications is a key responsibility in this role at Qualcomm India Private Limited. You will be required to develop power intent using UPF for DSP IPs based on the power specifications provided. Additionally, you will need to validate the power intent at RTL level and Gate level (synthesis, PD) using CLP. In case of any issues related to power intent, you will be responsible for fixing them based on PA DV feedback. Another aspect of the role involves debugging issues related to MV cell insertion during synthesis and modifying UPF accordingly. You will also be tasked with projecting dynamic and leakage power of DSP IPs at the beginning of the project and generating dynamic and leakage power numbers using PTPX. It will be important to track these numbers at different stages of the implementation flow. An essential part of the role is to highlight any issues related to dynamic and leakage power mismatch compared to the target. You will collaborate closely with Synthesis and PD teams to address and rectify these issues. Furthermore, working with cross-functional teams (SOC, Sub System, etc.) for a seamless handoff of power intent and dynamic & leakage power numbers at various stages of project execution will be a significant aspect of the job. Qualcomm is seeking individuals with a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 6 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 5+ years of experience or a PhD with 4+ years of experience in the relevant field will also be considered. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. For inquiries related to reasonable accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com.,

AlphaGrep Securities Private Limited is a proprietary trading firm that specializes in algorithmic trading across different asset classes worldwide. By utilizing technology, risk management, and quantitative research, we effectively cover global markets. With a notable trading volume on Indian exchanges and a significant market share on various global exchanges, we employ a disciplined and systematic quantitative approach to identify alpha-generating factors. These factors are combined with our proprietary ultra-low latency trading systems and robust risk management to develop trading strategies across equities, commodities, currencies, and fixed income asset classes. We are currently seeking a full stack FPGA developer with a minimum of 3 years of industry experience in hardware development to assist us in expanding our hardware platform for low latency trading. The selected candidate will play a crucial role in all stages of hardware development at AlphaGrep and will be tasked with designing and constructing FPGA-based trading systems for our most latency-sensitive strategies. **Responsibilities:** - Designing, implementing, testing, integrating, and delivering low latency trading systems. - Developing low latency designs in Verilog/System Verilog. - Creating test harnesses for verifying developed items using self-checking test benches, BFMs, etc. - Integrating the developed firmware on the target hardware with other system components and software. - Releasing developed items. - Contributing to peer design reviews. - Conducting requirements capture. - Operating in a fast-paced, feedback-driven development environment. - Ensuring adherence to company values, policies, and ethics codes of conduct. - Undertaking any other activities as reasonably requested by management. **Qualifications & Skills:** - Degree in electronics/engineering or equivalent experience. - Strong design standards and debugging skills. - Hands-on experience in digital design and FPGA architecture. - Excellent problem-solving and analytical abilities. - Understanding of digital hardware design. - Proficiency in developing self-checking testbenches and BFMs. - Familiarity with software, networking, digital communications protocols, and general networking. - Experience with large Altera and Xilinx FPGAs. - Proficiency in writing RTL in Verilog/System Verilog or VHDL. - Working knowledge of engineering tools such as Vivado and Questasim. - Experience in a Linux-based development environment. - Scripting skills in tcl/tk, Python. **Why You Should Join Us:** - Great People: We are a team of curious engineers, mathematicians, and statisticians who enjoy achieving our goals while having fun. - Transparent Structure: We value the ideas and contributions of our employees. - Relaxed Environment: Our flat organizational structure offers various activities for all employees, including yearly offsites, happy hours, and corporate sports teams. - Health & Wellness Programs: We believe in supporting a balanced lifestyle for our employees through perks like a stocked kitchen, gym membership, and generous vacation packages.,

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is seeking a motivated memory subsystem architects with great analytical skills and a deep understanding of system architecture and performance, to work with a team to model, debug and analyze performance issues in the Memory subsystem. What you will be doing: Contribute to advancing GPU Architecture and Simulators, GPU testing infrastructure, metrics, and/or compilers. Performance modeling and simulation of features to improve memory system efficiency. Develop test plans and testing infrastructure. Debug tests on architecture simulators. Performance analysis/ bottleneck analysis of sophisticated, Memory subsystem units and features. Work on hardware models of different levels of extraction, including performance models, RTL test benches and emulators to find performance bottlenecks in the system. Working with various multi functional teams like ASIC design and verification.. What we need to see: Master/Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering or related field (or equivalent experience). 5+ years experience dealing with system level architecture and performance issues. Strong programming ability in C, C++. Exposure to Verilog/System Verilog is a strong plus. Good understanding of Memory subsystem architecture, caches , MMU, memory controller, NOC / interconnects, computer architecture. Debugging and analysis, including use of RTL dumps to debug failures. Exposure to performance simulators, cycle accurate/approximate models or emulators for pre-silicon performance analysis is a plus. Strong communication and interpersonal skills are required along with the ability to work in a dynamic, product oriented, distributed team. Ways to stand out from the crowd: Knowledge of the memory system, caching, interconnects, DRAM controller, Memory management unit, performance modeling and analysis. Widely considered to be one of the technology world's most desirable employers. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, perform essential job functions, and receive other benefits and privileges of employment. #LI-Hybrid

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are looking for a Senior Engineer for our Build and Release Methodology Group catering to our pioneering SOCs. As the SOC development becomes more complex requiring packing of more and more IPs and the need for doing more SOCs increase, we need to have a scalable infrastructure to be able to complete SOC development in fastest as well as most efficient way possible. This requires an SOC Build and IP Release infrastructure that caters to and keeps up with these ever-increasing complexities. In this position, you will work first-hand on architecting and developing this methodology. If you have real passion for methodologies and automation solutions, you will fit in great! What you'll be doing: Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner. Architect and implement core build flows so as to optimize build and make it simpler and efficient. Improve build, release, and integration tools and procedures. Identify and develop Checks to enforce the best practices for the Build and Release guidelines. Develop solutions to enable abstraction and compartmentalization for customer IPs. Identify difficulties and inefficiencies in the SOC implementation process and propose ideas to solve them. Support IP teams with Build and Release related issues. What we need to see: BS or MS in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent experience. 5+ years of industry experience as Build and Release Engineer, Build Automation, IP integration and related areas. Strong coding skills in Perl, Python, Makefile, Shell script, or other industry-standard scripting languages. Excellent analytical and problem-solving skills. Excellent interpersonal skills to work with multi-functional teams and collaborate with team members across sites and cultures to build consensus. Background in RTL (Verilog), Verification (UVM, System Verilog) and C/C++ is a plus - Not must. Experience in synthesis and physical design is a plus - Not must. #LI-Hybrid