806 Rtl Jobs - Page 7

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. . Required education Master's Degree Preferred education High School Diploma/GED Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design,

Formal Verification Implementation and maintenance of Formal Verification environments in Chisel Applying various FV techniques to reduce complexity and prove correctness of DUT. Debugging RTL to identify causes of failure scenarios. Guide and train team members on effective usage of Formal Verification tools Develop/modify scripts to automate the verification process. Review formal setups and proofs with design and verification teams. Maintain and extend assertion libraries. 7+ years of experience in Formal Verification of Digital Hardware Design Extensive experience with Formal Abstraction Techniques and sign-off process Familiarity with industry-standard Formal Verification Tools, such as VC Formal, Jasper Gold Knowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ System Verilog Knowledge of Object-oriented Programming is a plus.

RTL Design Engineer 4+yrs experience Location: Hyderabad_onsite Malayasia Advanced RTL Design and DFT trainee, looking forward to build a career in the VLSI domain. To work with full determination and dedication, to achieve organization as well as personal goals. Skills : Verilog, Design for Testability (DFT), RTL Coding, STA, System Verilog, C, FPGA design Hands-on experience : Router 1x3 - Design using Verilog, RISCV32I Processor- RTL Design and DFT

7-15 years of experience in static timing analysis for digital IC design. Strong understanding of digital design concepts, including flip-flops, latches, combinational logic, and clocking methodologies. Proficiency in using STA tools like Synopsys PrimeTime, Cadence Tempus, or similar tools. Experience with timing optimization techniques and methodologies. Knowledge of various design flows, including RTL design, synthesis, and physical design. Familiarity with scripting languages such as Perl, Python, or Tcl for automation of STA tasks. Strong analytical and problem-solving skills with attention to detail. Excellent communication skills to collaborate effectively with cross-functional teams.

Synopsys (India) Private Limited is looking for ASIC Digital Design, Staff Engineer to join our dynamic team and embark on a rewarding career journey Lead and execute complex engineering projects. Collaborate with cross-functional teams to develop innovative solutions. Mentor and guide junior engineers. Ensure compliance with industry standards and regulations. Conduct technical reviews and assessments. Identify and mitigate project risks. Maintain up-to-date technical documentation.

SILICON DESIGN ENGINEER 2 THE ROLE: As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence . THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem - solving skills and are willing to learn and ready to take on problems . KEY RESPONSIBILITIES: Drive formal verification for the block and write formal properties and assertions to verify the design Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design Responsible for verification quality metrics like pass rates, code coverage and functional coverage PREFERRED EXPERIENCE: Project level experience with design concepts and RTL implementation for same Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics Good understanding of computer organization/architecture ACADEMIC CREDENTIALS: Bachelor s or M aster s degree in computer engineering/Electrical Engineering #LI-PK1

SDE + Instructor (Computer Architecture) Experience: 3 - 5 Years Exp Salary: 15 to 25 LPA Preferred Notice Period: Upto 30 Days Opportunity Type: Office (Sonipat, Haryana) Placement Type: Full-time (*Note: This is a requirement for one of Uplers' Clients) Must have skills: Linux Device Drivers OR VLSI Design OR RTL OR Computer architecture OR Kernel Development About Newton School: Newton School Come be part of a rocket ship thats creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates.We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CREDs Kunal Shah, Flipkarts Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaan’s Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities: Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications: B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats How to apply for this opportunity? Easy 3 Step Process: Click On Apply and register or log in to our portal Upload updated Resume & complete the Screening Form Increase your chances of getting shortlisted & meet the client for the Interview! About Uplers: Our goal is to make hiring and getting hired reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant product and engineering job opportunities and progress in their career. (Note: There are many more opportunities apart from this on the portal.) So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you!

SDE + Instructor (Computer Architecture) Experience: 3 - 5 Years Exp Salary: 15 to 25 LPA Preferred Notice Period: Upto 30 Days Opportunity Type: Office (Sonipat, Haryana) Placement Type: Full-time (*Note: This is a requirement for one of Uplers' Clients) Must have skills: Linux Device Drivers OR VLSI Design OR RTL OR Computer architecture OR Kernel Development About Newton School: Newton School Come be part of a rocket ship thats creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates.We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CREDs Kunal Shah, Flipkarts Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaan’s Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities: Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications: B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats How to apply for this opportunity? Easy 3 Step Process: Click On Apply and register or log in to our portal Upload updated Resume & complete the Screening Form Increase your chances of getting shortlisted & meet the client for the Interview! About Uplers: Our goal is to make hiring and getting hired reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant product and engineering job opportunities and progress in their career. (Note: There are many more opportunities apart from this on the portal.) So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you!

SDE + Instructor (Computer Architecture) Experience: 3 - 5 Years Exp Salary: 15 to 25 LPA Preferred Notice Period: Upto 30 Days Opportunity Type: Office (Sonipat, Haryana) Placement Type: Full-time (*Note: This is a requirement for one of Uplers' Clients) Must have skills: Linux Device Drivers OR VLSI Design OR RTL OR Computer architecture OR Kernel Development About Newton School: Newton School Come be part of a rocket ship thats creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates.We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CREDs Kunal Shah, Flipkarts Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaan’s Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities: Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications: B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats How to apply for this opportunity? Easy 3 Step Process: Click On Apply and register or log in to our portal Upload updated Resume & complete the Screening Form Increase your chances of getting shortlisted & meet the client for the Interview! About Uplers: Our goal is to make hiring and getting hired reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant product and engineering job opportunities and progress in their career. (Note: There are many more opportunities apart from this on the portal.) So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you!

REQUIRED SKILLS: RTL Design Quality checks, mainly Lint Automation using Python and TCL 5years+ experience, so not an NCG KEY RESPONSIBILITIES: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency. Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Work with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) flows Requires a mix of SDC knowledge, EDA tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) PREFERRED EXPERIENCE: Worked with EDA tools that enable RTL quality checks Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Ability to multitask and grasp new flows/tools/ideas Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. ACADEMIC CREDENTIALS: Bachelor's degree or Masters degree with 5years+ experience.

Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together Location- Remote, Delhi NCR, Bangalore, Chennai, Pune, Kolkata, Ahmedabad, Mumbai, Hyderabad Education- B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics) 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles

We are seeking a Senior CAD Engineer with 10+ years of experience to join our team in Bangalore The ideal candidate will be responsible for deploying and supporting front-end tools such as RTL simulators, low power tools, and static RTL checkers They will also develop scripts to automate regression/debug flows, manage CI/CD processes, interface with EDA vendors, and support global teams across geographies Proficiency in scripting (Python, Bash, Makefiles), Linux system administration, and version control tools (Git, Mercurial) is essential Experience in ASIC flows and standard CAD tools is required Immediate joiners with a notice period of 15 days or less are preferred

Lead the architecture and RTL design of complex digital blocks and subsystems for ASICs or SoCs Develop RTL using Verilog/SystemVerilog to meet functional and performance specifications Review micro-architecture and provide design solutions optimized for power, performance, and area Work closely with the verification team to ensure thorough test coverage and efficient debugging Collaborate with synthesis, STA, and physical design teams for design closure

If you're looking for an exciting opportunity to work with a team of talented colleagues who enjoy both work and life, Westernacher is the perfect place for you, We are looking for SAP CO Experts for our growing team in India, Your Experience and Skills: 4+ years of relevant experience in SAP CO module Must have experience in Product Costing Should have worked on Margin Analysis (COPA) Must have experience working in Material Ledger Should have worked in Cost Center Accounting Experience in Intercompany Scenarios & Reporting must have worked on multiple S4 HANA implementation projects, Should have excellent client-facing, communication, and presentation skills, Should be willing to travel to the client site when required, Why Westernacher Inspiringandexciting, innovativeworking environment, Competitive remuneration package (salary, bonus, benefits), International company culture and minimal hierarchical structure, Chance to work on complex projects from different industries and add to your business process know-how, Flexible working hours and hybrid working model, This is WE: Committed to innovation,since 1969 Westernacher Consulting has operated worldwide, with more than 1200 consultants in Europe, Asia, and the Americas Headquartered in Heidelberg, Germany,Westernacher Consultingis the global leader in business process and technology innovation, Living, working, and operating in partnership We are inquisitive, creative thinkers with a strong entrepreneurial spirit We question new ways of working, think differently, and are willing to try out new approaches to create value and innovation for our customers All of this makes us pioneers in our field and keeps us responsive, quality-focused, and results-oriented, Westernacher is a diverse work environment and is proud to be an equal opportunity employer All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetics, disability, age, or veteran status Westernacher is also committed to compliance with all fair employment practices regarding citizenship and immigration status, Life@Westernacher

If you're looking for an exciting opportunity to work with a team of talented colleagues who enjoy both work and life, Westernacher is the perfect place for you, We are looking for SAP CO Experts for our growing team in India, Your Experience and Skills: 4+ years of relevant experience in SAP CO module Must have experience in Product Costing Should have worked on Margin Analysis (COPA) Must have experience working in Material Ledger Should have worked in Cost Center Accounting Experience in Intercompany Scenarios & Reporting must have worked on multiple S4 HANA implementation projects, Should have excellent client-facing, communication, and presentation skills, Should be willing to travel to the client site when required, Why Westernacher Inspiringandexciting, innovativeworking environment, Competitive remuneration package (salary, bonus, benefits), International company culture and minimal hierarchical structure, Chance to work on complex projects from different industries and add to your business process know-how, Flexible working hours and hybrid working model, This is WE: Committed to innovation,since 1969 Westernacher Consulting has operated worldwide, with more than 1200 consultants in Europe, Asia, and the Americas Headquartered in Heidelberg, Germany,Westernacher Consultingis the global leader in business process and technology innovation, Living, working, and operating in partnership We are inquisitive, creative thinkers with a strong entrepreneurial spirit We question new ways of working, think differently, and are willing to try out new approaches to create value and innovation for our customers All of this makes us pioneers in our field and keeps us responsive, quality-focused, and results-oriented, Westernacher is a diverse work environment and is proud to be an equal opportunity employer All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetics, disability, age, or veteran status Westernacher is also committed to compliance with all fair employment practices regarding citizenship and immigration status, Life@Westernacher

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor core/cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design -Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements.

We are seeking highy motivated individuas with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to hande the chaenging probems in future technoogies and designs. We are aso ooking for candidates with Strong C/C++background to ead our eading-edge agorithmswithin our EDA soutions to increase our design team’s productivity and chip quaity and performance. Our dynamic goba team is ooking to enist enthusiastic professionas to join word-cass hardware design teams responsibe for deveoping the most chaenging and compex systems in the word. We are seeking energetic, highy motivated individuas wiing to go the extra mie with the aim of heping the overa IBM deveopment team. Strong interpersona skis are needed to coordinate deiverabes and requirements from severa areas within and outside of the organization.There are many opportunities to gain and utiize a deep understanding of future issues and provide input towards decisions affecting system deveopment, ogica and physica design as we as sophisticated methodoogy directions. Individuas who are chosen to become a part of our word cass deveopment teams wi be heping advance IBM’s eadership in deveoping the highest performing computers and changing hardware soutions. Do you want to be an IBMerCome THINK with us! Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise 4+ years of IT experience Strong C/C++programming skis in a Unix/Linux environment is a must. VLSI knowedge, Knowedge in front end inting toos and checkers and RTL Checkers. Great scripting skis – Per / Python/She Proven probem-soving skis and the abiity to work in a team environment are a must Preferred technica and professiona experience RTL Lint Checkers , Front end verification fow, VLSI knowedge, VHDL/Veriog, computer architecture

As a Logic design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers.Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLLAdditiona responsibiities:ogic (RTL) design, timing cosure, CDC anaysis etc.Understand and Design Power efficient ogic.Agie project panning and execution.Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise Minimum 8+ years of experience in Chip design and deveopment. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, mutipiers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Veriog

Expertise in ASIC or Digital physical design Expertise in RTL2GDSII physical design flows development (SNPS tool suite) Expertise in PD tool expertise (SNPS based - both construction & sign-off) Expertise in Cadence tools especially Innovus / Voltus Expertise in Python, Tcl, Shell programming skills Expertise in sign-off reports, triaging and root-cause analysis and suggest flow fixes Expertise in constraints / timing - STA. Expertise in full chip synthesis flow Expertise in PowerBI Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit Location - Bangalore, Beijing, Moscow, Taiwan, Vietnam

Eximietas is currently seeking a Senior Physical Design Architect with over 10 years of experience for a position in Hyderabad. The ideal candidate should hold a Bachelor's or Master's Degree in Engineering in Electronics, Electrical, Telecom, or VLSI Engineering. As a Senior Physical Design Architect, you will be working on designs ranging from 10nm to 5nm nodes with various customers. Your responsibilities will include solving critical design problems to meet performance, area, and power targets, developing placement, clock-tree synthesis, and routing methodologies, as well as providing training and technical support to customers. The successful candidate should have a strong background in place & route flow, including placement guidelines, clock-tree synthesis, routing, and timing optimizations. Experience with hierarchical designs, low power implementation, synthesis, floor plan design, static timing analysis, and physical verification activities such as DRC, LVS, and DFM is highly desirable. If you have the required experience and expertise for this role, please share your resume with us at maruthiprasad.e@eximietas.design.,

You Are: An experienced Emulation Engineer with Zebu experience. The Work: Port ASIC and IP RTL code to emulation platforms (Zebu). Build model from released RTL. Generate loadable image(s) for target emulation platform. Run sanity tests to qualify release of the image(s). Release the emulation models to various teams doing functional validation, firmware development and design verification. Assist debug of failures with stakeholder by providing instrumented models and captured waveforms extracted from emulation model. Coordinate with EDA and third-party tools team to validate implementation flows. Heres what you need: A minimum 2 years of experience in Emulation (Zebu) using System Verilog/Verilog/VHDL. A minimum of 2 years of experience with porting ASIC/IP RTL to Emulation platforms: Zebu. Unix/Linux development environments and scripting languages like TCL, Python, C++, C-shell. Logic simulation: VCS. Strong knowledge of Complete Design Cycle to understand the Different IP designs to integrate in the build. Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience). Bonus points if: Good knowledge of SoC design methodologies and technologies, with experience in the complete design validation cycle. Knowledge of key protocol’s like PCIe, USB, Ethernet, AMBA, UART, JTAG, I3C, DDR, flash memories and their usage in SoC environments. Experience with CPU integration is a big plus, especially ARM/RISC-V CPU. Knowledge of CoreSight/UltraSoC debug infrastructure integration. Familiarity with IO's such as MIPI CSI & DSI, USB, PCIE, LPDDR. SoC experience with bare-metal code.

Understand the design specification , TB architecture Learn in IBM Fusion and Trek verification languages and tools, apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of work experience in IP, Sub-system & SOC level - Exp in creating multiple UVM/SV based env from scratch, Strong in Block Level verification Exp in developing checkers, Scoreboards, Monitors, Test plan development, Code coverage, Functional coverage, FSM based design, System Verilog Assertions. Protocols SPI (Serial Peripheral Interface), AXI, AHB, APB, ETHERNET, I2C, JTAG, UART Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Preferred technical and professional experience Worked on Power Management blocks , Low Power, Boot & Reset sequences Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

As Logic Lead, you will be responsible for design and development of Compression, Security, and sustainability features for high performance Processors chips. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature Guide and mentor junior engineers. Represent as Design Lead in various forums. Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 10 to 15 years of work experience in one or more areas: Processor Architecture/ microarchitecture/ Logic design – Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. Experience in working with research, architecture/ FW/ OS teams Experience in low power logic design Experience in working with verification, validation for design closure including test plan reviews, verification coverage Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high-performance design and timing closure of high frequency designs Experience in silicon bring-up

We are seeking an experienced RTL Design Engineer to join our Digital Design team and contribute to the development of Aevas 4-D Lidar processing chip. The role involves implementing and integrating sub-components of the signal processing pipeline in ASICs and FPGAs, including filters, FFTs, and control logic. The engineer will be responsible for writing micro-architecture specifications, coding in SystemVerilog RTL, and validating Aeva-specific sub-components while ensuring functional safety, performance, and robustness. Collaboration with architects, design engineers, verification teams, and system software engineers is essential to meet SOC-level performance, power, and functionality goals. The ideal candidate will have over 10 years of experience in DSP design and implementation, expertise in AMBA protocols, and strong RTL coding skills. Additional experience in LPDDR, Ethernet, MIPI, high-speed SerDes, FPGA validation, pre/post-silicon bring-up, and diagnostics firmware development is highly desirable. This position offers an opportunity to work on cutting-edge lidar signal processing technology in a high-performance environment.