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R&D Engineering, Staff (Logic Synthesis)

R&D Engineering, Staff (Logic Synthesis)

Synopsys

3 - 8 years

15 - 30 Lacs

Noida Bengaluru

Posted:2 weeks ago| Platform:

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Skills Required

C++ Synthesis Verilog RTL

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Work from Office

Job Type

Full Time

Job Description

This position is in a cutting-edge synthesis product, in the area of Logic synthesis and Optimization. The candidate will be required to work on enhancing the optimization flow for performance, power, area (PPA) or runtime. This will involve identifying the opportunity for improving PPA, proposing a good solution/algorithm, implementing it, thoroughly testing it, and supporting it post-deployment. Job Requirements 1. 3+ years of work experience in EDA, preferably in logic optimization and logic synthesis. 2. Strong software skills: minimum 5 years of coding experience in C++. 3. Proficiency in data structures and algorithms. 4. Strong analytical and problem-solving skills. 5. Good understanding of chip design flow. 6. Must be a team player, clear in written and oral communication skills and open to work with diverse teams across multiple time zones. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Synopsys

www.synopsys.com

Software Development

Sunnyvale California

10001 Employees

617 Jobs

Key People

Aart de Geus

Co-CEO and Chairman
Chi-Foon Chan

Co-CEO and President
Sanjay Balakrishnan

Chief Financial Officer

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R&D Engineering, Staff (Logic Synthesis)

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R&D Engineering, Staff (Logic Synthesis)

Experience & Salary

Skills Required

Work Mode

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Job Description

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