455 Rtl Jobs - Page 19

• Well versed with the Timing Closure (STA), Timing closure methodologies • Pre/Post-layout constraint development to Timing Closure • Handshake with the Design team & Develop functional/DFT constraints • Abstraction expertise like Hyperscale/ILM/ETM Required Candidate profile • RC Balancing & scaling analysis of critical data paths of full chip clock • Automation in PERL, TCL and EDA tool-specific scripting • DMSA @ full chip and custom scripts for timing fixes

As a Logic design lead in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements:Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 3+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Responsibilities As a Logic design engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Good understanding of HW / SW co design / accelerators to enhance system level performance. Collaborate with the Chip development, Unit Verification, Physical design, testgen, millcode teams to develop the feature. Pre-Silicon:Signoff the Design that meets all the functional, area and timing goals. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise Experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core. Experience with VLSI Design in VHDL / Verilog logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution.

Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Understand the design specification , Memory and Memory BIST engine connections Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIST Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Hardware debug skills backed by relevant experience on projects Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , etc Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Responsibilities Lead the architecture, design and development of Processor Core Vector-Scalar Execution unit for high-performance IBM Systems. Architect and design Fixed point/Floating point/Vector/SIMD/Crypto instructions of a high performance processor CPU Develop the features, present the proposed architecture in the High level design discussions Estimate the overall effort to develop the feature. Estimate silicon area and wire usage for the feature. Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in post silicon lab bring-up and validation of the hardware Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing Execution unit of CPU Hands on experience of implementing Arithmetic/Crypto/SIMD functions Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Proficiency of RTL design with Verilog or VHDL Nice to haves Knowledge of instruction dispatch and load/store units Knowledge of verification principles and coverage High-level knowledge of Linux operating system Knowledge of one object oriented language and scripting language Understanding of Agile development processes Experience with DevOps design methodologies and tools Preferred technical and professional experience