806 Rtl Jobs - Page 5

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Mandatory Skills: RTL coding . Experience: 5-8 Years .

Job Description: What You'll Be Doing Familiarize with the latest technologies in FPGA and Acceleration domains like AI/ML by attending supplier trainings in person and via conference calls. Provide technical support and guidance to customers on RF and FPGA solutions. Troubleshoot and resolve customer issues related to RF and FPGA systems. Provide in-depth technical support to customers in their selection and use of Arrow PLD lines development tools, silicon and IP products that ensure design wins for Arrow. Code and implement designs to demonstrate capabilities of PLD silicon solutions and competitive advantages to secure design wins. Stay updated on the latest RF and FPGA technologies and trends. Drive demand creation by maximizing Arrow content on designs. Understand customer needs and leverage Arrow's engineering and design services resources to facilitate solutions for customers. Apply technical knowledge to influence designs utilizing solution selling. Be the first point of contact for customers in resolving any technical support issues while working with PLD silicon, tool and IP products, provide onsite technical support. Contribute to territory, account and opportunity plans and work as part of the Team Penetrate existing FPGA customers and position Arrow line card appropriately. Identify key relationships amongst decision makers within suppliers and customers. Team Collaboration: Work closely with Engineering & Marketing teams to resolve customer issues, product enhancements. Collaborate with field and factory resources to develop and deliver technical proposals to customer project managers, engineering managers, system architects and design engineers. Attend and actively participate in strategic branch meetings and QBR. Develop and drive strategic technical plans by supplier line or customer solutions. Partner with the sales team across pre-and post-sales activities, providing technical support and consulting to promote demand creation. Technical calibrations & research with sales & other Arrow depts. & Suppliers in support of the customer design. Provide regular feedback to supplier field sales and factory experts on the needs of the customers and align with corporate goals. What We Are Looking For BE/BTech/ME/MSc in Electronics and Telecommunications or equivalent Candidate with 2 to 3 years of related experience is preferred. Willing to Learn, Growth Mindset, Positive thinking, Open mind. Strong digital electronics fundamentals and in-depth knowledge of RTL (VHDL/Verilog/System-Verilog) Strong experience with RF designs, FPGA programming and Embedded systems. FPGA design experience including skills like board level debugging & troubleshooting hardware issues are a plus. Knowledge or Experience in software domains like Embedded Systems with C coding, OS concepts of Linux, model-based designs for Digital Signal Processing using Matlab Simulink are added advantage. Problem-solving skills and ability to drive issue resolution with cross-functional team. Strong interpersonal, written and verbal communication skills, strong presentation skills and ability to work in sales environment. Willingness and ability to travel North India for exploring new opportunities and supporting customer base of Arrow. Prior experience in a customer facing technical role is a plus. What's In It for You At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That is why we offer competitive financial compensation, including various compensation plans, and a solid benefits package. Insurance Bonus & Incentives Growth Opportunity & And more!

This job might be for you if You enjoy solving problems. You love taking on difficult challenges and finding creative solutions. You dont know the answer but will dig until you find it. You communicate clearly. You write well. You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference. You can impress our customers with your enthusiasm to solve their issues (and solve them!) Job Description Required Solid RTL coding experience including Microarchitecture of design System Verilog and Verilog coding using provided coding styles. Understanding of SDC Understanding STA reports and how to adjust RTL accordingly. Designing for error cases and debug of IP Understanding of CDC logic Knowledge of lint rules and exceptions Design and use of block level simulations to bring up IP. Knowledge of AMBA buses and when to use them. Job Description Preferred Experienceleading small design team. C coding / Firmware skills Knowledge on common processor architectures(ARM, RiscV) FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA. Lab brings up experience, scripting. Relevant tool experience such as: Socrates, Core Consultant in additionto standard simulation tools (xcellium, vcs, etc) Emulation experience(Zebu, Palladium, etc) Board knowledge, component selection, probing, debug. JTAG debugging experience (Coresight, Lauterbach, etc). Low power design techniques Qualifications E./B.Tech. degree at minimum.

Role & responsibilities Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners. • Own SDC constraint generation, validation, and refinement at top-level. • Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure. • Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimizations. • Conduct MMMC (Multi-Mode, Multi-Corner) timing analysis, including OCV, AOCV, and POCV variations. • Integrate timing reports from multiple blocks, perform hierarchical timing closure, and ensure sign-off compliance. • Work with DFT teams to analyze scan shift and at-speed test timing. • Automate report generation, violation tracking, and closure metrics using Tcl, Perl, or Python. • Provide guidance on timing budgets for IP/block owners. • Interface with foundries and EDA vendors to resolve tool and library issues.

Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively. Perform static timing analysis setup and sign-off for multi-corner, multi-voltage processes to align with PPA targets, initially at the hierarchical level and subsequently at the top-level, reviewing the timing arcs for the .lib generation. Collaborate closely with RTL, DFT, and IP teams to ensure smooth integration and address physical design concerns affecting scan shift and scan capture modes for DFT. Identify opportunities to optimize clock skew and insertion delay across various corners and modes. Evaluate the clock/reset-domain-crossing (CDC/RDC) issues at the netlisting stage and offer feedback on design fixes or establish waivers if the changes are not feasible. Implement power-saving strategies, such as power gating, multi-voltage domains, and clock gating, to meet low-power objectives while preserving performance standards. Create and refine custom scripts using Tcl, Perl, or Python to enhance workflow efficiency and streamline physical design operations. Mentor and support junior physical design engineers, disseminating best practices and providing technical guidance to elevate team proficiency and performance. PREFERRED EXPERIENCE: Over 8-10+ years of professional experience in constraints generation, synthesis, static timing analysis (STA), and IP-level timing and physical design, with a preference for high-performance SerDes designs. Proven ability in timing analysis, convergence, timing ECOs, and .lib generation. Experience with STA closure on PHYs & understanding the timing requirements across digital and analog macro interfaces is a plus. Proficient in physical design tools such as Synopsys ICC2, Primetime, and the ASIC design flow. Skilled in scripting with Tcl, Python, or Perl to automate and streamline physical design tasks. Excellent problem-solving, leadership, and communication skills and values team culture. Capable of thriving in fast-paced environments and managing multiple projects simultaneously.

Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 4+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details.

Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 4+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details.

If you have an experience developing RTL for IP or subsystems and understand architectural specifications, this role is for you. You will be responsible for IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. Key Responsibilities: Design of IP and subsystems with integration of AMD and other 3rd party IPs Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up Lead a subsystem development team of 4 to 5 members. Preferred Experience: 5-7 years full-time experience in IP hardware design Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Verilog lint tools (Spyglass) and verilog simulation tools (VCS) Clock domain crossing (CDC) tools Detailed understanding of SoC design flows Understanding of IP/SS/SoC Power Management(PM) techniques Power Gating, Clock Gating Experience with embedded processors and data fabric architectures (NoC) Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributedcomputeenvironment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts andSystemVeriloglanguage Good working knowledge ofSystemCand TLM with some related experience. Scripting language experience: Perl, Ruby,Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirableassetswith prior exposure to video codec system or other multimedia solutions.

The ideal candidate will get to work on Verification of complex Analog Mixed Signal IPs (with significant Digital and Analog content) that are delivered to various AMD SoCs. KEY RESPONSIBILITIES: Verification of IP features : Feature Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology-based (UVM) verification testbenches and components from scratch for various IP features. Quality deliverables through regressions Verification coverage: code-coverage, functional coverage, assertions, to achieve 100% verification completeness Reviews, and feedback to design/architecture teams. PREFERRED EXPERIENCE: Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions Expertise in code and functional coverage, Excellent Problem solving and debugging skills. Excellent Communication skills Strong digital design knowledge, SoC design flow Knowledge on AMS designs (SERDES or Memory PHYs such as DDR, GDDR) and Mixed signal verification methodology is an added advantage. UPF based RTL low power verification Prior experience in working on IPs with mixed signal content will be helpful. Prior experience of technical leadership will be an asset.

The ideal candidate for this role should possess a Bachelor's degree or equivalent practical experience along with a minimum of 2 years of experience in developing and maintaining STA constraints and scripts. It is essential to have prior experience working collaboratively in a team of DFT engineers, specifically with Register-Transfer Level (RTL) and Physical Designer Engineers. Preferred qualifications for this position include a Bachelor's or Master's degree in Electrical Engineering or Computer Science, or relevant practical experience. The candidate should have at least 6 years of experience in Static Timing Analysis with exposure to mixed signal design. Proficiency in flow methodology and development is highly desirable, as well as experience in coding using perl, python, and tcl scripting languages. Strong problem-solving and decision-making skills are essential for this role. As part of this role, you will be joining a diverse team dedicated to pushing boundaries and developing custom silicon solutions that drive Google's direct-to-consumer products into the future. Your contributions will be instrumental in shaping the innovation behind products that are beloved by millions globally, with a focus on delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. As a member of our team, you will have the opportunity to leverage the best of Google AI, Software, and Hardware to create revolutionary experiences that are profoundly helpful. Our work involves researching, designing, and developing new technologies and hardware to accelerate computing, ensuring that it is faster, seamless, and more powerful, ultimately aiming to enhance people's lives through innovative technology. Key Responsibilities: - Develop and maintain Static Timing Analysis (STA) and flow methodologies. - Create flow for custom/Analog and Mixed Signal (AMS) IP collateral, encompassing all view generation and QA checks. - Ensure timing closure for Place and Route (PnR) blocks. - Validate time constraint development. In this role, your expertise and contributions will play a crucial role in advancing the next generation of hardware experiences, contributing to a future where technology enhances and enriches the lives of individuals worldwide.,

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Compute Development Organization (CCDO) is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for an SOC RTL to PD Engineer to join the team. #azurehwjobs

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: RTL coding . Experience: 3-5 Years .

Job Title: React.Js. Engineer Job Description We're Concentrix. The intelligent transformation partner. Solution-focused. Tech-powered. Intelligence-fueled. The global technology and services leader that powers the world's best brands, today and into the future. We're solution-focused, tech-powered, intelligence-fueled. With unique data and insights, deep industry expertise, and advanced technology solutions, we're the intelligent transformation partner that powers a world that works, helping companies become refreshingly simple to work, interact, and transact with. We shape new game-changing careers in over 70 countries, attracting the best talent. The Concentrix Technical Products and Services team is the driving force behind Concentrix's transformation, data, and technology services. We integrate world-class digital engineering, creativity, and a deep understanding of human behavior to find and unlock value through tech-powered and intelligence-fueled experiences. We combine human-centered design, powerful data, and strong tech to accelerate transformation at scale. You will be surrounded by the best in the world providing market leading technology and insights to modernize and simplify the customer experience. Within our professional services team, you will deliver strategic consulting, design, advisory services, market research, and contact center analytics that deliver insights to improve outcomes and value for our clients. Hence achieving our vision. Our game-changers around the world have devoted their careers to ensuring every relationship is exceptional. And we're proud to be recognized with awards such as World's Best Workplaces, Best Companies for Career Growth, and Best Company Culture, year after year. Join us and be part of this journey towards greater opportunities and brighter futures. 1. Having 6+ years of experience and 5+ years of experience on React is a MUST 2. Working with latest React and Redux versions 3. Having experience in Both JavaScript as well as Typescript (MUST) 4.Unit Testing knowledge with JEST and RTL is a MUST 5. Having experience working with projects from inception, (So that we can decide to either go with Manual Project setup or with create react app command) 6. Knowledge of Java (Good to have) Location: IND Bangalore - 55, Divyasree Towers, Bannerghatta Main Road Language Requirements: Time Type: Full time If you are a California resident, by submitting your information, you acknowledge that you have read and have access to the

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

Lead a team of 5-10 resources Understand the design specification , PowerOn Specification Understand boot firmware and reset flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization. ( for SoA) Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Required Skills & Qualifications Bachelors or Master’s degree in Electronics, Electrical, or Computer Engineering. 8+ years of experience in FPGA design, prototyping, and RTL development. Expertise in RTL coding (Verilog/SystemVerilog/VHDL) and synthesis. Strong experience with FPGA platforms (Xilinx, Intel/Altera, Microchip). Hands-on with FPGA prototyping tools: Vivado, Quartus, Synplify, ModelSim, VCS. Knowledge of ASIC design flows, verification methodologies (UVM), and timing analysis. Debugging with logic analyzers, oscilloscopes, and FPGA debug tools (ILA/Chip scope). Strong analytical, leadership, and team collaboration skills.

You will be working as a DV, RTL, PD, DFT Engineer at Primesoc Technologies in Bengaluru. Your role will involve developing high-performance architectures of Digital IP controllers, ensuring the smooth functioning of devices with a focus on area, power, and performance factors. You should possess DV, RTL, PD, DFT skills and have experience in developing low power, high-performance architectures. Hands-on experience with FPGA validation and silicon realization will be necessary. Strong problem-solving and analytical skills are required for this role. Additionally, excellent written and verbal communication skills are essential. A Bachelor's or Master's degree in Electrical Engineering or a related field is preferred for this full-time on-site position.,

We are looking for a highly skilled Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team in Noida with a hybrid work model where you will be required to work 3 days in the office. As an ideal candidate for this role, you should have a minimum of 6 to 15 years of experience along with strong analytical skills, attention to detail, and the ability to collaborate effectively with cross-functional teams. Proficiency in EDA tools and digital design principles is a must-have for this position. Your key responsibilities will include working closely with SoC cross-functional teams to define and develop Synthesis & STA methodologies for advanced nodes such as 3nm, 5nm, and 16nm. You should possess a strong knowledge of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff. Experience with EDA tools like Genus, Fusion Compiler, PrimeTime, Tempus, and Conformal will be beneficial for this role. Additionally, strong scripting skills in Perl, TCL, and Python for automation and flow development are required. If you meet the above requirements and are excited about this opportunity, click on the Apply option or share your resume with Heena at heena.k@randstad.in.,

As a Senior ASIC Physical Design Engineer at Synopsys, you will play a crucial role in shaping the future of the semiconductor industry by driving innovations in IC design and physical implementation. Your expertise in high-performance digital design, low-power design, and high-speed clock design will be instrumental in developing cutting-edge solutions for creating high-performance silicon chips. You will collaborate with cross-functional teams to streamline the physical design process, enhance product offerings, and exceed customer expectations. Your responsibilities will include floor planning, developing timing constraints, physical synthesis, clock tree optimization, routing and extraction management, timing closure, signal integrity analysis, physical verification, and design for manufacturability (DFM) checks. By contributing to the development and enhancement of physical design flows for advanced technology nodes, you will drive innovation and improve efficiency in the physical design process. To excel in this role, you should have a solid understanding of IC design principles and physical implementation, experience with the full design cycle from RTL to GDSII, proficiency in deep sub-micron design flows, and hands-on experience with complex design projects and successful tape-outs. You should be a detail-oriented professional with strong analytical and problem-solving skills, an effective communicator, a proactive learner, a dedicated team player, and a creative thinker who can contribute to innovative solutions and improvements. You will be part of a dynamic and innovative team at Synopsys, dedicated to pushing the boundaries of IC design and physical implementation. Together, you will work collaboratively to address complex challenges and deliver exceptional results, driving the technological advancements that shape the future of the semiconductor industry. Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process. Join us at Synopsys to transform the future through continuous technological innovation and contribute to the growth of our innovative group.,

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilities: Expected to be an SME, collaborate, and manage the team to perform. Responsible for team decisions. Engage with multiple teams and contribute on key decisions. Provide solutions to problems for their immediate team and across multiple teams. Lead and mentor junior team members. Conduct code reviews to ensure code quality and adherence to coding standards. Professional & Technical Skills: Must To Have Skills: Proficiency in Emulation platform like Palladium/Zebu/Veloce/HAPS. Strong understanding of SOC Architecture Experience with debugging using any Emulation Palladium/Zebu/Veloce/HAPS platform. Hands-on experience with ARM (A/M) architecture. Knowledge of C language. Additional Information: The candidate should have a minimum of 5 years of experience in Emulation. This position is based at our Bengaluru office. A 15 years full-time education is required. Qualification 15 years full time education

- Lead the architecture, design and development of Processor Core Vector- Scalar Execution unit for high-performance IBM Systems. - Architect and design Fixed point/Floating point/Vector/SIMD/Crypto instructions of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise - 8 or more years of demonstrated experience in architecting and designing Execution unit of CPU - Hands on experience of implementing Arithmetic/Crypto/SIMD functions - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of instruction dispatch and load/store units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Master's Degree/PhD

You will be responsible for the following: - Holding a Bachelors or Masters degree in Electronics/Electrical Engineering - Possessing a minimum of 7+ years of experience in ASIC/IP Digital Design for large SOCs - Demonstrating expertise in implementing RTL in Verilog/SV for complex designs with multiple clock domains - Having expertise with various bus matrices on AHB, AXI, and NOC designs - Demonstrating experience in ARM processor and/or NAND Flash subsystems (preferred) - Experience in low power design methodology and clock domain crossing designs - Proficiency in Spyglass Lint/CDC checks, report analysis, and signoff - Experience in Synthesis using DC, timing analysis, and closure (preferred) - Expertise in Perl, Python, TCL language is advantageous - Ability to quickly ramp-up and collaborate effectively with Verification/Validation teams - Must possess a positive attitude and a solution-oriented approach - Excellent written and verbal communication skills Qualifications: - Bachelors degree with 7+ years experience, Masters degree with 6+ years experience, or PhD with 3+ years experience in CS, CE, EE, EC, or equivalent required.,

In this role, you will be responsible for developing and implementing user interface components in React.Js and Next.Js with workflows built using Redux, Context, etc. You will also work with Node.Js and Next.Js to create and maintain server-side functionality, such as building optimized APIs, Cron Jobs, etc. Furthermore, you will be tasked with profiling and improving application performance, as well as documenting the codebase. Your technical skills should include the ability to clearly understand requirements, translate them into technical requirements, and implement code effectively. You must have a strong proficiency in JavaScript, including DOM manipulation and the JavaScript object model, and proficiency in TypeScript will be beneficial. It is crucial to possess in-depth knowledge of the latest standards and industry frameworks of HTML and CSS, with a good understanding of creating accessible user experiences, implementing SEO, and graceful fallbacks for a wide range of supported browsers. You should also be capable of translating designs and wireframes into responsive designs accurately. Moreover, you should have a strong proficiency and experience in MERN Stack and Next.Js, with an understanding of the latest features and updates according to the frameworks" latest versions. A good understanding of common design patterns is essential, along with the ability to write optimized code compliant with coding standards considering scalability, reusability, and performance in mind. Troubleshooting and debugging skills are also crucial, as well as familiarity with UI libraries and popular React.js workflows. Additionally, you should be able to write secure Restful APIs with frameworks like Express, Apollo, GraphQL, etc., and have proficiency in version control systems like GIT. Your knowledge should extend to modern authentication and authorization mechanisms, various security protocols, and performing Unit tests and Point tests with tools like Jest, RTL, Sonar, Husky, Es lint, etc. Familiarity with modern build pipelines, DevOps strategies, and tools for design, tasks, code, and documentation management is also expected. Your responsibilities will include collaborating with various stakeholders to understand, develop, and deliver requirements, building reusable and optimized code and libraries, documenting code and design decisions, ensuring technical feasibility of UI/UX design, and guiding/mentoring junior developers. It is important to follow standards and best practices for application development, conduct peer code reviews, and empower junior developers with web development-related trends.,

As a Physical Design Engineer/Lead based in Noida, Ahmedabad, Bangalore, or Hyderabad, you will be responsible for leveraging your 5 to 15 years of hands-on experience in various aspects of physical design implementation. Your key responsibilities will include executing block-level physical design implementation from RTL to GDSII or Netlist to GDSII, ensuring block-level physical signoff, conducting block-level timing signoff and ECO generation, and overseeing block-level power signoff. Your role will also entail demonstrating proficiency in automation using tools such as Perl, Tcl, Awk, or Python. Additionally, you will be expected to offer technical guidance to a team of 4-6 junior engineers and have experience leading small project teams. Strong communication skills are essential as you will serve as the primary point of contact for clients. Please note that this role does not support work from home or remote work arrangements.,