As a Hardware at , you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today s market. Your role and responsibilities As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design - Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up ABOUT BUSINESS UNIT

Key Responsibilities Lead and manage all engineering functions across front-end and back-end VLSI design and verification. Define and execute engineering strategy aligned with company objectives and customer requirements. Drive excellence in RTL design, functional verification, DFT, physical design, STA, and sign-off processes. Build and mentor high-performing teams; attract, retain, and develop top VLSI engineering talent. Ensure timely delivery of high-quality project outcomes across multiple client engagements. Establish and enforce best practices, methodologies, and quality standards. Collaborate with business development and sales teams to support proposals and client interactions. Evaluate and introduce tools, technologies, and methodologies to enhance engineering productivity. Manage engineering budgets, resource planning, and project allocation. Foster a culture of innovation, ownership, and continuous improvement. Qualifications B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related field. 15+ years of hands-on experience in VLSI design and verification, including at least 5 years in senior leadership roles. Proven track record of managing large engineering teams and delivering complex SoC or ASIC projects. Deep expertise in design (RTL, synthesis) and verification (UVM, SystemVerilog, functional coverage). Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor, etc.). Strong leadership, communication, and organizational skills. Experience working with global clients or in multinational environments is a plus.

Job Details: : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, testcoverage, DPM, and testtime/vectormemory reduction goals as well as design integrity for physical implementation. Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure highquality integration of the IP block. Collaborates with postsilicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE. Qualifications: B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering with 7+ years of DFT experience Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Boeing India Engineering has an immediate opening for an Engineering Manager Digital Circuits , who will be responsible for development and management of engineers in India to perform engineering work-statements for Boeing product life cycle management. This position will work collaboratively with the teams from across the globe in an integrated design environment to help deliver engineering statement of work. The selected individual will develop and handle Engineers, interact with the program leaders from across the globe, with a vision to grow ownership in execution with their team. This position will be in Bengaluru, India , and will be reporting directly to the Sr. Electronic Manager India. Primary Responsibilities: Manages employees performing engineering and technical activities in the areas of ASIC/FPGA verification and design. Develops and executes integrated departmental plans, policies and procedures and provides input on departmental business and technical strategies, goals, objectives. Acquires resources for department activities, provides technical management of suppliers and leads process improvements. Develops and maintains relationships and partnerships with customers, stakeholders, peers, partners and direct reports. Provides oversight and approval of technical approaches, products and processes. Provides project/Activity planning, and key milestone tracking. Manages post silicon debug support activities for validation, SW development and Test Team. Manages directly (including people reporting) the RTL, DV and DFT primarily. Integrated PD and Emulation activities Understand complex protocols and create implementable objectives for team, Protocols would include PCIe, ARINC, MIL 1553, USB, I2C and other proprietary protocols related to space and flight systems Manages, develops and motivates employees along with functional capability planning. Build capability and capacity upon SV & UVM. Nurture directed test case scenarios using VHDL and similar platforms. Should have strong verbal and written communication skills. Basic Qualifications (Required skills/experience): A Bachelors degree or higher is required as a BASIC QUALIFICATION Bachelor Degree from an accredited course of study in electrical engineering, computer science, mathematics, or physics is required At least 12 years of experience in Digital IC design and verification, involved in atleast 3 Chip Tape outs or equivalent. Proficient in tools such as Vmanager and similar tools with other EDA vendors to track and maintain verification workflow metrics for the team. Proficient in concepts such as cross domain clock sync, polymorphism. Proficient in validating the verification workflow with available limitations on tools and resources to provide maximum functional coverage on priority. Demonstrated success leading development efforts, including project management and earned value tracking. Preferred Qualifications (Desired skills/experience): Experience leading or managing in an engineering organization. Familiarity with FAA DO-254 certification. Familiar with Emulation and Safety Flow Analysis Familiar in Formal Verification techniques Familiar in Design Concepts US Person as defined by 22 C.F.R 120.15 is advantageous. Familiar with LOR verification based VCRM structure Typical Education & Experience: Education/experience typically acquired through advanced education (e.g. Bachelor) and typically 13 to 16 years' related work experience or an equivalent combination of education and experience (e.g. Master+12 years of related work experience etc.)

Minimum 18+ years of experience post Engineering degree in EE or EC. Proven expertise in SoC design methodologies and architecture definition Deep understanding of RTL development, integration, and backend handoff.

Qualifications and Preferred Skills: BS, MS in Electrical Engineering, Computer Engineering or Computer Science. 8+ years and current hands-on experience in microarchitecture and RTL development . Proficiency in Verilog, System Verilog . Familiarity with industry-standard EDA tools and methodologies. Experience with large high-speed, pipelined, stateful designs, and low power designs. In-depth understanding of on-chip interconnects and NoC's. Experience within Arm ACE/CHI or similar coherency protocols. Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoC's. Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus. Experience with modern programming languages like Python is a plus. Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills.

Lead the architecture, design and development of Processor Core Front end of pipeline units for high-performance IBM Systems. - Architect and design I-Cache, Instruction Fetch, Branch Prediction and Decode units of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing specific CPU unit(eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) - Hands on experience of different Branch Prediction techniques - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Knowledge of at least one object oriented or functional programming language and scripting language. - Nice to haves - Knowledge of instruction decode and handling pipeline hazards - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Master's Degree/PhD

Responsibilities: Build and guide a team of DFT engineers to deliver the architecture and the DFT deliveries towards SOC development. Engage with the RTL & physical design program management to plan and execute the DFT deliveries. Work with cross-functional teams (e.g., design, verification, test engineering) to integrate DFT features effectively. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise : At least 10+ years of experience in DFT implementation / methodology Strong understanding of digital design and test principles. Proficiency in DFT techniques, such as scan insertion, BIST, and Automatic Test Pattern Generation (ATPG), MBIST insertion Experience with EDA tools , Synopsys and Cadence &scripting languages (e.g., Python, TCL). Knowledge of IC design flows, verification tools, and fault models Ability to identify, analyze, and resolve testing challenges. Work effectively within multidisciplinary teams, communicating complex technical details clearly. Ensure thorough testing, comprehensive fault coverage, and alignment with industry standards. Technically lead/managed 10 - 15 DFT engineers to deliver DFT implementation on SOC Preferred technical and professional experience NA

RTL engineers: (5-15 years of experience) - SoC Design engineer with experience working on SOCs based on ARM Architecture DV engineers : - SOC Verification Experience on ARM Ecosystem - PCIE Experience and also PCIE-VIP usage experience

Pre-Silicon Validation Engineer Experience4 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Creating test environments, checker strategies, and test generators for validating embedded power management firmware in the SOC Communicating effectively, coordinating and working with firmware developers and SOC integration teams Potentially participating in the debug of failures in silicon and developing new testing strategies to detect these failures on pre-silicon models Mentoring junior members of the team in their development You should have 3-5 years of experience in the following areas: SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM Reading and interpreting technical specs and Register Transfer Level (RTL) code SW development skills (Unit Testing, Test Driven Development) Hands-on Debug Preferred Skills and Experience: Expertise in any of one domain like Audio, Performance, power management will be a huge plus 4+ years’ experience with writing validation plans and implement those validation plans Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips- the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world- like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries of"science and engineering to make possible"the next generations of technology, join us to Make Possible® a Better Future. What We Offer Location: Bangalore,IND At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. Were committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits . Youll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers."We empower our team to push the boundaries of what is possible"”while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. Key Responsibilities: Understand and Enhance Existing FPGA Architecture: Analyze and comprehend current FPGA designs and architectures. Identify areas for improvement and optimization within existing systems. Implement enhancements to improve performance, efficiency, and functionality. Develop Modular Architectural Approaches with a Focus on Testability: Design modular FPGA architectures to facilitate ease of testing and integration. Ensure that new designs are scalable and maintainable. Incorporate best practices for testability into the design process. Collaborate with Software, Hardware, and System Teams: Work closely with cross-functional teams to ensure FPGA designs meet system requirements. Communicate effectively with software developers, hardware engineers, and system architects. Participate in design reviews and provide feedback to other team members. Develop RTL Code, Perform Logic Synthesis, Timing Analysis, and Timing Closure: Write and optimize RTL (Register Transfer Level) code for FPGA designs. Conduct logic synthesis to translate RTL code into gate-level designs. Perform timing analysis to ensure designs meet timing constraints and achieve timing closure. Create Test Benches and Simulation Tools for Verification: Develop comprehensive test benches to verify the functionality and performance of FPGA designs. Utilize simulation tools to test and validate designs before implementation. Debug and resolve issues identified during the verification process. Troubleshoot and Improve Building Block Modules: Identify and resolve problems in FPGA modules to enhance performance and reliability . Continuously improve the design and functionality of FPGA building blocks. Document troubleshooting processes and solutions for future reference. Qualifications: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Proficiency in hardware description languages such as VHDL or Verilog. Experience with FPGA design tools and platforms (e.g., Xilinx Vivado, Altera Quartus). Strong understanding of digital design principles and practices. Excellent problem-solving skills and attention to detail. Ability to work collaboratively in a team environment and communicate effectively with diverse teams. Preferred Skills: Experience with high-speed digital design and signal processing. Familiarity with scripting languages (e.g., Python, Tcl) for automation tasks. Knowledge of system-level integration and testing methodologies. Experience in low-power design techniques and optimizations. The role of an FPGA engineer is dynamic and requires a strong technical foundation, creativity in design, and the ability to work well within a multidisciplinary team to develop cutting-edge digital systems. Top of Form Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

About Applied Applied Materials is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations make possible the technology shaping the future. Your Opportunity As an EE you will be working in highly technical, flexible environment with top level exposure to all cutting-edge technologies and legacy system. You will have the opportunity to engage in the Product Life Cycle from concept designs to volume manufacturing for the modules/systems enabling to solve the High value problems of our customers. You will be offered unique opportunities and challenges to get interfaced with our customers and suppliers. Applied continues to grow and is the #1 Semiconductor Manufacturing Company in the industry. Key Responsibilities Expert level technical support in the resolution of FPGA design and application issues Design or modify electrical/electronic engineering assemblies, layouts/schematics and/or detailed drawings/specifications of moderate scope under general supervision. Create design and specification documents, test plans and progress reports. Conduct obsolescence risk assessment for prompt risk mitigation strategy and implementation to ensure product manufacturability and sustenance. Coordinate the procurement and assembly of electrical/electronic components/equipment and identify sources of critical parts and subsystems to resolve technical issues. Participate in resolving customer complaints & escalations through root-cause analysis and corrective-preventive actions. Functional Knowledge (Required Skills/Experience): Extensive knowledge of RTL design language. Hands on experience on design, simulation and testing of FPGA application. Good knowledge of electrical design engineering, Digital/Analog/Mixed signals, Power electronics, Controls and Instrumentation. Good knowledge of electrical engineering design concepts and applications - components, schematics, electrical system. Good understanding on communication interface such as I2C, SPI, USB, Wi-Fi, IoT and Bluetooth, memory device such as SRAM, DDR3+, and high speed communication protocols such as ETHERCAT, ETHERNET, PCIe Experience on microcontrollers and microprocessor design. Interpersonal Skills Demonstrate strong written, oral, and interpersonal communication skills. Excellent aptitude for multi-tasking and willing to learn. Qualifications Bachelors Degree in Electrical Engineering / Electronics & Communication Qualifications Education: Bachelor's Degree Skills: Certifications: Languages: Years of Experience: 4 - 7 Years Work Experience: Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer committed to diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

- Lead the architecture, design and development of Power Management for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor) . - Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams - Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Estimate the overall effort to develop the feature - Estimate the silicon area required for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing Server SoC power management features. * Experience with hardware to model correlation * At least 1 generation of silicon bring up experience * In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) * Proficiency of RTL design with Verilog or VHDL * Knowledge of at least one object oriented or functional programming language and scripting language. Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s microprocessor chip design team. As a member of DFT team, you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in processor flow and post silicon validation

We are hiring a CAD Automation Software Engineer (Frontend & Backend) with 10+ years of experience to deploy and support front-end tools, develop scripts for regression and debug flows, and collaborate with design, implementation, and verification teams. The candidate must be proficient in scripting (Python, Bash, C), Linux administration, and version control (Git/Mercurial). Experience in ASIC flows, CAD tools, and CI/CD setup is essential.

Greetings from Wafer Space! Exciting Opportunity for Senior RTL Design Lead Engineers Automotive SoC Domain Job Title: Senior RTL Design Engineer No. of Positions: 4 Notice Period: Immediate to 30 Days Only Referrals: Please refer only suitable and relevant profiles About the Role: We are looking for experienced RTL Design Engineers to join our team developing next-generation solutions for automotive camera and display systems. This is a key position requiring strong technical expertise in microarchitecture and RTL coding, with an emphasis on high-performance, low-power ASIC designs. Key Responsibilities: Define microarchitecture and implement RTL to meet performance, power, and area (PPA) goals. Collaborate with software teams to define hardware/software interfaces, configuration requirements, and verification collaterals. Partner with verification teams on assertion development, test plans, debugging, and coverage closure. Ensure adherence to industry-standard ASIC design methodologies. Drive design quality and functional safety for automotive-grade solutions. Required Skills & Qualifications: Bachelors/Masters/Ph.D. in Electrical/Electronics Engineering. 5–10 years of hands-on experience in RTL design and microarchitecture development. Strong proficiency in Verilog and SystemVerilog. Proven experience in designing IP blocks for video/audio pipelines. Sound understanding of MIPI CSI and DSI protocols. Experience with high-speed, pipelined, and low-power designs. Familiarity with EDA tools and design methodologies (e.g., Synopsys, Cadence). Experience working on designs complying with automotive functional safety (ISO 26262) is a plus. Excellent problem-solving, communication, and team collaboration skills. Note: Only candidates with a notice period of 30 days or less will be considered. Please share or refer profiles that are strictly relevant to the requirements.

Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the physical design implementation of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Establishes regression flows, drives improvement in RTL to GDS flows, and creates and implements methodologies for improving robustness, power, performance, area, and timing for optimizing physical design constraints. Develops new physical design techniques through innovative scripts, checkers, flows, and other CAD based automation to simplify and expedite the design process. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing physical design related TFM. Partners with physical design, circuits, CAD, RTL, tool/flow owners, and third-party vendor teams to continuously improve physical design methodologies and efficiencies. Qualifications: Minimum Qualifications: B.E/B.Tech or M.Tech/M.S Preferred qualifications: Requirements listed would be obtained through a combination of industry relevant job experience. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore

. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. . 3-10 years of experience in RTL design and Design Verification implementation for VLSI systems.

Key Responsibilities: Translate design specifications into comprehensive power specifications and architect UPF files accordingly. Build and refine power intent using Unified Power Format (UPF) at RTL and gate-level, ensuring consistency across synthesis and physical design flows. Perform power-aware checks using CLP and debug issues arising during MV cell insertion such as isolation, retention, and level shifters. Collaborate with Power Aware DV teams to address feedback and enhance the robustness of power intent. Estimate dynamic and leakage power early in the design cycle and generate power reports using tools like PTPX . Monitor and analyze power trends through implementation milestones; highlight mismatches and coordinate resolution with synthesis/PD teams. Partner with SoC, subsystem, and verification teams for accurate delivery of power intent and power estimates across project phases. Drive automation and improve analysis workflows via scripting using TCL, Perl, or Makefiles . Technical Skills: Expertise in creating and validating UPF-based power intent for SoCs with complex power domains In-depth experience in CLP-based RTL/Gate-level validation Strong command of power estimation using PrimeTime PX (PTPX) Solid knowledge of MV logic components and their insertion behavior during synthesis Clear understanding of power optimization techniques for both dynamic and leakage at various design stages Familiarity with Pre-Si/Post-Si power correlation strategies Strong scripting capabilities in TCL/Perl , with experience in managing flows through Makefiles Interested share resume or references to Shubhanshi@incise.in

Desired Skills and Experience: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl or Python scripting skills. Prior experience with logic synthesis tools is required. Prior experience using or supporting SDC tools would be a significant plus. Prior experience with RTL simulation, SVA would be a plus. Prior experience supporting front-end EDA tools would be a plus. Sound communication skills, verbal and written. Ability to produce product requirement documents. BS EE/CE. 4 years experience with STA/Synthesis.

What You ll Need: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl, or Python scripting skills. Prior experience with logic synthesis tools. Prior experience using or supporting SDC tools (a significant plus). Prior experience with RTL simulation and SVA (a plus). Sound communication skills, both verbal and written. Ability to produce detailed product requirement documents. BS in Electrical or Computer Engineering with 10+ years of experience in STA/Synthesis/Front-End Flows.

Developing and testing software for validation and automation purposes. Performing device-level and system-level validation and debug in post-silicon environments. Executing software tests in verification environments to ensure product quality. Working with FPGA-based setups to run validation tests and update FPGA RTL modules as needed. Creating detailed test and validation reports with statistical analysis. Interfacing with customers to capture requirements and provide post-release support. The Impact You Will Have: Contributing to the development of cutting-edge technology that drives innovation in various industries. Ensuring the reliability and performance of high-speed serial interface PHYs like USB, PCIe, and Ethernet. Enhancing the validation and debug processes through meticulous testing and analysis. Improving the overall quality and functionality of Synopsys products through rigorous validation. Supporting the continuous improvement of product development cycles. Providing valuable insights and feedback to enhance future product iterations. What You'll Need: B.Tech in ECE/CS or equivalent with 3-7 years of previous experience in a similar role/industry. Experience in programming and testing using C/C++. Board-level test and debug experience using lab equipment. Experience with embedded or resource-constrained environments. Development experience on Unix, Linux, and Windows platforms. Ability to quickly learn new workflows and adapt to new technologies. Exposure to MATLAB/Python programming is a plus. Exposure to verification and basic RTL is a plus. Excellent verbal and written communication skills.