806 Rtl Jobs - Page 4

Lead the architecture, design and development of Processor Core Front end of pipeline units for high-performance IBM Systems. - Architect and design I-Cache, Instruction Fetch, Branch Prediction and Decode units of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing specific CPU unit(eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) - Hands on experience of different Branch Prediction techniques - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Knowledge of at least one object oriented or functional programming language and scripting language. - Nice to haves - Knowledge of instruction decode and handling pipeline hazards - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Understanding of Agile development processes - Experience with DevOps design methodologies and tools

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team, you will be required but not restricted to insertion, pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Hands-on experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in Asics/processor flow and post silicon validation

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor core/cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Lead the architecture, design and development of a server class, high- performance Processor CPU for IBM Systems. - Architect and design Instruction caches, Branch Predictors, Issue queues, Register Renaming, Load Store Execution and other areas of the IBM processor CPU - Research novel instruction/data prefetching and branch prediction architectures. - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise Expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of object oriented languages and scripting languages - Understanding of Agile development processes - Experience with DevOps design methodologies and tools

Lead the architecture, design and development of Processor Core Load- Store Execution unit for high-performance IBM Systems. - Architect and design Load and Store pipelines, D-Cache, Address Translation, Out of Order Execution of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise 12 or more years of demonstrated experience in architecting and designing Load-Store Execution unit of CPU - Hands on experience of implementing D-Cache, Address Translation, Memory Consistency handling, Store ordering etc. - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of instruction dispatch and Arithmetic units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred Education

Lead the architecture, design and development of Processor Core Vector- Scalar Execution unit for high-performance IBM Systems. - Architect and design Fixed point/Floating point/Vector/SIMD/Crypto instructions of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise 12 or more years of demonstrated experience in architecting and designing Execution unit of CPU - Hands on experience of implementing Arithmetic/Crypto/SIMD functions - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of instruction dispatch and load/store units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilities:- Expected to be an SME, collaborate, and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Lead and mentor junior team members.- Conduct code reviews to ensure code quality and adherence to coding standards. Professional & Technical Skills: - Must To Have Skills: Proficiency in Emulation platform like Palladium/Zebu/Veloce/HAPS.- Strong understanding of SOC Architecture- Experience with debugging using any Emulation Palladium/Zebu/Veloce/HAPS platform.- Hands-on experience with ARM (A/M) architecture.- Knowledge of C language. Additional Information:- The candidate should have a minimum of 5 years of experience in Emulation.- This position is based at our Bengaluru office.- A 15 years full-time education is required. Qualification 15 years full time education

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilities:- Expected to be an SME, collaborate, and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Lead and mentor junior team members.- Conduct code reviews to ensure code quality and adherence to coding standards. Professional & Technical Skills: - Must To Have Skills: Proficiency in Emulation platform like Palladium/Zebu/Veloce/HAPS.- Strong understanding of SOC Architecture- Experience with debugging using any Emulation Palladium/Zebu/Veloce/HAPS platform.- Hands-on experience with ARM (A/M) architecture.- Knowledge of C language. Additional Information:- The candidate should have a minimum of 5 years of experience in Emulation.- This position is based at our Bengaluru office.- A 15 years full-time education is required. Qualification 15 years full time education

• Expertise in ASIC RTL Design • Expertise in ASIC IP Design • Expertise in CDC and Lint tools • Expertise in design and simulation tools • Expertise in Video processing algorithms / interfaces • Expertise in CXL / PCIe Protocol, 5G, Datacenter

General Summary: Today, more intelligence is moving to edge devices, and mobile is becoming the pervasive AI platform. Building on the smartphone foundation, Qualcomm envisions making AI ubiquitous - expanding beyond mobile and powering machines, vehicles, and Internet of things. Be part of the group that is working on technology which will bring cognition to all connected devices. Join the machine learning team responsible for ASIC IP design and integration of leading-edge technologies in the area of image post processing, machine learning, and IoT. We are searching for a lead ASIC Design Engineer to be part of the AI Processor Design Team responsible for developing hardware to support AI/ML and video processing systems. Preferred Qualifications Masters- Electrical Engineering , Computer Engineering, Exposure to functional safety, Automotive(ASIL) ASIC design. Experience with cache control and/or video processing function design/verification Detail oriented with strong analytical and debugging skills Strong communication (written and verbal), collaboration, and specification skills Ability to work well in a team and collaborate with your colleagues worldwide Minimum Qualifications Previous experience working on complex high-performance RTL design, preferably on DSP or processor based sub-system. Expert in hardware (RTL) design in Verilog, System Verilog or VHDL. Knowledge of standard on chip bus interface protocols (AXI, APB, AHB) Experience with some of below. Model development (SystemC, or C++) RTL to gates synthesis (Synopsys DCG or Cadence Genus) Design rule and CDC checking (SVA assertions, Spyglass, 0-in) Work on high performance low power RTL design. Scripting languages (PERL, Python, TCL, C, etc.) PRINCIPAL DUTIES AND RESPONSIBILITIES: Develop micro-architecture, design and program specific documentation Design and modelling of compute ASIC modules and sub-systems. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Resolves architecture, design, or verification problems by applying sound ASIC engineering practices Use of various design tools (Synopsys, Compiler Linting, CDC, LEC, CLP etc.) to check and improve design quality Help the design verification team execute on the functional verification strategy. Generates innovative ideas for IP core and process flow improvements Level of Responsibility: Working independently with little supervision. Making decisions that are moderate in impact; Using deductive and inductive problem solving; multiple approaches may be taken/necessary to solve the problem; often information is missing or incomplete; intermediate data analysis/interpretation skills may be required. May be solicited during strategic planning period. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years RTL Design/Hardware Engineering experience or related work experience. Strong Domain Knowledge on RTL design(Verilog/VHDL/System Verilog) , implementation, and integration, micro-architecture & designing cores and ASICs Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc Exposure in scripting (Pearl/Python/TCL) Strong debugging capabilities at simulation, emulation, and Silicon environments Collaborate closely with cross-functional teams to research, design and implement performance and power management strategy for product roadmap Knowledge on Designing low power/power management controller IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), on-chip sensor controller Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows Work closely with system/software/test team to enable the low power feature in SoC products

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years RTL Design/Hardware Engineering experience or related work experience. Strong Domain Knowledge on RTL design(Verilog/VHDL/System Verilog) , implementation, and integration, micro-architecture & designing cores and ASICs Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc Exposure in scripting (Pearl/Python/TCL) Strong debugging capabilities at simulation, emulation, and Silicon environments Collaborate closely with cross-functional teams to research, design and implement performance and power management strategy for product roadmap Knowledge on Designing low power/power management controller IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), on-chip sensor controller Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows Work closely with system/software/test team to enable the low power feature in SoC products

General Summary: As a Qualcomm Systems Engineer, you will research, design, develop, simulate, and/or validate systems-level software, hardware, architecture, algorithms, and solutions that enables the development of cutting-edge technology. Qualcomm Systems Engineers collaborate across functional teams to meet and exceed system-level requirements and standards. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. ORPhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. Job Overview Work with Qualcomm's security architecture / IP and access control team on next generation SOC for smartphone, tablet, automotive and IOT product categories. is responsible for assisting product development teams throughout the company to apply secure HW design principles to individual blocks, computing cores, and at the SoC level. SW/HW co-design, HW development experience. Familiarity with debug architectures such as JTAG and ARM coresight are a plus Successful candidates will be able to engage with product teams independently with minimal supervision to detect and mitigate security vulnerabilities in hardware architecture and implementations, involve in access control issues at both SW and HW. Minimum Qualifications 6 to 12 years of industry or academic experience in Security are required. Additionally, applicants must have expertise in two or more of the following areas: Computer architecture and hardware based or assisted access control and security Mobile platform security, Secure Boot, Secure Storage, Access Control, Secure Debug, DDR protection ARM TrustZone, Virtualization Operating system security and hypervisor security languages: C/C++, Python, RTL Teamwork across various teams and geolocations. Able to communicate in English, both verbal and written. Preferred Qualifications The following skills/experience will be considered a plus: ARM architecture SoC security design Applied Cryptography Trusted Computing Working Knowledge on hardware firewalls for access control Knowledge on AI/ML is added advantage SystemVerilog, VHDL, Verilog, SystemC - FPGA/ASIC design is a plus Side channel attacks, power analysis and timing attacks on crypto elements is a plus Memory technology (DDR4, DDR5), storage technologies is (eMMC, UFS) is a plus Educational Requirements: Required: Bachelor degree and above, Computer Engineering and/or Electrical Engineering Experience Requirements: Bachelors/ Masters with 5-7+ years Systems Engineering or related work experience

Overview Developing emulation testbenches to support necessary DV scenarios and firmware/software/hardware bring up Responsibilities Build emulation models from RTL and release/support those models Develop emulation tools such as debugger and monitor features Work closely with verification and software development teams Develop emulation and verification strategy Develop test framework and test cases Write documents such as verification specification and reports Coach younger colleagues Emulation and Prototyping technologies such as Palladium, Veloce, Zebu, HAPS, (these names are registered trade marks of their respective owners) Requirements Experience - minimum 15+ yrs and above with minimum of 5+ yrs of experience of woking on any one of the Emulation platform. Education Qualification: BE/BTech Show more Show less

DFT Engineers with experience in ATPG, MBIST, post-silicon debug. Tools: TestKompress, VCS RTL Engineers with Verilog, SoC/IP design, PCIe/DDR, Spyglass. Tools: DC, Verdi, Xcelium. Physical Design Engineers with experience in Innovus, STA, 28nm Office cab/shuttle Food allowance Health insurance

About SiFive SiFive, the pioneers who introduced RISC-V to the world, are revolutionizing the future of computing by harnessing the boundless potential of RISC-V for the most high-performance and data-intensive applications globally. SiFive's unparalleled computing platforms continue to empower leading technology firms worldwide to innovate, optimize, and deliver cutting-edge solutions across various chip design segments, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer electronics. With SiFive, the future of RISC-V knows no bounds. At SiFive, we are eager to engage with talented individuals who share our fervor for driving innovation and making a difference in the world. Our culture of constant innovation and enduring success is attributed to our remarkable teams of immensely talented individuals who collaborate and support one another to generate truly revolutionary ideas and solutions. These solutions are poised to significantly impact people's lives, gradually making the world a better place, one processor at a time. Are you prepared to join us on this journey To delve deeper into SiFive's remarkable achievements and discover why we have been honored with the GSAs prestigious Most Respected Private Company Award (for the fourth time!), explore our website and Glassdoor pages. Responsibilities - Lead the implementation and drive uARCH optimization of SiFive's high-performance Out of Order RISC-V CPUs from RTL to GDSII. - Achieve ambitious performance, power, and area (PPA) goals at the block and/or CPU subsystem level. - Work closely with the microarchitecture and RTL teams to identify and optimize PPA trade-offs, including pathfinding for the next generation of CPUs. - Develop timing and area models for configurability to ensure predictable execution. - Contribute to the development of physical implementation flow and enhance Foundation IP (standard cell, SRAM) to achieve best-in-class automation and PPA. Requirements - Possess 12+ years of physical implementation experience with multiple tape-outs across various technologies; Strong preference for experience in CPU implementation and advanced process nodes (3nm and below). - Proficient in Synopsys/Cadence Silicon Implementation tools. - Expertise in aggressive PPA optimization through physical design techniques. - Familiarity with out-of-order core uArch and logic design is highly preferred. - Prior experience in leading/managing teams is advantageous. - Detail-oriented with a focus on high-quality design. - Ability to collaborate effectively with others and a belief in the collaborative nature of engineering. - Hold a Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. Additional Information This role necessitates successful background and reference checks, along with satisfactory proof of your eligibility to work in India. Any employment offer for this position is subject to the Company verifying your authorization for access to export-controlled technology under relevant export control laws or, if not already authorized, our ability to obtain any necessary export license(s) or approvals successfully. SiFive upholds equal employment opportunities. We value diversity and are dedicated to fostering an inclusive environment for all employees.,

You will be responsible for demonstrating expertise in RTL, Integration, PLDRC, CDC, and Quality Checks. Your role will involve working with a leading Product Engineering Services company that specializes in Semiconductor Design Services, Embedded Systems, Digital Solutions, Artificial Intelligence, Machine Learning, IoT, Networking, and Robotics. The position is based in Bangalore and requires a minimum experience of 3+ years in the field. Face-to-face interviews are scheduled for Friday, February 28. TekWissen Group is committed to being an equal opportunity employer that promotes workforce diversity.,

As a UI Developer with 4-5 years of experience, you will work both independently and collaboratively within a team environment to design, develop, and test web-based applications. Your primary responsibilities will include designing, developing, testing, and documenting high-quality software that meets user and functional requirements. You will be expected to adhere to the best coding standards and generate rapid prototypes for feasibility testing. Additionally, you will produce all relevant documentation for software operation and follow prescribed development systems and procedures to ensure efficient, effective, and high-quality delivery. Effective communication with stakeholders and the ability to perform tasks as directed by the Delivery Lead/Team Lead are essential aspects of this role. Your qualifications should include a strong focus on UI development, with expertise in creating User Interfaces using various front-end technologies such as SSR, SPA, and PWA Apps. You should have extensive experience in React, Redux, Typescript, JavaScript, HTML5, CSS3, and related technologies, enabling you to analyze and develop code effectively. A good understanding of cross-browser compatibility, cross-platform functionality, Server-side rendering, and Micro Frontends is required. Experience with RESTful API integration, cloud environments like Microsoft Azure, and application performance analysis and tuning are also necessary. Proficiency in unit testing using Jest and RTL, as well as familiarity with UI libraries like MUI, ANTD, PrimeReact, or similar, is highly desirable. Knowledge of web accessibility concepts, CI/CD environments, version control tools like Git, and user interface monitoring tools is expected. Mandatory qualifications include proficiency in HTML5, CSS, JavaScript, and Typescript, as well as experience with technologies like REACT, Redux, React Router, and Axios. Familiarity with testing tools such as Jest and RTL, and cloud platforms like Azure/AWS is also required. Highly desirable skills include expertise in Next JS, Micro Frontend, and PWA technologies.,

Seeking a Platform Verification Lead to drive end-to-end validation of high-performance SoC platforms, define verification strategies, mentor teams, and ensure first-time-right delivery.

Job Requirements Experience 4-8 yrs in Design Verification. Strong SV UVM Verification exp in real projects. Peripheral I/O, Ethernet ARM SOC-based Experience in Physical design with block level and familiar with ASIC design flow from synthesis to GDSII. Experience in handling High utilized critical blocks and Congestion mitigation Work very closely with Architecture teams to come up with micro-architecture and hardware specification for features Design and RTL ownership Work very closely with Design Verification teams to review test plans and sign off the validation of all design features across products. Work closely with physical design teams to achieve the right power, performance and area metrics for the GPU blocks. WFO mandated.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Design, implement, and verify FPGA logic using Vivado toolchain. Develop and integrate custom FPGA IP blocks, ensuring functionality and performance requirements are met. Write, optimize, and maintain Verilog-based designs and testbenches for FPGA projects. Perform synthesis, place & route, timing closure, and bitstream generation in Vivado. Validate FPGA IP on hardware platforms, including board bring-up and debug. Collaborate with cross-functional teams (ASIC, SoC, validation) to ensure smooth IP integration into larger systems. Support FPGA prototyping of SoC/ASIC designs, contributing to pre-silicon validation. Document design specifications, validation methodologies, and debug findings. Skills Must have 2-4y exp Hands-on experience with Xilinx Vivado FPGA design flow (synthesis, implementation, bitstream generation). Strong proficiency in Verilog HDL for design and validation. Aptitude for FPGA IP development including design, integration, and verification. Good understanding of digital design fundamentals and FPGA architectures. Familiarity with simulation, debugging, and timing analysis on FPGA platforms. Nice to have Organized and methodical with effective communication skills.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop System Verilog/UVM-based testbenches for block-level and system-level verification. Write and execute UVM test cases to verify functional correctness of RTL designs. Perform detailed functional coverage and code coverage analysis, and drive coverage closure. Debug simulation failures, root-cause issues, and work closely with design and verification teams for resolution. Collaborate with cross-functional teams to ensure successful verification closure within project timelines. * Develop and maintain scripts using Python or other scripting languages for automation, regression management, and data analysis (optional but preferred). Apply working knowledge of standard bus protocols such as AXI, APB, UART, and IJTAG for testbench development and debugging. Document verification plans, test specifications, test reports, and maintain traceability. Skills Must have 4-6y exp SV / UVM Test bench development and test cases coding Code and Functional coverage analysis and closure Work with team for verification closure Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage. Nice to have Experience with python or any other scripting language is a plus

As a Senior Physical Design Engineer with Micron Technology, you will play a crucial role in the HBM Team based in Hyderabad, India. Your primary responsibility will be to design and develop complex Application-Specific Integrated Circuits (ASICs) catering to the requirements and specifications of High Bandwidth Memories (HBM). These memories are utilized in intensive applications like artificial intelligence and high-performance computing solutions, aiming to push the boundaries of technology and innovation. Your role involves designing IPs or Hierarchical blocks solutions for high-performance and low-power applications. You will collaborate closely with cross-functional teams to define project requirements and conduct feasibility studies. Your expertise will be instrumental in creating detailed IPs or Hierarchical blocks design specifications, ensuring alignment with project goals. Additionally, you will enable Place and route, clock tree synthesis capabilities for the System on Chip (SoC) Integration. To excel in this position, you will implement and optimize digital designs using hardware description languages (HDLs) such as Verilog or VHDL, considering various design trade-offs and performance metrics. Your responsibilities will also include evaluating RTL coding, timing analysis, synthesis, and functional verification to ensure the correctness and robustness of the design. As a Senior Physical Design Engineer, you will lead and participate in verification efforts, write testbenches, run simulations, and debug functional and timing issues. Collaboration with physical design engineers is essential to guide and optimize the layout to achieve performance and power targets effectively. Moreover, you will contribute to the evaluation and selection of third-party IP blocks to integrate into the IPs or Hierarchical blocks design. It is crucial to stay updated with the latest design methodologies, tools, and industry trends, continuously enhancing design practices. Additionally, mentoring junior engineers by providing technical guidance and support will be part of your role. To be successful in this position, you should have at least 5 years of relevant work experience focused on RTL to GDS for high-performance architectures. Experience in physical design, timing closure, and physical integration/signoff is essential. You should possess a drive for continuous learning, evaluating microarchitectural options, and interconnecting complex microarchitectural structures and subsystems. Proficiency in hardware description languages (HDLs), familiarity with EDA tools, and a strong understanding of design methodologies are required. Scripting language proficiency for automating design tasks will be advantageous. A Bachelor's degree (BE) or Master's degree (MTech) in Electronic/VLSI Engineering is necessary to qualify for this role. Micron Technology, Inc. is a global leader in innovative memory and storage solutions, dedicated to transforming the use of information to enrich life for all. If you are passionate about pushing the boundaries of technology and innovation, this role offers an exciting opportunity to contribute to cutting-edge semiconductor products and maintain a competitive edge in the industry.,

Role & responsibilities Handling hierarchical scan insertion ATPG flow. Integration and Verification of MBIST at RTL level. RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST. Implementation and Verification of IEEE1149.1 JTAG, IJTAG standards. Post silicon debug activities for DFT patterns. Collaboration with RTL design, Physical design and verification teams will be a daily aspect of the role. Preferred candidate profile Degree/PG in Electrical/Electronic Engineering, Computer Engineering or Computer Science. At least 12+ years of experience in related domains and have working knowledge of industry standard digital EDA toolkits. Must be conversant on EDA tools such Tessent, Genus, FC, VCS and Conformal/Formality etc. Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Cando attitude, openness to new environment, people and culture. Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus. Ability to work independently and as part of a team. Mentor and guide junior engineers in DFT.

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.