MBit Wireless Private Limited is a next-generation fabless semiconductor innovator delivering advanced 4G/5G SoCs, edge-computing chipsets, software, and turnkey solutions that power the future of mobile broadband, AIoT, and EV ecosystems. Our ultra-low-power, high-efficiency processors enable smarter, faster, and more connected devices across global markets

Role Description

Design and develop RTL for complex SoC subsystems using
Verilog/SystemVerilog
Implement and integrate IPs such as
CPU/MCU, interconnects (AXI/AHB), memory controllers, peripherals, and accelerators
Translate
architecture and micro-architecture specifications
into high-quality RTL
Ensure
synthesizable, timing-clean, and low-power RTL
following coding guidelines
Perform
block-level and SoC-level integration
Collaborate closely with
architecture, verification, physical design, and firmware teams
Support
functional verification
, including debug of simulation and emulation failures
Address
lint, CDC/RDC, reset, and low-power checks
Participate in
design reviews
and incorporate feedback
Support
DFT requirements
(scan, MBIST, JTAG integration)
Work with
UPF/low-power intent
and power domain implementations
Analyze and resolve
timing, area, and power
issues in coordination with PD teams
Maintain RTL quality for
reusability, scalability, and maintainability
Assist in
post-silicon debug
and silicon bring-up activities
Document design specifications, integration guides, and release notes

Qualifications

3 to 5 years of experience in RTL development
B.Tech/BE Electronics & Communication Engineering, Electrical & Electronics Eng
Strong expertise in
SystemVerilog/Verilog
Solid understanding of
digital design fundamentals
Experience with
AMBA protocols (AXI, AHB, APB)
Familiarity with
EDA tools
(simulation, synthesis, lint, CDC)
Ability to debug complex SoC-level issues

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