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2.0 - 7.0 years

5 - 12 Lacs

bengaluru

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As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5...

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3.0 - 8.0 years

8 - 12 Lacs

noida, hyderabad, bengaluru

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Skills/Experience: Extensive experience in IP/SOC Verification. Must be proficient in System Verilog and UVM. Must have hands-on experience in the verification of the IP protocols such as PCIe/DDR/USB/Ethernet/CXL/HDMI/MIPI/DSI/CS/GLS/CPU Verification or any other high-speed protocols. Experience with scripting language (Python, Perl, TCL etc.) Experience in assembly language or C is a plus. Ability to create testbenches from scratch and own the complete verification including coverage of the subsystem/chip level. Strong debugging capabilities. Experience (years) : 3 - 12 Years Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

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4.0 - 8.0 years

5 - 7 Lacs

hyderabad

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VHDL/FPGA Design Engineer RTL design, simulation, test bench development & debugging using VHDL. Experience with Xilinx Vivado, timing constraints & synthesis tools. SoC integration, communication protocols & strong HDL debugging skills.

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2.0 - 7.0 years

7 - 11 Lacs

noida

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We make real what matters. This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will get along with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. You're an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute You've got phenomenal knowledge of verification engineering and have ...

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3.0 - 8.0 years

8 - 13 Lacs

noida, hyderabad, bengaluru

Work from Office

Skills/Experience: Good Experience with Xilinx FPGA. Should be well aware of RTL logic. Well versed with Vivado tool and associated IP Well versed with LUT considerations in FPGA design Well versed with FPGA simulation and testing methods Well versed with FPGA debug using Xilinx JTAG debugger Experience (years) : 3 - 12 Years Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

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3.0 - 8.0 years

8 - 13 Lacs

noida, hyderabad, bengaluru

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Skills/Experience: Strong design fundamentals with hands-on experience in front-end design flows Hands-on experience in design of micro-architecture blocks, RTL coding, block-level verification. Hands-on experience in Linting, CDC analysis of reports, identify ways to fix the violations Hands-on experience in SoC/IP integration Excellent understanding of SoC components like processors, memories, peripherals, IOs Good understanding of at-least one of the protocols like UFS/PCIe/SAS/SATA/USB Experience of working with ARM or ARC (Synopsys) processors/sub-systems Experience of UPF flow, updating constraints Ability to work independently, ramp-up quickly and work with verification/validation tea...

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3.0 - 5.0 years

5 - 9 Lacs

bengaluru

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Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

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3.0 - 8.0 years

2 - 5 Lacs

bengaluru

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Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC ver...

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4.0 - 9.0 years

10 - 20 Lacs

chennai

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RTL Design and FPGA prototyping experience of ASIC - IP & SoC Integration - To Integrate various IPs into Sub-System/SoC. - Handle all integration flows (IP/SoC) including clocking, resets, interrupts, Bus interfaces, Fuses, Security, Address Map etc. - To run all QA checks including compile, lint, CDC, Synth Elab, CLP, Register File generation at IP/SoC - To develop glue logic at IP/SoC for various requirements including IPC, Address decoding, top-level control/status registers, security etc - Involve in initiatives being pursed in IP/SoC Integration including automation.

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2.0 - 6.0 years

5 - 9 Lacs

bengaluru

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We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug. You will play a key role in silicon bring-up, workload execution and validation. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Proficiency in C and Python for validation and automation Hands on experiencec in Writin...

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8.0 - 13.0 years

11 - 15 Lacs

bengaluru

Work from Office

Lead the Architecture, Design and development of processor MMU (Memory management unit) for high- performance IBM Systems. - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the MMU feature enhancements. - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Mas...

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1.0 - 3.0 years

3 - 7 Lacs

bengaluru

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End-to-end design and development of features for IBM high performance Mainframe and POWER processors and ASICs. Develop the feature, present the proposed architecture in the High level design discussions Estimate the overall effort to develop the feature Develop micro-architecture, Design RTL, Collaborate with the Verification, Physical design, FW teams to develop the feature Pre Silicon: Signoff the Design that meets all the functional, area and timing goals Post Silicon: Bringup and Validate the hardware functionality Required education Bachelor's Degree Required technical and professional expertise 1 to 3 years of professional experience Experience with HDLs- VHDL/ Verilog Understand and...

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10.0 - 14.0 years

10 - 20 Lacs

bengaluru

Work from Office

We are seeking a highly experienced Staff Design Engineer with 10+ years of expertise in RTL design and digital signal processing for our Bengaluru location (max 30 days notice period). The ideal candidate will be responsible for designing, developing, and integrating custom DSP components such as filters, FFTs, and control logic for Aevas advanced 4-D Lidar processing chip across ASIC and FPGA platforms. The role involves creating micro-architecture specifications, writing and validating SystemVerilog RTL code, and ensuring designs meet stringent performance, low-power, and robustness requirements. The engineer will collaborate with architects, verification, and system software teams to ach...

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7.0 - 12.0 years

25 - 40 Lacs

pune, chennai, bengaluru

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Functional Safety Lead VLSI / SoC Email: prabhu.p@acldigital.com | WhatsApp: +91 87543 87484 Job Overview We are looking for an experienced VLSI Functional Safety Lead who will be responsible for planning and leading functional safety activities in compliance with ISO 26262 for silicon hardware design . You will work across SoC and IP development teams to drive safety analysis, audits, verification methodologies , and ensure compliance to functional safety standards. This is a key leadership role that requires a strong mix of ASIC/SoC design, verification, and ISO 26262 functional safety expertise . Key Responsibilities Lead functional safety activities for ASIC/SoC designs in compliance wit...

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10.0 - 14.0 years

7 - 12 Lacs

bengaluru

Work from Office

We are seeking a highly experienced Staff Design Engineer with 10+ years of expertise in RTL design and digital signal processing for our Bengaluru location (max 30 days notice period). The ideal candidate will be responsible for designing, developing, and integrating custom DSP components such as filters, FFTs, and control logic for Aevas advanced 4-D Lidar processing chip across ASIC and FPGA platforms. The role involves creating micro-architecture specifications, writing and validating SystemVerilog RTL code, and ensuring designs meet stringent performance, low-power, and robustness requirements. The engineer will collaborate with architects, verification, and system software teams to ach...

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10.0 - 15.0 years

6 - 9 Lacs

bengaluru

Work from Office

We are seeking a highly experienced Staff Design Engineer with 10+ years of expertise in RTL design and digital signal processing for our Bengaluru location (max 30 days notice period). The ideal candidate will be responsible for designing, developing, and integrating custom DSP components such as filters, FFTs, and control logic for Aevas advanced 4-D Lidar processing chip across ASIC and FPGA platforms. The role involves creating micro-architecture specifications, writing and validating SystemVerilog RTL code, and ensuring designs meet stringent performance, low-power, and robustness requirements. The engineer will collaborate with architects, verification, and system software teams to ach...

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4.0 - 9.0 years

10 - 20 Lacs

hyderabad, bengaluru

Work from Office

Job Description We are looking for an experienced Design Verification Engineer to join our team and contribute to the verification of complex SoC/ASIC designs. The ideal candidate will have strong expertise in verification methodologies, testbench development, and debugging. Key Responsibilities: Develop and implement verification plans, environments, and testbenches using SystemVerilog/UVM. Write and execute test cases for functional, regression, and coverage-driven verification. Perform debugging and root cause analysis for design and verification issues. Collaborate with RTL design, architecture, and validation teams to ensure quality deliverables. Analyze functional coverage metrics and ...

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3.0 - 5.0 years

5 - 9 Lacs

bengaluru

Work from Office

Education: Bachelors degree (BE/B.Tech)orMasters degree (ME/M.Tech) Roles & Responsibilities: Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team. Write and perform the test plan in close cooperation with the logical design team. Develop coverage models and verification environments using UVM-SystemVerilog C++. Write, maintain and publish the verification specification. Monitor, analyze and debug simulation errors. Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time. Produce a maintainable and reusable code across projects Required Skills and Experience ...

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3.0 - 7.0 years

12 - 16 Lacs

hyderabad

Work from Office

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification t...

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3.0 - 5.0 years

5 - 9 Lacs

bengaluru

Work from Office

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

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6.0 - 11.0 years

4 - 9 Lacs

hyderabad, pune, bengaluru

Hybrid

Design Verification: SV/UVM Test Bentch Developement Any Protocols: PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM) • 6+ years of hands-on DV experience in System Verilog/UVM. •Must be able to own and drive the verification of a block / subsystem or a SOC. •Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Physical Design: •In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. - Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Floor Planning/Innovus/Fusion Compiler Experience on programming in Tcl/Tk/Perl. Physical Design Methodologies a...

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2.0 - 8.0 years

0 Lacs

karnataka

On-site

Qualcomm India Private Limited is seeking talented engineers for CPU RTL development targeted at high-performance, low-power devices. As a CPU Micro-architecture and RTL Design Engineer, you will collaborate with chip architects to conceptualize the micro-architecture and contribute to architecture/product definition early in the product life-cycle. Your responsibilities will include performance exploration, microarchitecture development and specification, RTL ownership to achieve power, performance, area, and timing goals, functional verification support, performance verification support, and design delivery in coordination with a multi-functional engineering team. To excel in this role, yo...

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8.0 - 12.0 years

0 Lacs

hyderabad, telangana

On-site

You have an immediate job opening with one of your valuable clients in Hyderabad for FPGA with Firmware profiles. The ideal candidate should have at least 8 years of experience in FPGA, RTL Design, RTL Coding, Firmware, CDC, and Lint. The location for this position is Hyderabad and the notice period is immediate to 15 days. If you are interested in this opportunity, kindly share your updated profile with Anand Arumugam at anand.arumugam@modernchipsolutions.com or call +919900927620 for further discussion.,

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3.0 - 7.0 years

0 Lacs

hyderabad, telangana

On-site

The ASIC/SOC Front End Design Engineer role involves setting up ASIC QA flows for RTL design quality checks, understanding top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, and power domains. You will be responsible for executing various design steps such as Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, and CLP. Additionally, you will create clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers while reviewing flow errors, design errors, and violations. As an ASIC/SOC Front End Design Engineer, you will debug CDC and RDC issues, provide RTL fixes, and support the DFX team for DFX controller integration, Scan insertion...

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5.0 - 9.0 years

0 Lacs

karnataka

On-site

As a RTL Design Engineer for DDR Memory Controller IP development team at Cadence, your primary responsibility will be to design and support the RTL of the DDR Memory Controller solution. This entails supporting all leading DDR memory protocols including DDR4/LPDDR4. You will collaborate on working with the existing RTL, incorporating new features, ensuring customer configurations are clean during verification regressions, providing customer support, and ensuring the design adheres to LINT and CDC design guidelines. To qualify for this role, you should hold a BE/B.Tech/ME/M.Tech in Electrical/Electronics/VLSI and possess significant experience as a design and verification engineer, with a fo...

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