566 Rtl Design Jobs - Page 14

We are seeking highy motivated individuas with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to hande the chaenging probems in future technoogies and designs. We are aso ooking for candidates with Strong C/C++background to ead our eading-edge agorithmswithin our EDA soutions to increase our design team’s productivity and chip quaity and performance. Our dynamic goba team is ooking to enist enthusiastic professionas to join word-cass hardware design teams responsibe for deveoping the most chaenging and compex systems in the word. We are seeking energetic, highy motivated individuas wiing to go the extra mie with the aim of heping the overa IBM deveopment team. Strong interpersona skis are needed to coordinate deiverabes and requirements from severa areas within and outside of the organization.There are many opportunities to gain and utiize a deep understanding of future issues and provide input towards decisions affecting system deveopment, ogica and physica design as we as sophisticated methodoogy directions. Individuas who are chosen to become a part of our word cass deveopment teams wi be heping advance IBM’s eadership in deveoping the highest performing computers and changing hardware soutions. Do you want to be an IBMerCome THINK with us! Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise 4+ years of IT experience Strong C/C++programming skis in a Unix/Linux environment is a must. VLSI knowedge, Knowedge in front end inting toos and checkers and RTL Checkers. Great scripting skis – Per / Python/She Proven probem-soving skis and the abiity to work in a team environment are a must Preferred technica and professiona experience RTL Lint Checkers , Front end verification fow, VLSI knowedge, VHDL/Veriog, computer architecture

As a Logic Design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers. Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLL Additiona responsibiities: ogic (RTL) design, timing cosure, CDC anaysis etc. Understand and Design Power efficient ogic. Agie project panning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise Minimum 8+ years of experience in Chip design and deveopment. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, mutipiers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Veriog

As a Logic design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers.Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLLAdditiona responsibiities:ogic (RTL) design, timing cosure, CDC anaysis etc.Understand and Design Power efficient ogic.Agie project panning and execution.Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise Minimum 8+ years of experience in Chip design and deveopment. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, mutipiers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Veriog

As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5. Work closely with verification teams to develop test plans and ensure 100% functional coverage. 6. Debug and resolve design and integration issues during simulation and post-silicon validation. 7. Participate in timing analysis and closure in collaboration with the physical design team. 8. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 210 years of experience in RTL design and implementation for VLSI systems. 3. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. 4. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. 5. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. 6. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. 7. Experience in static timing analysis (STA) and timing closure workflows. 8. Strong problem-solving skills and the ability to debug complex design issues. 9. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: 1. Experience with low-power design and multi-clock domain systems. 2. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 3. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. 4. Familiarity with machine learning or AI-based RTL optimizations. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.

Key Responsibilities: Perform block- and chip-level functional verification of complex ASIC/SoC designs. Build UVM-based testbenches from scratch for new IPs and subsystems. Create and execute detailed verification test plans based on specifications. Develop constrained-random and directed test cases and debug simulation issues. Conduct functional and code coverage analysis and drive coverage closure. Use RAL (Register Abstraction Layer) for register-level testing. Develop and validate SystemVerilog Assertions (SVA). Candidate Requirements: • Education: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related fields. • Experience: 6–10 years of relevant experience in ASIC/SoC design verification.

Position: Lead RTL Design Engineer (ASIC/FPGA) Location: Bangalore Experience: 7+ years Senior / Lead Level Role Overview Were seeking a proactive Lead RTL Engineer to define micro-architectures, implement robust RTL, guide integration, and collaborate across ASIC and FPGA domains. You will architect complex subsystems and mentor a high-performing team. Key Responsibilities Micro-architecture & Specifications: Create block-level design docs & detailed RTL micro-architecture for highcomplexity IP/subsystems. RTL Coding & Review: Develop clean, synthesizable RTL in Verilog/SystemVerilog/VHDL. Ensure code quality via lint/CDCC/static timing checks. Integration & IP Subsystems: Integrate with SoC/FPGA subsystems—protocols like AMBA/AXI, interconnects, memory, serial interfaces. Synthesis & Timing Closure: Lead flows using Design Compiler, Primetime, STA tools to meet timing and area goals. Verification & Debug: Coordinate with verification leads, support testbench development, and debug RTL—functional, wavebased, simulation. Leadership & Mentorship: Mentor engineers, lead reviews, steer integration, and liaise across RTL, verification, physical design, and architecture teams. Toolchain & Scripting: Script for automation (Tcl, Python, Perl, Shell); manage version control (e.g. Perforce, Git) . Innovation & Best Practices: Drive RTL design best practices, stay current with EDA tools, lowpower (UPF), CDC, linting, and continuous improvement. Required Qualifications Bachelor’s/Master’s in EE/CE or similar. 7+ years in RTL for ASIC/FPGA, +3 years in a leadership role. Expert in Verilog/SystemVerilog/VHDL, microarchitecture, FSMs, datapaths, CDC. Experienced with SoC/IP integration—AXI, AHB, APB, PCIe, USB, Ethernet, DDR, etc. Proficient with synthesis, STA, CDC, lint tools, DFT flows. Solid scripting with Tcl/Python/Perl/Shell and version control systems. Strong communication, documentation, team leadership, and cross-team collaboration skills. Preferred Skills FPGA prototyping and hardware bring-up expertise. Low-power methodologies (UPF, power gating). ASIC methodology experience (synthesis, timing, DFT, PPA closure). Familiarity with UVM verification, formal methods. Integration experience with high-speed or accelerator IP (NoC, memory controllers, etc.). What You’ll Get High-impact leadership in advanced RTL design for ASIC/FPGA cutting-edge chips. Opportunity to mentor and build a top-tier RTL team. Collaborative culture working with architecture, verification, PD, and system teams. Learning, ownership, and visibility across end-to-end chip delivery.

What Youll Be Doing Use of hardware such as oscillator and logic analyzers for hardware debugging Good understanding of digital electronics and design practices Strong sense of ownership, passionate, fast learner, analytical mind set, perfection seeker. Excellent interpersonal, communication, collaboration and presentation skills. What Are We Looking For Strong VHDL/Verilog Programming skills In depth knowledge of RTL design, FPGA design, and FPGA design tools. Complete FPGA development flow from logic design, place route, timing analysis closure, simulation, verification, and validation Experience withXilinx/Intel/Lattice/MicrochipFPGA families and corresponding development tools Experience inverification/simulationtools Modelsim/Questa-sim etc. Strong troubleshooting and debugging FPGA implementations on hardware boards Experience with debugging HW/SW issues and the use of equipment/tools such as oscilloscope, logic analyzer, Chipscope/ILA/Signal Tap Ability to understand synthesis reports, perform timing analysis and write FPGA design constraints Hands-on experience on communication protocols (UART/I2C/SPI etc.) and bus interfaces (AMBA/AXI etc.)

raja.a@honeybeetechsolutions.com resume to Client Name: Proxelera Client SPOC: NA Industry: SEMICON HBTS SPOC: Shilpa Gajjala Client Req ID: ZR_116_JOB Position Name RTL Engineer Job No : PROX-14075 Position type: Permanent Total Exp: 4 to 5 years HBTS Budget: Open No of Position: 1 Notice Period: Immediate Asset: Laptop Mandatory for interview Work Location: Hyderabad Work Type: WFO Job Type: Full-time CVR Type: Internal CVR CVR Panel Name: Shilpa Gajjala Interview Rounds: 2 Rounds Interview Mode: Virtual in Teams Job Description Must have: Must Have RTL coding knowledge Must Have Top-level (SOC) level basic industry standard Arch knowledge Must Have SoC & IP level Integration knowledge Must Have IPXACT knowledge Must Have IORING and Phys & GPIOs basic functionality Must Have Design Partitioning(Tilification) knowledge Must Have Design RTL quality checks: Must Have Clock domain crossing(CDC) Must Have Reset domain crossing(RDC) Must Have LINT Must Have VSI Must Have UPF knowledge Must Have LEC(Logic equivalence check) Must Have Timing concepts & SDC knowledge Must Have Tools knowledge: Must Have Vc_static or equivalent other tools(VSI) Must Have VC_spyglass LINT, CDC and RDC Must Have 0in Must Have Formality and conformal LEC tool Must Have Design and scripting languages: Must Have Verilog and SV Must Have Perl Must Have Python Must Have TCL

#Hiring FPGA Design Engineer Exp-5- 8Years Notice Period- 0 to 15Days Location- Bangalore Job Description: RTL and FPGA design, implementation, and timing closure using Xilinx & Synopsys development tools. Bring up and validate the design in the lab and generate test reports. Perform hardware validation tasks and debug IPs. Read, understand, and modify software drivers and scripts. Skills RTL Design & FPGA Implementation: Verilog, System Verilog, Vivado , ISE, Synplify, Design Compiler FPGA Platforms: Xilinx 7-series, Ultrascale/Ultrascale+, Zynq Toolchain Expertise: Xilinx Vivado, Synopsys DC/PT, ModelSim, VCS Hardware Validation: Bitstream generation, on-board debugging, performance tuning Lab Equipment: Oscilloscopes, logic/protocol analyzers, JTAG debuggers Software & Scripting: C, C++, Python, Perl, TCL, Bash Operating Systems: Linux (device driver understanding), embedded systems Interested candidates share your resume to sreeja.s@sasnee.com ,

Silicon Design Engineer (RTL Design and Development) Responsible for RTL design and development Experience in FPGA VHDL and/or Verilog design, Xilinx technology and tools Perl, Python or TCL Scripting Email id- ta6@nipppondata.com

Lead the architecture, design and development of Processor Core Front end of pipeline units for high-performance IBM Systems. * Architect and design I-Cache, Instruction Fetch, Branch Prediction and Decode units of a high performance processor CPU * Develop the features, present the proposed architecture in the High level design discussions * Estimate the overall effort to develop the feature. * Estimate silicon area and wire usage for the feature. * Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature * Signoff the Pre-silicon Design that meets all the functional, area and timing goals * Participate in post silicon lab bring-up and validation of the hardware * Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing specific CPU unit(eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) * Hands on experience of different Branch Prediction techniques * Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA * Experience with high frequency, instruction pipeline designs * At least 1 generation of Processor Core silicon bring up experience * In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) * Proficiency of RTL design with Verilog or VHDL * Knowledge of at least one object oriented or functional programming language and scripting language.

- Lead the architecture, design and development of Processor Core Vector- Scalar Execution unit for high-performance IBM Systems. - Architect and design Fixed point/Floating point/Vector/SIMD/Crypto instructions of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise - 8 or more years of demonstrated experience in architecting and designing Execution unit of CPU - Hands on experience of implementing Arithmetic/Crypto/SIMD functions - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of instruction dispatch and load/store units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Master's Degree/PhD

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities for this role include: Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes. Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing. Are you expertized in working through complex technical issues and independently building solutions and new methodologies! Explain complex principles in simple terms to broad audiences. Some travel, domestic and international. Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs. Working closely with our key customers on deployment challenges. Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings. Architecture reviews of customer designs. Closely working with AEs to gather top issues blocking their engagement's success. Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U. We don’t need hard workers, just superminds! BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 10 - 15 years of experience. Knowledge of design logic design languages, tool usage, design flow steps required. We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs. ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation. Knowledge of a scripting language like TCL. We need someone self-motivated and dedication to improvement with strong problem-solving skills. Excellent organizational skills, written and verbal English language communication skills. Proficiency in LINUX and Windows environments. The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-HYBRID

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 1-3 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Design and implementation of Interconnect for next gen SoC design. Work with System architects and IP design owners to understand requirements for optimal implementation of interconnect. Prior experience with Arteris Flexnoc/NIC/NoC will be an added advantage. RTL development including tool flows like lint, CDC and synthesis. Knowledge of standard bus protocols mandatory for efficient interconnect design. Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. Provide support to SoC integration and chip level pre/post-silicon debug. Work closely with Functional verification, performance verification and emulation teams to ensure all requirements are verified in pre Silicon environments. Provide post Silicon support related to device performance to validation and SW teams. Qualifications MTech/BTech in EE/CS with hardware engineering experience of 12+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc. ), synthesis/DFT/FV/STA. Ability to understand IP needs and translate to optimal Interconnect design needs. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design -Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Job Details: : Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: A bachelors degree in electrical/computer engineering, Computer Science or related field with 6+ years of experience (or) a masters degree with 4+ years of experience. Preferred Qualification: Relevant experience with skills in SoC flows, RTL integration and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc). Experience in subsystem design and HSIO protocols such as PCIe, UCIe is a plus. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues. Qualifications: Bachelor Degree in Electrical and Electronics Engineering or Masters Degree in Electrical and Electronics Engineering or Computer Engineering with 8+ years experience. Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si. Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PM/Reset/PCIE/DMI/DDR/Mem et.al. Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware. Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation. Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis. Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers. Knowledge in RTL design, VHDL/Verilog is a plus. Strong analytical ability, problem solving and communication skills. Ability to work independently and at various levels of abstraction. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

HI Greetings for the day!!1 I am hiring for TOP MNC for VLSI Design Engineer, check the attached JD for more clarity, kindly revert with below details ON swati@thinkpeople.in Total Experience Rel Exp Current CTC Exp ctc Location Notice period Current org primary skill ; Skills : PD / DV / AMS / DFT / ASIC OR RTL Design: (please mention) JD; Analog Circuit Design Lead : TitleMandatory Skills Experience : 7+ years Responsibilities :1. Experience in entire Analog IP development including circuit design, layout, AMS verification, and characterization.2. Must have led the entire Analog IP development cycle and team.3. Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc.4. Analog/custom layout design in advanced CMOS process.5. Ability to understand design constraints and implement high-quality layouts.6. Conceptualize and implement chip-level mixed signal simulation environments (testbenches, run scripts, etc...).7. Characterization.8. Hands-on experience on lower FINFET technology nodes and design/PPA trade-offs DFT Interface with ASIC design teams to ensure DFT design rules and coverages are met. Generate high-quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. MBIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Work with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting post-silicon debug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary. Preferred Experience : Bachelor's degree in Computer Science, Electrical/Electronics Engineering 7 to 12 years' experience in ASIC/DFT - simulation and Silicon validation. Should have worked in at least one Full chip DFT Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement. In-depth knowledge and hands-on experience in ATPG - coverage analysis. In-depth knowledge of Memory verification, repair and failure root-cause analysis. Experience with any of these tools is required: ATPG - TestKompress, MBIST - MentorETVerify, Simulation - VCS (preferred), ModelSim. Expertise in scripting languages such as Perl, shell, etc. is an added advantage. Ability to work in an international team, dynamic environment with good communication skills. Ability to learn and adapt to new tools, methodologies. Ability to do multi-tasking & work on several high-priority designs in parallel. RTL Role : ASIC RTL Engineer / Digital Design Exp : 7 + Mandatory Skill : • RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory • PCIe/DDR/Ethernet - Any One • I2C,UART/SPI - Any One • Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One • Scripting languages like Make flow, Perl ,shell, python - Any One Good to have : • processor architecture / ARM debug architecture • debug issues for multiple subsystems • create/review design documents for multiple subsystems • Able to support physical design, verification, DFT and SW teams on design queries and reviews Details JD : Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC) Knowledge of synthesis and low power is a plus Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) Good understanding of timing concepts Knowledge of one or more of the interface protocols a. PCIe b. DDR c. Ethernet d. I2C, UART, SPI PD; Floor Planning/Innovus/Fusion Compiler Experience on programming in Tcl/Tk/Perl. Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. DV Must Have: SV/UVM Test Bentch Developement Any Protocols: (PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM) • 8+ years of hands-on DV experience in System Verilog/UVM. •Must be able to own and drive the verification of a block / subsystem or a SOC. •Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. •Must have extensive experience in verification of one or more of the following: •PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM • ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages • Power Aware Simulations using UPF

• 3+ years of solid experience in IP/SoC design • Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts • Good knowledge of Digital Design and RTL development • Hands-on experience with SoC Design, Verilog RTL coding • Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug • Working knowledge of Lint, CDC, PLDRC, CLP etc • Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification • Manage SoC dependencies, planning and tracking of all front-end design related tasks • Working for successful design delivery for the project milestones across the design, verification and physical implementations • Should possess effective communication skills Interested candidates can share their resumes to shubhanshi@incise.in

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor core/cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilities:- Expected to be an SME, collaborate, and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Lead and mentor junior team members.- Conduct code reviews to ensure code quality and adherence to coding standards. Professional & Technical Skills: - Must To Have Skills: Proficiency in Emulation platform like Palladium/Zebu/Veloce/HAPS.- Strong understanding of SOC Architecture- Experience with debugging using any Emulation Palladium/Zebu/Veloce/HAPS platform.- Hands-on experience with ARM (A/M) architecture.- Knowledge of C language. Additional Information:- The candidate should have a minimum of 5 years of experience in Emulation.- This position is based at our Bengaluru office.- A 15 years full-time education is required. Qualification 15 years full time education

We are hiring an FPGA Engineer with experience in RTL design, timing closure, and logic optimization on Xilinx/Intel FPGAs to work on digital signal processing solutions in a collaborative, multidisciplinary engineering environment.

Will be working on the next generation High Performance designs for commercial, Enterprise and Automotive applications Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create architecture and micro-architecture with detailed design documents for some of the components of the design for medium to high complexity functionality Be an individual contributor in the Design Tasks - RTL coding of design, synthesis, CDC analysis, debug, Test development etc. May need to interact with customers to discuss/ understand customers specification requirements, if needed The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide Must have Bachelors/Masters degree in EE/EC/VLSI with 5+ years of relevant experience in the following areas: Hands-on design of data path designs and algorithmic blocks such as Reed Solomon FEC encoder and Decoder as per IEEE 802.3-bj, ck, bs specifications, BCH codes, Parallel CRC computation architectures, MAC SEC engines. Experience in datapath architecture designs for area, latency, throughput trade-offs Knowledge of one or more of protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro/ SD-MMC/ USB/AMBA (AMBA2, AXI) Experience with control path-oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc. Hands-on experience with architecting/ micro-architecture/ detailed design from Functional Specifications Hands-on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background Experience with high speed design greater than 600MHz and with P&R aware synthesis including usage of tools such as Fusion Compiler is a significant plus Experience with Perforce or similar revision control environment Knowledge of Perl/Shell scripts Exposure to quality processes in the context of IP design and verification is an added advantage Ability to work/ Prior experience as a Technical Lead for a small team is a major plus Should be able to mentor and technically lead a team of designers