566 Rtl Design Jobs - Page 12

3+Yrs Exp.Android device platform, Proficient In Kotlin Language knowledge of design patterns like MVP, MMVM, RxJava, and others knowledge of Android SDK, NDK, Android Studio, Gradle, and Lint Knowledge of Flutter or React native will be an advantage Required Candidate profile Candidate will be able to build and integrate android libraries and modules and design-build and maintain high performance reusable java and OOPS concept

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies. This role is based in Noida. But youll also get to visit other locations in India and globe, so youll need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities for this role include: Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes. Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing. Are you expertized in working through complex technical issues and independently building solutions and new methodologies! Explain complex principles in simple terms to broad audiences. Some travel, domestic and international. Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs. Working closely with our key customers on deployment challenges. Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings. Architecture reviews of customer designs. Closely working with AEs to gather top issues blocking their engagement's success. Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U. We dont need hard workers, just superminds! BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 8 - 12 years of experience. Knowledge of design logic design languages, tool usage, design flow steps required. We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs. ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation. Knowledge of a scripting language like TCL. We need someone self-motivated and dedication to improvement with strong problem-solving skills. Excellent organizational skills, written and verbal English language communication skills. Proficiency in LINUX and Windows environments. The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Transform the everyday #LI-EDA #LI-HYBRID

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This role is based in Bengaluru. But youll also get to visit other locations in India and globe, so youll need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! This is your role Deploy Siemens EDA ProFPGA prototyping software and hardware solutions at customers and guide the customers to successful design bring-up Work closely with R&D to solve problems, review product specs, and find good general solutions that improve the overall product Train AEs and customers on the solutionWin pre-sales engagements in cooperation with the technical sales teams Successfully deploy our solutions at early customer sites. This means educating the customer on best practices and tool requirements. It also means working with R&D to make the tool improvements necessary for the customers success. Ensure existing customers maximize the value they receive from the solution by developing and enhancing methodology that exploits the solutions capabilities Ensure customers are kept up-to-date with the latest enhancements Provide customer requirements to R&D and marketing Work with QA and Docs to help them create tests and documentation that will improve our solutions Create examples and tutorials that are shipped with our products. Develop and/or refine methodology employed in creating and using prototypes and maximizing the value of our prototyping solution We dont need superheroes, just super minds! A good understanding of FPGA based hardware prototyping platforms Working knowledge of multi FPGA prototyping flows(Synthesis, partitioning, PnR, runtime and debug) Practical insights into the application and usage of FPGA prototyping systems Knowledge of design mapping, testbench mapping and transactor development Expertise of hardware/software debug solutions related to FPGA prototyping Knowledge of test bench acceleration, ICE and co-model solutions Highly proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification Solid background in Functional Verification, RTL synthesis and PnR flows Conversant with SoC design and architecture concepts Good communication and inter-personal skills. #disw #LI-EDA #LI-Hybrid A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! At Siemens, we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrows reality. Find out more about the Digital world of Siemens here:/digitalminds Siemens Software. Where today meets tomorrow

Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based onImplementation means trying, testing, and improving outcomes until a final solution emerges . Knowledge means exchange discussions with colleagues from all over the world. Join our team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation. We make real what matters. This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will get along with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. You're an Electronics Engineer ( B.Tech / M.Tech ) or related field from a reputed institute You've got phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. You've sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe , Flash, DIMM etc. You are a great teammate, resilient and sincere, Enjoy learning new things and build knowledge base in new area. Weve got quite a lot to offer. How about you This role is based in" Noida " but " youll get the chance to work with teams impacting entire cities, countries- and the shape of things to come. The pace of innovation in electronics is constantly accelerating. To enable our customers to deliver life-changing innovations to the world faster and to become market leaders, we are committed to delivering the worlds most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services. We, at Siemens EDA enable companies to develop better electronic products faster and more efficiently. Our innovative products and solutions help engineers conquer design challenges in the increasingly sophisticated worlds of board and chip design We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. About the role: We are seeking a highly motivated and detail-oriented Application Support Engineer to join our dynamic, fast paced and growth-mindset team. In this role, you will be focused on supporting the Questa verification products, specifically in Verification IP line of products. In this position, you will be working closely with the product engineering team, field application engineers and customers. As an ASE, you will be solving some of our customers complex design, testbench and environment issues in the domain of functional verification. You will also be working closely on creating knowledge-based content and providing expertise on the Questa platform. You will work with multiple customers to understand their challenges and flow and be involved in technical presentations, training, evaluation and competitive benchmarking. You will part of the larger application support engineering organization and will be interfacing regularly with the North American and PACRIM teams. Minimum Qualifications BS Electronic/Computer Engineering from an accredited institution Minimum of 2+ years of Digital Design/Verification experience Knowledge of VHDL or Verilog, or SystemVerilog RTL languages for ASIC or FPGA design Experience with ASIC or FPGA hardware design and implementation using RTL tool flows and methodologies Knowledge of Windows and Linux OS Self-motivated, flexible, self-disciplined, and comfortable in a dynamic, quick-moving environment. Strong interpersonal and communications skills with the ability to quickly establish rapport and credibility with our customers, sales, and product teams. Strong oral, and written communication, and presentation skills Excellent organizational and time management skills Preferred qualifications MS Electronic/Computer Engineering Knowledge of UVM and System Verilog for Verification Clock Domain Crossing (CDC), Static and Formal Verification- Formal Applications Working knowledge of Working knowledge of Questa-Modelsim, VCS (Synopsys), NCSim (Cadence) or Aldec simulators. Knowledge of C/C++ programming languages Demonstrated proficiency with Object-Oriented Programming experience in test bench architecture and design Knowledge of scripting languages (e.g., Shell, Tcl, Perl, Python) Knowledge of CDC, low power and formal methodologies. Location Noida/ Bangalore Why us Working at Siemens Software means flexibility - Choosing between working at home and the office at other times is the norm here. We offer great benefits and rewards, as you'd expect from a world leader in industrial software. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! Siemens Software. Transform the Everyday #Li-EDA #LI-HYBRID

As a member of DFT team , you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features. Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in processor flow and post silicon validation

* Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering.* Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment.* Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU.* Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments.* Develop verification test plan for both functional and performance verification including the estimation for coverage closure.* Support higher level core/system simulation environment.* Participate in post silicon lab bring-up and validation of the Hardware.* Lead , guide ,mentor a team of engineers and represent them at global forums.* Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement.* Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. * Hands-on on Power Management domain Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 4 years or more experience in functional verification of processors, demonstrating a deep understanding of power management unit verification.* Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. * Experience with high frequency, instruction pipeline designs* At least 1 generation of Processor Core silicon bring up experience* In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs)* Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design* Proficiency in C++, Python scripting or similar object oriented programming languages.2:37Y Annapurna Bharathi Preferred technical and professional experience * Knowledge of instruction dispatch and Arithmetic units.* Knowledge of test generation tools and working with ISA reference model.* Experience with translating ISA specifications to testplan.* Knowledge of verification principles and coverage.* Understanding of Agile development processes. * Experience with DevOps design methodologies and tools.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -12+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. . Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications,processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages.. Preferred technical and professional experience Knowledge of verification principles and coverage. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. . Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications,processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages.. Preferred technical and professional experience Nice to haves - Knowledge of verification principles and coverage. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.

Responsibilities: Should have good understanding of SoC design flow Hands-on expertise in writing RTL in Verilog and System Verilog (optional VHDL) language, SoC level RTL integration ,Linting, CDC checks, STA ,constraints, UPF

We are seeking a Senior CAD Engineer with 10+ years of experience to join our team in Bangalore. The ideal candidate will be responsible for deploying and supporting front-end tools. Key Responsibilities Deploy and support tools such as RTL simulators , low-power tools , and static RTL checkers . Develop scripts to automate regression and debug flows. Manage CI/CD processes. Interface with EDA vendors . Support global teams across various geographies. Ensure the smooth functioning of CAD tools and methodologies. Required Skills & Experience 10+ years of experience as a CAD Engineer . Proficiency in scripting languages like Python , Bash , and Makefiles . Experience with Linux system administration . Hands-on experience with version control tools such as Git and Mercurial . Strong knowledge of ASIC flows and standard CAD tools . Excellent problem-solving and communication skills.

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com call me :7995220108. Client Name: Proxelera Industry: SEMICON Position Name DFT MBIST Engineer Position type: Permanent Total Exp: 3 to 5 Years HBTS Budget: Open No of Position: 1 Notice Period: Immediate to 15days Work Location: Hyderabad Job Description Must have: "The person is responsible for ensuring the integrity of a design by analyzing signal connectivity, specifically related to Design for Testability (DFT) features, utilizing Spyglass tools to identify and report potential violations within the test logic. Expertise should include and not limited to the following Strong understanding of digital circuit design principles and timing analysis concepts Experience with RTL design, synthesis Proficiency in scripting languages like TCL, Perl, or Python for automation Excellent problem-solving and debugging skills Strong communication and teamwork abilities to collaborate with cross-functional teams " AMD (Dont Share AMD Profiles) Preferred candidate profile

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL Lead Engineer Location: Mysore Work Type: Onsite Job Type: Full time Job Description: Strong proficiency in Verilog and SystemVerilog, with experience in designing finite state machines (FSMs), clocking, reset strategies, and bus architectures. Capable of developing microarchitecture from specification to RTL, including block and subsystem design, as well as thorough documentation. Skilled in RTL debugging, with working knowledge of synthesis processes and timing closure. Familiar with industry protocols and integration, such as AXI, APB, AHB, PCIe, SoC integration, design-for-test (DFT), and power domain management. Good to Have Skills: Experience with scripting and automation using Python, Tcl, or Perl to streamline design flows. Demonstrated leadership and collaboration abilities, including mentoring, cross-functional communication, AMS integration, UPF-based low-power design, post-silicon debugging, and a proactive approach to automation TekWissen Group is an equal opportunity employer supporting workforce diversity.

Synthesis and Timing engineer to participate in the development of large SOCs with multiple physical blocks and 300+ clock domains. He/She must be high energy candidate with strong written and verbal communication skills, technically strong to find solutions and help the team both inside and outside the organization. REQUIRED SKILLS: RTL Design Quality checks, mainly Lint Automation using Python and TCL 5years+ experience, so not an NCG KEY RESPONSIBILITIES: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency. Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Work with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) flows Requires a mix of SDC knowledge, EDA tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) PREFERRED EXPERIENCE: Worked with EDA tools that enable RTL quality checks Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Ability to multitask and grasp new flows/tools/ideas Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. ACADEMIC CREDENTIALS: Bachelor's degree or Masters degree with 5years+ experience.

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 310 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Skills Must have 1 position6+y, 1 position4+y Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash... Proficiency in Unix environment. Good communication skills Nice to have Bachelor's/Master's in ECE Other Languages EnglishB2 Upper Intermediate Seniority Regular

RTL Design, Debugging Skills, RTL Integration process, 5G Telecom domain experience Mandate. 5G Radio

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Design For Testability - DFT. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Design For Testability - DFT. Experience3-5 Years.

Role Purpose The purpose of the role is to support process delivery by ensuring daily performance of the Production Specialists, resolve technical escalations and develop technical capability within the Production Specialists. Do Oversee and support process by reviewing daily transactions on performance parameters Review performance dashboard and the scores for the team Support the team in improving performance parameters by providing technical support and process guidance Record, track, and document all queries received, problem-solving steps taken and total successful and unsuccessful resolutions Ensure standard processes and procedures are followed to resolve all client queries Resolve client queries as per the SLAs defined in the contract Develop understanding of process/ product for the team members to facilitate better client interaction and troubleshooting Document and analyze call logs to spot most occurring trends to prevent future problems Identify red flags and escalate serious client issues to Team leader in cases of untimely resolution Ensure all product information and disclosures are given to clients before and after the call/email requests Avoids legal challenges by monitoring compliance with service agreements Handle technical escalations through effective diagnosis and troubleshooting of client queries Manage and resolve technical roadblocks/ escalations as per SLA and quality requirements If unable to resolve the issues, timely escalate the issues to TA & SES Provide product support and resolution to clients by performing a question diagnosis while guiding users through step-by-step solutions Troubleshoot all client queries in a user-friendly, courteous and professional manner Offer alternative solutions to clients (where appropriate) with the objective of retaining customers and clients business Organize ideas and effectively communicate oral messages appropriate to listeners and situations Follow up and make scheduled call backs to customers to record feedback and ensure compliance to contract SLAs Build people capability to ensure operational excellence and maintain superior customer service levels of the existing account/client Mentor and guide Production Specialists on improving technical knowledge Collate trainings to be conducted as triage to bridge the skill gaps identified through interviews with the Production Specialist Develop and conduct trainings (Triages) within products for production specialist as per target Inform client about the triages being conducted Undertake product trainings to stay current with product features, changes and updates Enroll in product specific and any other trainings per client requirements/recommendations Identify and document most common problems and recommend appropriate resolutions to the team Update job knowledge by participating in self learning opportunities and maintaining personal networks Deliver NoPerformance ParameterMeasure1ProcessNo. of cases resolved per day, compliance to process and quality standards, meeting process level SLAs, Pulse score, Customer feedback, NSAT/ ESAT2Team ManagementProductivity, efficiency, absenteeism3Capability developmentTriages completed, Technical Test performance Mandatory Skills: FPGA Design. Experience5-8 Years.

The ASIC Front-End Head is responsible for leading the front-end design team, ensuring high-quality Application-Specific Integrated Circuit (ASIC) designs, and driving innovation in digital chip development. This role requires expertise in RTL design, verification, synthesis, and architecture development, along with strong leadership and strategic planning skills. Key Responsibilities Technical LeadershipDefine and implement best practices for front-end ASIC design, ensuring efficiency and performance. Architecture & DesignOversee the development of digital circuits, including RTL coding, synthesis, and timing analysis. Verification & ValidationEnsure robust design verification methodologies using tools like UVM, SystemVerilog, and simulation frameworks. Cross-Team CollaborationWork closely with back-end design, physical design, and fabrication teams to optimize chip performance. Innovation & R&DStay updated with emerging semiconductor technologies and drive research initiatives. Mentorship & Team DevelopmentGuide and mentor engineers, fostering a culture of learning and technical excellence. Technical Project ManagementOversee front-end development timelines, ensuring timely delivery of high-quality designs. Required Qualifications EducationBachelor's or Master's degree in Electrical/Electronics Engineering, VLSI Design, or a related field. Experience15+ years in ASIC front-end design, with a proven track record of successful projects. Technical Skills: Expertise in HDLs (Verilog, VHDL), synthesis tools, timing analysis, and low-power design techniques. Leadership & CommunicationAbility to lead teams, manage projects, and communicate effectively with stakeholders. Problem-SolvingAnalytical mindset with a passion for optimizing digital designs for performance and efficiency. Reinvent your world.We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) Mandatory Skills: ASIC Design. Experience5-8 Years.

Lead the architecture and RTL design of complex digital blocks and subsystems for ASICs or SoCs Develop RTL using Verilog/SystemVerilog to meet functional and performance specifications Review micro-architecture and provide design solutions optimized for power, performance, and area Work closely with the verification team to ensure thorough test coverage and efficient debugging Collaborate with synthesis, STA, and physical design teams for design closure

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL design Location : Bangalore Work Type: Onsite Job Type: Full time Job Description: 7+ years of RTL design experience with 4+ years focused on SoC integration Expert knowledge of industry-standard bus protocols (AXI, AHB, APB, etc.) Proven experience with large-scale integration challenges in complex SoCs Strong understanding of clock synchronization strategies and metastability management Deep knowledge of power management techniques and implementation Experience with integration-specific verification methodologies Proficiency in debugging complex system-level issues TekWissen Group is an equal opportunity employer supporting workforce diversity.